Single event crosstalk prediction in nanometer technologies

Selahattin Sayil • Vijay K. Boorla

Received: 17 April 2011 / Revised: 19 July 2011 / Accepted: 6 August 2011 / Published online: 20 August 2011

� Springer Science+Business Media, LLC 2011

Abstract As CMOS technology continues to scale down,

circuits become increasingly more sensitive to transient

pulses caused by single event (SE) particles. On the other

hand, coupling effects among interconnects can cause

single event transients to contaminate electronically unre-

lated circuit paths which may increase the SE susceptibility

of CMOS circuits. The coupling effects among intercon-

nects need to be considered in single event hardening,

modeling and analysis of CMOS logic gates due to tech-

nology scaling effects that increase both SE vulnerability

and crosstalk effects. This work, for the first time, proposes

an SE crosstalk noise estimation method for use in design

automation tools. The proposed method uses an accurate

4-p model for interconnect and correctly models the effect

of non-switching aggressors as well as aggressor tree

branches noting the resistive shielding effect. The SE

crosstalk noise expressions derived show very good results

in comparison to HSPICE results. Results show that aver-

age error for noise peak is about 5.2% while allowing for

very fast analysis in comparison to HSPICE.

Keywords Single event transients � Single event

crosstalk � Coupling noise � Closed form modeling

1 Introduction

The International Technology Roadmap for Semi-conduc-

tors (2009) has pointed to signal integrity in chips as a

major challenge [1]. Nanometer circuits are increasingly

becoming more sensitive to interferences coming from

these multiple noise sources. Among them, radiation-

induced soft errors in commercial nanometer CMOS

technologies have recently become a growing concern [2].

Terrestrial soft errors in memory have been a very well

known problem [3]. However, due to increasing clock

frequencies and shrinking feature sizes soft errors are now

affecting CMOS logic. It has been predicted that for 45 nm

technologies and below the majority of the observed radi-

ation induced soft failures will be due to transients that will

occur in combinational logic (CL) circuits [2].

For commercial chips at ground level, soft errors are

mainly induced by alpha particles emitted from radioactive

decay of uranium and thorium impurities located within the

chip packaging and due to atmospheric neutrons [3]. When

an energetic radiation particle strikes the sensitive area

within a combinational circuit such as the depletion region

of transistor drains or a reverse-biased p-n junction, many

hole-electron pairs can be created due to ionization

mechanism. These free carriers can later drift under the

electric field creating a transient voltage pulse. This tran-

sient is named as single event transient (SET) and can pass

through a series of CL gates and reach to storage elements

under certain conditions. If the generated pulse arrives at

the storage element during its latching window, incorrect

data can be stored resulting in soft error. This is also

termed as single event upset (SEU).

With increasing coupling effects, an SET pulse gener-

ated on a circuit node is no longer limited to the logic path

existing between the hit node and a latch. The interconnect

coupling effects can cause SETs to contaminate electron-

ically unrelated circuit paths which can in turn increase the

‘‘SE Susceptibility’’ of CMOS circuits to SETs [4–6].

Although SETs are considered as the main reason for

radiation induced soft errors in CL, for mission-critical

S. Sayil (&) � V. K. Boorla

Drayer Department of Electrical Engineering, Lamar University,

P.O. 10029, Beaumont, TX 77710, USA

e-mail: ssayil@lamar.edu

123

Analog Integr Circ Sig Process (2012) 72:205–214

DOI 10.1007/s10470-011-9748-9

high-reliability applications such as avionics [7], medical

systems [8], and etc., additional sources such as SE crosstalk

effects must also be included in analysis in addition to SETs.

Advancements in lithographic process cause circuits to

become more crowded leading more reduction of distances

among interconnects. The interaction caused by parasitic

coupling between wires, which is generally known as

crosstalk, may cause undesired effects such as positive and

negative glitches, overshoot, undershoot, signal delays or

even delay reduction [9–11]. If crosstalk effects on the

victim (affected) net are large, they can propagate into

storage elements that connected to victim line and can

cause permanent errors.

It is no longer just the normal signal switching events on

aggressor (affecting) lines that are responsible for such

crosstalk effects. As technology scaling continues, the

charge deposited due to an SE particle on aggressor line

may also create increasing cross-coupling noise effects,

and in some cases the effects can be larger than a normal

switching induced crosstalk [6].

With increased coupling effects among interconnects,

the SET generated on a circuit node may affect multiple

logic paths due to strong coupling among wires. Figure 1

shows aggressor victim pair along with its drivers and

receivers. Since inputs of both drivers are held at logic 1,

the outputs are normally at logic 0. An SE hit at the drain of

OFF PMOS transistor of the inverter driver causes output

to go towards logic 1 (or 1.2 V) for some pulse duration.

The SE transient voltage created, in turn, can affect the

victim line through coupling capacitor Cc inducing SE

crosstalk noise on the victim.

The cross-coupling effects produced by SE hits can

violate noise margins of gates connected to affected line

and may result in logic errors. Serious effects may occur if

the affected line is somewhat important such as a clock line

[6]. Crosstalk noise effects on a clock network may have

multiple effects on areas much farther from originating

source of the SE crosstalk point. An upset can be

interpreted as a clock edge potentially causing many dif-

ferent bits to be stored incorrectly (multiple upsets).

Balasubramanian et al. [4] have shown that SE tran-

sients can produce crosstalk effects on neighboring lines

that can induce logic level state changes for interconnects

as small as 100 lm on technologies 90 nm and lower. The

work has studied crosstalk effects induced by SE transients

for various interconnect lengths and deposited charges up

to 1 pC using a simple lumped RC model for interconnect.

Later work in [5] has experimentally measured the SE

induced crosstalk in a 90 nm process and proved the

existence of the problem.

Recent work in [6] studied the SE crosstalk effects using

a more accurate distributed model for interconnect, and

suggested hardening techniques for SE crosstalk. The work

also showed that aggressor driver sizing technique that is

normally used in conventional crosstalk mitigation has an

opposite effect for SE crosstalk mitigation.

Although, previous work studied the problem in detail

using simulations, there has not been any work in the

predicting the SE crosstalk noise effects. In this work, the

crosstalk noise generated on neighboring line due to an

SET pulse will be calculated for the first time to our

knowledge. The formulas developed will provide good

basis to gain insight into the effects of SE pulse transients

on the crosstalk noise. With closed-form expressions, the

crosstalk pulse dependency on various design parameters

can be observed via sensitivity expressions obtained.

Traditional SPICE simulators can be used to estimate

crosstalk effects in signal lines. While results are accurate,

due to density of interconnect lines, these simulations are

time inefficient [9–11]. A rapid and accurate crosstalk

noise estimation alternative is needed to ensure acceptable

signal integrity in a limited design cycle time so that one

can quickly verify if a given wire routing solution will not

lead to logic failures caused by the coupled noise.

Here, using a distributed model for interconnect, we first

analyze SE crosstalk effects and then compare to normal

switching crosstalk to see if these effects important. An

accurate representation of a distributed RC circuit can be

obtained by using multiple-p segments. Accuracy of the

model increases as the number of segments increase, and

the transient behavior approaches that of a distributed RC

line. Kawaguchi and Sakurai have reported that the error in

simulating delay of the distributed RC line by using 5-psegment is less than 1% for almost all cases [12].

Nevertheless, researchers often use the 10-p model, to

represent the distributed RC line in Spice simulations when

comparing the accuracy of closed form expressions for

crosstalk [12–14]. In this work, we use an even more

accurate 20-p model for interconnect to represent RC dis-

tributed behavior. The coupling capacitances are also dis-

tributed in this model as can be seen in Fig. 2.Fig. 1 Single event crosstalk noise (lumped wire model is for

demonstration only)

206 Analog Integr Circ Sig Process (2012) 72:205–214

123

Two parallel interconnects that are on the intermediate

layer in 65 nm technology are considered with wire

dimensions taken as follows: the width (W), spacing (S) is

0.14 lm, and wire thickness T is 0.35 lm [15]. A wire

length of 500 lm is chosen for the intermediate wire.

Inductance effects in on-chip interconnects becomes

increasingly important with smaller rise times and lower

wire resistance especially in global interconnects. However

for most on-chip lines or interconnects, capacitive effects

are still the dominant factor [9–11].

In our work, we assume that the input rise time as 33 ps,

which is the 10% of signal period at 3 GHz clock fre-

quency. For the intermediate wire parameters and driver

sizes considered, we found that inductance effects are not

important. Hence, we ignore inductance effects and assume

capacitive coupling as the dominant mechanism for

crosstalk in our work.

An SE hit was simulated at the output of the first

inverter using a double exponential current pulse [3] that is

given by:

IðtÞ ¼ Q

ta � tbðe�t=ta � e�t=tbÞ ð1Þ

where, Q is the charge (positive or negative) deposited by the

particle strike, ta is the collection time constant of the p–n

junction, tb is the ion-track establishment time constant.

The time constants ta and tb are dependent on process

technology and are taken as 100 and 5 ps, respectively

based on [16]. Alternatively, the single exponential current

model given in [17] may also be used. Researchers in [15,

18] mention that the single pole model can be replaced by

double exponential current pulse model for SEUs without

loss of generality. In this work, the double pole represen-

tation has been used as an approximation to waveforms

seen in mixed-mode simulations.

In order to analyze the SE induced crosstalk noise, both

the aggressor and victim driver inputs are connected to

‘‘logic high’’. In this case, normally aggressor driver output

would be at ‘‘logic low’’ but it would be taken to ‘‘logic

high’’ if there is a sufficient SE hit charge on output node of

the driver.

It is assumed that aggressor and victim driver sizes are

0.26/0.13 lm (Wp/Wn) and the loads at the end of the wires

are minimum sized identical inverters. Here, the receiver

gates are taken as minimum size in order to maximize the

crosstalk noise effects. At the end of the line, receiver gates

act as load capacitances and contribute to the stability of

aggressor and victim lines. Hence, smaller driver sizes are

chosen to maximize the crosstalk noise.

Figure 3 compares the SE induced coupling noise to the

normal aggressor switching induced crosstalk on the victim

line for a VDD of 1.2 V. Varying deposited charges in

between 25 and 150 fC were selected in our comparison.

As shown in Fig. 3, the SE crosstalk amplitude can easily

exceed normal crosstalk amplitude for SEU hit charges

above 60 fC and it can be as high as four times the regular

crosstalk noise peak for charges near 150 fC. This is

because of the fact that an SET waveform rises much

rapidly compared to normal aggressor waveform, and in

turn induces more coupling noise on the victim line.

We have also studied the effect of different wire lengths.

For a fixed deposited charge, when we decreased the wire

Fig. 2 Simulation setup used in

calculating the single event

induced crosstalk noise

Fig. 3 Switching versus single event induced crosstalk noise at

varying deposited charge

Analog Integr Circ Sig Process (2012) 72:205–214 207

123

length, the SE coupling noise width decreased and became

less comparable to regular crosstalk noise width. For longer

lengths, the width of the noise pulse has increased. For both

cases, the SE Crosstalk Noise amplitude, on the other hand,

remained relatively constant. In conclusion, although a given

net passes the normal crosstalk noise check, it may still pose

a threat if SE crosstalk effects are not properly considered.

This paper is organized as follows. Section 2 explains

the 4-p model template that is used in SE crosstalk cal-

culation. In Sect. 3, the equivalent capacitance formula for

passive aggressor and the victim line is derived. Modeling

of aggressor RC trees and branches are discussed in Sect. 4.

The aggressor coupling voltage due to an SE particle hit is

calculated in Sect. 5 noting the loading effects of victim

and possible aggressor tree branches.

In Sect. 6, the SE crosstalk voltage at victim-end is

formulated and the proposed SE crosstalk model is

explained in detail. The model has been tested extensively

using 1,000 randomly generated circuits and results are

verified using HSPICE. These results are shown in Sect. 7

in tabular form. Finally, we conclude in Sect. 8.

2 Single event crosstalk modeling

The proposed SE crosstalk model uses a 4-p interconnect

model in which both the victim and aggressor nets are

modeled using the 2-p circuits [10, 11]. Figure 4 shows the

4-p template used in SE crosstalk calculation.

In this model, RC parameter values are calculated based

on technology and the geometric information from

Fig. 4(a). The coupling node (node 2) is set to be the center

of the coupling portion of the victim net. We assume the

upstream and downstream resistance/capacitance at node 2

to be R1a/Cua and R2a/Cda, respectively. Similarly for vic-

tim net, let’s assume upstream and downstream resistance/

capacitance at node 5 to be R1v/Cuv and R2v/Cdv, respec-

tively. Then, for aggressor and the victim line:

C1a ¼ Cua=2;C2a ¼ CuaþCdað Þ=2 and; Cla ¼ Cda=2þClda

C1v ¼ Cuv=2;C2v ¼ CuvþCdvð Þ=2 and; Clv ¼ Cdv=2þCldv

where, Clda and Cldv represent the load capacitances for

aggressor and victim lines, respectively.

Inductance effects in on-chip interconnects becomes

increasingly important with smaller rise times and lower

wire resistance especially in global interconnects. How-

ever, for most on-chip lines or interconnects, capacitive

effects are still the dominant factor [9–11]; hence induc-

tance is ignored in our modeling.

We assume that both victim and aggressor driver inputs

are at logic 1 and a positive charge deposition occurs on

aggressor driver output due to an SE particle. It is also

assumed that the SET voltage generated due to particle

strike at aggressor driver output does not exceed value of

VDD - VTN (where VTN is NMOS device threshold),

hence both the aggressor and victim drivers can be repre-

sented approximately by holding resistances of ON

(NMOS) transistors since these transistors stay in non-

saturation region [19, 20]. This approximation may be

correct for most particle deposited charge levels seen in

terrestrial environment. In addition, the coupling capaci-

tances effectively couple deposited charge into victim

network before aggressor line gets a chance to rise above

VDD - VTN as observed from our simulations.

In Fig. 5, the effective resistances Rda and Rdv model the

holding resistances of aggressor and victim drivers,

respectively. Each holding resistance models the effect of

on transistors (NMOS) that dissipate the charge and restore

the node to its original logic value.

A single event hit has been simulated at the output of the

aggressor driver using a double exponential current source

given earlier. The multiline crosstalk model proposed in

[11] has been adopted for SE crosstalk estimation in this

work. In this model, the loading effects of non-switching

(passive) aggressors and aggressor tree branches are

Fig. 4 The 4-p model for two coupled interconnects

Fig. 5 Single event crosstalk calculation using the 4-p template

circuit

208 Analog Integr Circ Sig Process (2012) 72:205–214

123

correctly modeled using equivalent capacitances. The

model is advantageous over techniques which simply use

lumped capacitors [10] at coupling/branching point. These

equivalent capacitance values are derived noting the

aggressor waveform and the resistive shielding effect.

In our work, the line where the SET generates due to

particle strike is taken as the active aggressor, while any other

nets coupled to the victim are considered as passive aggressor

lines. It is also assumed that none of the lines switch during

particle hit so that SE crosstalk noise is generated.

Another advantage of our model is the limited use of

dominant pole approximation. In [10], the direct transfer

function between aggressor input and victim output is

calculated, then dominant pole approximation is hired on

the whole transfer function to reduce complexity. How-

ever, too much use of dominant pole approximation redu-

ces model accuracy in great amount. In our model, the

dominant pole approximation is used only moderately in

between aggressor coupling node and victim line output

which results in better accuracy. For this, the aggressor

waveform at the coupling node is first formulated and then

entered to the transfer function between the coupling node

and the victim output to obtain noise voltage.

3 Passive aggressor modeling

A victim line can be coupled to many non-switching

(passive) aggressors. Previously, the loading effect of a

passive aggressor is simply taken as a coupling capacitor at

victim coupling point [10]. However, a passive aggressor

follows victim waveform and contributes to the stability of

the victim line. Therefore, equivalent load capacitance at

the victim coupling point is less than coupling capacitance

and can be formulated using coupling/branching admit-

tance concept [11, 21]. Referring to Fig. 6, the equivalent

capacitance formula for a passive aggressor is derived

assuming an exponential aggressor waveform at victim

coupling node V. For this, the passive aggressor is first

reduced to the simple circuit shown in Fig. 6, where [11]:

R0a ¼ Rda þ R1a ð2Þ

C0a ¼ C2a þ Cla þ ðR2da=ðRda þ R1aÞ2ÞC1a ð3Þ

Then, for matching purposes, the victim waveform is

assumed to be a normalized exponential voltage. Referring

to Fig. 7, the currents coming from victim node should be

same for both cases:

I ¼ CcdVVðtÞ

dt� dVA tð Þ

dt

� �¼ Ceq

dVV tð Þdt

ð4Þ

Assuming zero initial condition and an exponential

waveform, we can calculate the equivalent capacitance, Ceq

by integrating (3) over 0 B t B 5tr interval (where tr is the

exponential rise time constant). Here, it is assumed that the

exponential waveform reaches its final value at t = 5tr.

Then, the equivalent capacitance value for a passive

aggressor is given by:

Ceq ¼ Cc 1� VAð5trÞ½ � ð5Þ

Again referring to Fig. 7, we can also write a KCL

equation at node A, giving:

CcdVVðtÞ

dt

� �¼ ðCc þ C0aÞ

dVAðtÞdtþ VAðtÞ

R0að6Þ

VAðtÞ ¼CcR0a

tr � R0aðCc þ C0aÞe�

ttr � e

�tR0aðCcþC0aÞ

h ið7Þ

Inserting VA(5tr) in (4), Ceq formula is given as:

Ceq ¼ Cc 1þ CcR0atr � R0aðC0a þ CcÞ

� e�5tr

R0aðC0aþCcÞ

� �ð8Þ

A passive aggressor coupled to the victim line can now

be represented by an equivalent capacitor using (8) and this

capacitor updates the value of C2v at node 5. Finally, the

circuit would reduce to the one in Fig. 5.

4 RC trees and branches

Most previous work treats aggressor net branches simply as

lumped capacitances at branching point [9, 10]. However,

the capacitance seen at the branching node is less than the

total branch capacitance due to resistive shielding effect

[11], and hence needs to be correctly formulated.

For this, the tree branches are reduced to a simple -

model following the moment matching method as

Fig. 6 A non-switching aggressor net coupled to the victim line

Fig. 7 Passive aggressor line reduction

Analog Integr Circ Sig Process (2012) 72:205–214 209

123

demonstrated in [21]. This model is then reduced to an

equivalent branching capacitance Ceq-br (Fig. 8) consider-

ing an exponential waveform on input node A.

We equate the currents on node A for both circuits:

Ceq�br

dVA tð Þdt

¼ CadVAðtÞ

dtþ Cb

dVB tð Þdt

ð9Þ

Assuming a rising exponential voltage at input node and

zero initial condition, we can obtain an equivalent

branching capacitance after integrating both sides of

above equation over 0 B t B 5tr time interval:

Ceq�br ¼ Ca þ CbVB 5trð Þ ð10Þ

Then, after applying KCL on node B, one obtains:

dVB tð Þdtþ VB tð Þ

RCb¼ 1� e�t=tr

RCbð11Þ

Upon solving the differential equation and inserting t = 5tr

VBð5trÞ ¼ 1þ RCb

tr � RCbe�5tr=RCb ð12Þ

Finally, this value can be inserted in (10) giving:

Ceq�br ¼ Ca þ Cb 1þ RCb

tr � RCbe�5tr=RCb

� �ð13Þ

5 Aggressor waveform calculation at coupling node

In the proposed model, the aggressor waveform at the

coupling node is first calculated and then entered to the

transfer function between the coupling node and the victim

output to obtain victim noise voltage.

In order to calculate aggressor coupling node waveform

correctly on node 2 (see Fig. 5), the victim loading effect

needs to be included. For this, the victim line is first

reduced into an equivalent capacitor Ceqv using the quiet

aggressor/victim net reduction techniques as summarized

in Sect. 3.

After obtaining Ceqv, a source transformation is also

implemented on aggressor input giving the final circuit

shown in Fig. 9. As shown in Fig. 9, the voltage source

resulting from source transformation has been represented

using two voltage sources in series. This is merely done for

convenience in calculation. The sources Vin1 and Vin2 are

given as:

Vin1 ¼QRda

ta � tbð1� e�t=tbÞ ð14Þ

and,

Vin2 ¼QRda

tb � tað1� e�t=taÞ ð15Þ

respectively.

We consider one input at a time (Vin1 or Vin2) using

superposition to find the coupling node waveform. For this,

the aggressor branches after the coupling point are also

reduced to an equivalent capacitance Creq using the tree

branch reduction techniques given earlier (see Fig. 10).

The equivalent branching capacitance for Vin1 (Creq-b) is

given by:

Creq�b ¼ C2a þ Cla 1þ R2aCla

tr � R2aClae�5tb

R2aCla

� �ð16Þ

Figure 11 shows the resulting circuit for coupling node

voltage calculation (shown for Vin1 input). The transfer

function between the input and coupling node 2 is calcu-

lated as:

V2ðsÞVinðsÞ

¼ 1

sta1 þ 1ð17Þ

where,

ta1 ¼ C1aRda þ ðCeqv þ Creq�bÞðRda þ R1aÞ

We note that ta1 in fact is the Elmore delay between the

input and node 2. Finally, the delayed waveform at

coupling node for the first input is calculated to be:

V 02ðtÞ ¼QRda

ta � tb1� e�t=tbn

� �ð18Þ

where,

Fig. 8 Obtaining an equivalent branching capacitanceFig. 9 Decoupled aggressor line for coupling node voltage

calculation

Fig. 10 Tree branch reduction on right part of aggressor net

210 Analog Integr Circ Sig Process (2012) 72:205–214

123

tbn ¼ tb þ ta1

Similarly, the delayed waveform at coupling node due to

Vin2 (Fig. 9) can be calculated as:

V 002 ðtÞ ¼QRda

tb � tað1� e�t=tanÞ ð19Þ

where,

tan ¼ ta þ ta2;

and

ta2 ¼ C1aRda þ ðCeqv�a þ Creq�aÞðRda þ R1aÞ

Finally, the coupling waveform is given by:

V2ðtÞ ¼ V 02ðtÞ þ V 002 ðtÞ¼ QRda

ta � tbð1� e�t=tbnÞ þ QRda

tb � tað1� e�t=tanÞ ð20Þ

6 Output voltage formulation

In output voltage formulation, the aggressor waveform at

coupling location is entered to the transfer function to

calculate victim noise as shown in Fig. 12.

Referring to Fig. 12, we have,

1

Z1

¼ 1

Rdþ sC1v ð21Þ

1

Z2

¼ 1

R2v þ sClvþ sC2v þ

1

Z1 þ R1vð22Þ

V5ðsÞ ¼Z2

Z2 þ 1=sCcV2ðsÞ ð23Þ

VoutðsÞ ¼1

sClvR2v þ 1V5ðsÞ ð24Þ

After inserting (23) in (24), we hire dominant pole

approximation method to reduce complexity of the transfer

function [22, 23] and obtain:

VoutðsÞV2ðsÞ

¼ ssx

ssv þ 1ð25Þ

where,

sv ¼ RdðCc þ C1v þ C2v þ ClvÞ þ R1vðCc þ C2v þ ClvÞþ R2vClv

and,

sx ¼ ðRd þ R1vÞCc

Finally coupling node waveform in (20) can be inserted

in (25) to finally obtain the Vout expression:

VoutðsÞ ¼ssxQRda

ðssv þ 1Þðta � tbÞ1

sþ 1=tan� 1

sþ 1=tbn

� �

ð26Þ

In time domain, the victim output noise waveform

would be:

VoutðtÞ

¼ QRdasx

ta � tb� e�t=tbn

tbn � sv� e�t=tan

tan � svþ

tbn � tan

� e�t=sv

tan � svð Þ tbn � sv

� " #

ð27Þ

Noise peak has been traditionally used as a metric to

determine if the noise is at an acceptable level. In order to

calculate the noise peak, the derivative of (27) should be set

zero to find the time instant where the maximum occurs.

However, the above equation contains three exponential

terms and hence; it is difficult to find a closed-form

expression for amplitude. On the other hand, one can obtain

a function f(t) which can be used in Newton’s iteration

method to solve for the tpeak where noise peak Vpeak occurs:

f ðtÞ ¼ dVout

dt

¼ QRdasx

ðtb � taÞe�t=tbn

tbnðtbn � svÞ� e�t=tan

tanðtan � svÞ

�

þ ðtbn � tanÞe�t=sv

svðtan � svÞðtbn � svÞ

�

¼ 0 ð28Þ

Then, tpeak can be found using:

tpeakkþ1¼ tpeakk

� f tpeakk

� =f 0 tpeakk

� ð29Þ

This method converges very rapidly after little iteration. The

noise peak voltage Vpeak is found after inserting tpeak in (27).

Fig. 11 Aggressor waveform calculation at coupling node

Fig. 12 Output voltage calculation

Analog Integr Circ Sig Process (2012) 72:205–214 211

123

A similar victim noise expression can also be obtained

for the case that a negative particle strike occurs at the

output of aggressor driver. In this case, since both driver

inputs are at logic 0, the holding resistances of PMOS

transistors should be utilized in noise formulation.

6.1 Summary

The following steps summarize for the proposed model:

1. Determine the particle charge based on the environ-

ment, find constants ta and tb that is needed to model

the SE particle strike.

2. Calculate the equivalent capacitance value Ceq-a for

each passive aggressor that is coupled to victim line.

This capacitor is then placed in parallel at victim

coupling node.

3. Reduce any aggressor tree branches using an equiva-

lent branching capacitance Ceq-br at branching point.

4. Repeat the same procedure in step (2) for the victim

line, and find an equivalent capacitance value Ceq-v.

This capacitor updates the value of C2a at the active

aggressor coupling point. The formula for Ceq-v is

slight variation of (8).

5. Calculate the new time constants tan and tbn at

aggressor coupling point.

6. Calculate other time constants sx and sv.

7. Using the iteration formula find the time that noise

peak occurs, which is tpeak.

Table 1 Experimental results

obtained in first 30 casesCase # Qdep

(fF)

Ragg

(X)

Rvic

(X)

Cagg

(fF)

Cvic

(fF)

Cc

(fF)

Noise (mV)

HSPICE

Noise (mV)

Model

|Error

%|

1 100 400 500 29 37 50 0.443 0.471 6.32

2 150 350 450 31 40 45 0.670 0.708 5.67

3 75 380 490 30 41 45 0.374 0.407 8.82

4 94 210 225 12 14 27 0.483 0.520 7.66

5 65 225 260 14 17 30 0.368 0.375 1.90

6 90 900 900 64 64 112 0.647 0.667 3.09

7 125 364 357 21 20 48 0.740 0.760 2.70

8 50 350 350 23 23 42 0.380 0.329 13.42

9 120 452 450 27 27 57 0.734 0.746 1.63

10 46 184 232 13 14 23 0.350 0.376 7.43

11 95 356 451 22 27 44 0.533 0.576 8.07

12 39 310 359 30 32 40 0.355 0.361 1.69

13 90 420 455 31 39 52 0.447 0.412 7.83

14 85 290 320 19 23 37 0.410 0.413 0.73

15 83 445 482 23 28 55 0.426 0.446 4.69

16 70 900 900 54 54 113 0.609 0.616 1.15

17 135 421 402 25 24 51 0.859 0.872 1.51

18 90 352 450 25 30 45 0.506 0.520 2.77

19 85 347 413 24 31 43 0.490 0.520 6.12

20 145 690 670 49 43 83 0.792 0.821 3.66

21 25 525 560 35 41 66 0.203 0.180 11.33

22 35 125 130 11 14 16 0.140 0.155 10.71

23 89 190 210 13 15 23 0.492 0.509 3.46

24 150 460 475 31 40 55 0.710 0.755 6.34

25 65 592 592 37 37 73 0.489 0.508 3.89

26 65 358 358 23 23 45 0.396 0.434 9.60

27 100 843 860 66 73 105 0.670 0.720 7.46

28 95 516 531 32 39 65 0.640 0.580 9.38

29 65 915 923 65 68 115 0.553 0.568 2.71

30 85 635 642 44 47 70 0.595 0.609 2.35

Average % error for

first 30 cases

5.47%

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123

8. Finally obtain Vpeak by inserting tpeak in (27) and

decide whether the noise is important or not.

7 Validation of the proposed model

We have tested our proposed model using over 1,000

randomly generated cases to simulate real-time cases in

65 nm technology.

We assumed two parallel interconnects on intermediate

layer that are driven by 29 inverters (0.26/0.13 lm). It was

also assumed that the loads at the end of wires are minimum

sized identical inverters. Various interconnect spacing, length

and widths were examined. Interconnect lengths were varied

from 200 up to 2 mm with coupling portion changed. Some of

these nets also included some tree branches. The parameter

values for these test circuits have been derived using inter-

connect model given in [24]. The simulated deposited char-

ges, Qdep, were selected in the range 20–150 fC.

The SE crosstalk model has been coded in C?? envi-

ronment and results are verified by comparing to HSPICE

outputs. While the proposed model used a 4-p template,

HSPICE simulation utilized a 20-p representation to model

the distributed behavior. In Spice modeling, the coupling

capacitances were also distributed.

Table 1 shows the SE Crosstalk noise calculation results

for the first 30 cases. In this table, Ragg/Cagg and Rvic/Cvic

denote aggressor and victim line resistance/capacitance,

respectively. Finally, Cc indicates the coupling capacitance

values taken for each case.

For the 30 test cases considered, the proposed model has

an average error of 5.47% when compared to HSPICE. For

all cases shown, the percent error stays less than 15%.

Table 2 summarizes the results obtained for 1,000 ran-

dom test circuits considered. In this table, the percentage of

nets that fall into the given error ranges has been given. For

example, about 86% of nets have errors less than 10%

when predicting the noise peak voltage. On the other hand,

around 97% of all nets have errors less than 15%.

Results show an average error of 5.2% for the noise

peak when compared to HSPICE results. The CPU time for

these test circuits ranges from 0.02 to 0.29 mS on a

3.0 GHz Pentium IV machine which suggests that the

model calculation is at least a 10009 faster than HSPICE.

8 Conclusion

Researchers mostly focused on the propagation of SET

pulses through logic gates without considering intercon-

nects between them. However, due to strong coupling

among wires, SETs may now affect multiple logic paths.

For high-reliability, mission critical applications, such as

military or medical systems, SE crosstalk effects must also

be in reliability analysis included in addition to SETs.

In this work, we proposed a fast SE crosstalk noise

estimation method for use in design automation tools.

Normally, SPICE simulators can be used to estimate

crosstalk effects in signal lines. However, due to density of

interconnect lines, these simulations are time-inefficient.

The proposed method uses an accurate 4-p model for

interconnect and correctly models the loading effect of

neighboring lines and net tree branches noting the resistive

shielding effect. The dominant pole approximation was

used in moderation which resulted in increased accuracy of

model.

A logical extension of this work would incorporate non-

linear characteristics of drivers in the model especially for

large charge injection levels.

For the deposited charge levels considered in terrestrial

environment, the derived SE crosstalk noise expressions

show very good results in comparison to HSPICE results.

Results show that average error for noise peak is about

5.2% while allowing for very fast analysis compared to

HSPICE.

Acknowledgment This work was supported in part by NASA Texas

Space Grant Consortium (TSGC) Higher Education Grant.

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Selahattin Sayil received the

M.Sc. degree from the Penn-

sylvania State University, Uni-

versity Park, PA, in 1996 and

the Ph.D. degree in Electrical

Engineering from Vanderbilt

University, TN, in 2000. He is

currently an Associate Professor

in Electrical Engineering at

Lamar University, where he

leads the VLSI CAD And Sig-

nal Integrity Group. His current

research interests include Radi-

ation Effects Modeling in VLSI,

Single Event Mitigation, Inter-

connect Analysis, Signal Integrity in CMOS VLSI, and Contactless

Testing of VLSI Circuits. He is a member of IEEE and serves as an

Associate Editor for International Journal of Electronics.

Vijay K. Boorla received his

Master of Science Degree in

Electrical Engineering from

Lamar University in May 2010.

He has received his Bachelors

Degree from Jawaharlal Nehru

Technological University, Hy-

derabad, India in 2007. His

research areas include Radiation

Hardening, Noise analysis and

modeling of VLSI Interconnects.

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