Simultaneous Multithreading (SMT)

EECC722 - ShaabanEECC722 - Shaaban#1 Lec # 2 Fall 2000 9-11-2000

Simultaneous Multithreading (SMT)Simultaneous Multithreading (SMT)• An evolutionary processor architecture originally

introduced in 1996 by Dean Tullsen at the University of Washington that aims at reducing resource waste in wide issue processors.

• SMT has the potential of greatly enhancing processor computational capabilities by:

– Exploiting thread-level parallelism (TLP), simultaneously executing instructions from different threads during the same cycle.

– Providing multiple hardware contexts, hardware thread scheduling and context switching capability.


Microprocessor Architecture TrendsMicroprocessor Architecture Trends

C IS C M ac h i n e sins truc tio ns take var iable t im e s to c o m ple te

R IS C M ac h i n e s ( m i c r o c o d e )s im ple ins truc tio ns , o ptim ize d fo r spe e d

R IS C M ac h i n e s ( p i p e l i n e d )s am e individual ins truc tio n late nc y

gre ate r thro ughput thro ugh ins truc tio n "o ve r lap"

S u p e r s c a l ar P r o c e s s o r sm ultiple ins truc tio ns e xe c uting s im ultane o us ly

M u l t i t h r e ad e d P r o c e s s o r saddit io nal H W re so urc e s ( re gs , P C , SP )e ac h c o nte xt ge ts pro c e s so r fo r x c yc le s

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de c re ase d H W c o ntro l c o m ple xity

S i n g l e C h i p M u l t i p r o c e s s o r sduplic ate e ntire pro c e s so rs

( te c h so o n due to M o o re 's Law)

S IM U L TA N E O U S M U L TITH R E A D IN Gm ultiple H W c o nte xts ( re gs , P C , SP )e ac h c yc le , any c o nte xt m ay e xe c ute


Performance Increase of Workstation-Class Performance Increase of Workstation-Class Microprocessors 1987-1997Microprocessors 1987-1997

Integer SPEC92 PerformanceInteger SPEC92 Performance


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Moore’s Law:Moore’s Law:2X transistors/ChipEvery 1.5 years

Alpha 21264: 15 millionPentium Pro: 5.5 millionPowerPC 620: 6.9 millionAlpha 21164: 9.3 millionSparc Ultra: 5.2 million

Moore’s Law


Increase of Capacity of VLSI Dynamic RAM ChipsIncrease of Capacity of VLSI Dynamic RAM Chips

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1.55X/yr, or doubling every 1.6 years


CPU Architecture Evolution:CPU Architecture Evolution:

Single Threaded PipelineSingle Threaded Pipeline

• Traditional 5-stage pipeline.• Increases Throughput: Ideal CPI = 1

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CPU Architecture Evolution:CPU Architecture Evolution:

Superscalar ArchitecturesSuperscalar Architectures• Fetch, decode, execute, etc. more than one instruction per cycle (CPI <

1).• Limited by instruction-level parallelism (ILP).


Traditional Multithreaded ProcessorTraditional Multithreaded Processor

• Multiple HW contexts (PC, SP, and registers)

• One context gets CPU for x cycles at a time.

• Limited by thread-level parallelism (TLP).

Advanced CPU Architectures:Advanced CPU Architectures:


VLIW: Intel/HPVLIW: Intel/HP

Explicitly Parallel Instruction Computing Explicitly Parallel Instruction Computing (EPIC)(EPIC)

• Strengths: – Allows for a high level of instruction parallelism (ILP).

– Takes a lot of the dependency analysis out of HW and places focus on smart compilers.

• Weakness: – Keeping Functional Units (FUs) busy (control hazards).

– Static FUs Scheduling limits performance gains.



Single Chip MultiprocessorSingle Chip Multiprocessor• Strengths:

– Create a single processor block and duplicate.

– Takes a lot of the dependency analysis out of HW and places focus on smart compilers.

• Weakness: – Performance limited by individual thread performance

(ILP).




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SMT: Simultaneous Multithreading• Multiple Hardware Contexts running at the same time

(HW context: registers, PC, and SP).

• Avoids both horizontal and vertical waste by having multiple threads keeping functional units busy during every cycle.

• Builds on top of current time-proven advancements in CPU design: superscalar, dynamic scheduling, hardware speculation, dynamic HW branch prediction.

• Enabling Technology: VLSI logic density in the order of hundreds of millions of transistors/Chip.


SMT• With multiple threads running penalties from long-

latency operations, cache misses, and branch mispredictions will be hidden.

• Pipelines are separated until issue stage

• Functional units are shared among all contexts during every cycle

– More complicated writeback stage.

• More threads issuing to functional units results in higher resource utilization


SMT: Simultaneous Multithreading

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The Power Of SMTThe Power Of SMT1 1

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Superscalar Traditional Multithreaded

Simultaneous Multithreading

Rows of squares represent instruction issue slotsBox with number x: instruction issued from thread xEmpty box: slot is wasted


SMT Performance ComparisonSMT Performance Comparison• Instruction throughput from simulations by Eggers et al. at The University of Washington, using both multiprogramming and parallel workloads:

Multiprogramming workload

Superscalar Traditional SMTThreads Multithreading 1 2.7 2.6 3.1 2 - 3.3 3.5 4 - 3.6 5.7 8 - 2.8 6.2

Parallel Workload

Superscalar MP2 MP4 Traditional SMTThreads Multithreading 1 3.3 2.4 1.5 3.3 3.3 2 - 4.3 2.6 4.1 4.7 4 - - 4.2 4.2 5.6 8 - - - 3.5 6.1


SMT Instruction Scheduling MethodsSMT Instruction Scheduling Methods

• Round Robin:

– Instruction from Thread 1, then Thread 2, then Thread 3, etc.

• I-Count:

– Highest priority assigned to thread with the lowest number of instructions in static portion of pipeline.

• Other:

– Branch First: Branch instructions issued first

– Spec Last: Speculative instructions given low priority


SMT Performance ExampleSMT Performance Example

Inst Code Description Functional unitA LUI R5,100 R5 = 100 Int ALUB FMUL F1,F2,F3 F1 = F2 x F3 FP ALUC ADD R4,R4,8 R4 = R4 + 8 Int ALUD MUL R3,R4,R5 R3 = R4 x R5 Int mul/divE LW R6,R4 R6 = (R4) Memory portF ADD R1,R2,R3 R1 = R2 + R3 Int ALUG NOT R7,R7 R7 = !R7 Int ALUH FADD F4,F1,F2 F4=F1 + F2 FP ALUI XOR R8,R1,R7 R8 = R1 XOR R7 Int ALUJ SUBI R2,R1,4 R2 = R1 – 4 Int ALUK SW ADDR,R2 (ADDR) = R2 Memory port

• 4 integer ALUs (1 cycle latency)

• 1 integer multiplier/divider (3 cycle latency)

• 3 memory ports (2 cycle latency, assume cache hit)

• 2 FP ALUs (5 cycle latency)

• Assume all functional units are fully-pipelined


SMT Performance Example SMT Performance Example (continued)(continued)

Cycle Superscalar Issuing Slots SMT Issuing Slots1 2 3 4 1 2 3 4

1 LUI (A) FMUL (B) ADD (C) T1.LUI (A) T1.FMUL(B)

T1.ADD (C) T2.LUI (A)

2 MUL (D) LW (E) T1.MUL (D) T1.LW (E) T2.FMUL (B) T2.ADD (C)3 T2.MUL (D) T2.LW (E)45 ADD (F) NOT (G) T1.ADD (F) T1.NOT (G)6 FADD (H) XOR (I) SUBI (J ) T1.FADD (H) T1.XOR (I) T1.SUBI (J ) T2.ADD (F)7 SW (K) T1.SW (K) T2.NOT (G) T2.FADD (H)8 T2.XOR (I) T2.SUBI (J )9 T2.SW (K)

• 2 additional cycles to complete program 2

• Throughput:

– Superscalar: 11 inst/7 cycles = 1.57 IPC

– SMT: 22 inst/9 cycles = 2.44 IPC


Simulator (sim-SMT) @ RIT CESimulator (sim-SMT) @ RIT CE

• Execution-driven, performance simulator.

• Derived from Simple Scalar tool set.

• Simulates cache, branch prediction, five pipeline stages

• Flexible:– Configuration File controls cache size, buffer sizes, number

of functional units.

• Cross compiler used to generate Simple Scalar assembly language.

• Binary utilities, compiler, and assembler available.

• Standard C library (libc) has been ported.


Simulator Memory Address SpaceSimulator Memory Address Space


Alternate Functional Unit Alternate Functional Unit ConfigurationsConfigurations

• New functional unit configurations attempted (by adding one of each type of FU):– +1 integer multiplier/divider

• +2.8% IPC, issue rate

• -74% times with no FU available

• Simulator very flexible (only one line in configuration file required change)


Sim-SMT Simulator LimitationsSim-SMT Simulator Limitations

• Does not keep precise exceptions.

• System Call’s instructions not tracked.

• Limited memory space:

– Four test programs’ memory spaces running on one simulator memory space

– Easy to run out of stack space


Simulation Runs & ResultsSimulation Runs & Results• Test Programs used:

– Newton interpolation.– Matrix Solver using LU decomposition.– Integer Test Program.– FP Test Program.

• Simulations of a single program– 1,2, and 4 threads.

• System simulations involve a combination of all programs simultaneously– Several different combinations were run

• From simulation results:– Performance increase:

• Biggest increase occurs when changing from one to two threads.

– Higher issue rate, functional unit utilization.


Performance (IPC)Performance (IPC)Simulation Results:Simulation Results:


Simulation Results: Simulation Results: Simulation Time Simulation Time


Instruction Issue RateInstruction Issue RateSimulation Results:Simulation Results:


Performance Vs. Issue BWPerformance Vs. Issue BWSimulation Results:Simulation Results:


Functional Unit UtilizationFunctional Unit UtilizationSimulation Results:Simulation Results:


No Functional Unit AvailableNo Functional Unit AvailableSimulation Results:Simulation Results:


Horizontal Waste RateHorizontal Waste RateSimulation Results:Simulation Results:


Vertical Waste RateVertical Waste RateSimulation Results:Simulation Results:


SMT: Simultaneous Multithreading• Strengths:

– Overcomes the limitations imposed by low single thread instruction-level parallelism.

– Multiple threads running will hide individual control hazards (branch mispredictions).

• Weaknesses: – Additional stress placed on memory hierarchy Control unit

complexity.– Sizing of resources (cache, branch prediction, etc.)– Accessing registers (32 integer + 32 FP for each HW context):

• Some designs devote two clock cycles for both register reads and register writes.


SMT: Simultaneous MultithreadingSMT: Simultaneous Multithreading

Kernel CodeKernel Code• Many, if not all, benchmarks are based upon a limited

interaction with kernel code.

• How can the kernel overhead be minimized (context-switching, process management, etc.)?– CHAOS (Context Hardware Accelerated Operating

System).

• Introduce a lightweight dedicated kernel context to handle process management:– When there are 4 contexts, there is a good chance that one

of them will continue to run, why take an (expensive) chance in swapping it out when it will be brought right back in by the swapper (process management).


SMT & TechnologySMT & Technology

• SMT architecture has not been implemented in any existing commercial microprocessor yet (First 4-thread SMT CPU: Alpha EV8 ~2001).

• Current technology has the potential for 4-8 simultaneous threads:

– Based on transistor count and design complexity.


RIT-CE SMT Project GoalsRIT-CE SMT Project Goals• Investigate performance gains from exploiting Thread-

Level Parallelism (TLP) in addition to current Instruction-Level Parallelism (ILP) in processor design.

• Design and simulate an architecture incorporating Simultaneous Multithreading (SMT).

• Study operating system and compiler modifications needed to support SMT processor architectures.

• Define a standard interface for efficient SMT-processor/OS kernel interaction.

• Modify an existing OS kernel (Linux?) to take advantage of hardware multithreading capabilities.

• Long term: VLSI implementation of an SMT prototype.


Current Project StatusCurrent Project Status• Architecture/OS interface definition.

• Study of design alternatives and impact on performance.

• SMT Simulator Development:

– System call development, kernel support, and compiler/assembler changes.

• Development of code (programs and OS kernel) is key to getting results.


Short-Term Project ChartShort-Term Project Chart

S im u la to r Com piler

Linker/Loader

S im ulation Res ults(running program )

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Current/Future Project GoalsCurrent/Future Project Goals• SMT simulator completion refinement, and further testing.

• Development of an SMT-capable OS kernel.

• Extensive performance studies with various workloads using the simulator/OS/compiler:– Suitability for fine-grained parallel applications?– Effect on multimedia applications?

• Architectural changes based on benchmarks.

• Cache impact on SMT performance investigation.• Investigation of an in-order SMT processor (C or VHDL model)

• MOSIS Tiny Chip (partial/full) implementation.

• Investigate the suitability of SMT processors as building blocks for MPPs.

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Simultaneous Multithreading (SMT)