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Simulations of ‘Bottom-up’ Fill Simulations of ‘Bottom-up’ Fill in Via Plating of Semiconductor in Via Plating of Semiconductor Interconnects Interconnects Uziel Landau Uziel Landau 1 , Rohan Akolkar , Rohan Akolkar 1 , , Eugene Malyshev Eugene Malyshev 2 , and Sergey , and Sergey Chivilikhin Chivilikhin 2 1 Department of Chemical Engineering Case Western Reserve University Cleveland, OH 44106 and 2 L-Chem, Inc Beachwood, OH 44122

Simulations of ‘Bottom-up’ Fill in Via Plating of Semiconductor Interconnects Uziel Landau 1, Rohan Akolkar 1, Eugene Malyshev 2, and Sergey Chivilikhin

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Page 1: Simulations of ‘Bottom-up’ Fill in Via Plating of Semiconductor Interconnects Uziel Landau 1, Rohan Akolkar 1, Eugene Malyshev 2, and Sergey Chivilikhin

Simulations of ‘Bottom-up’ Fill in Simulations of ‘Bottom-up’ Fill in Via Plating of Semiconductor Via Plating of Semiconductor

InterconnectsInterconnectsUziel LandauUziel Landau11, Rohan Akolkar, Rohan Akolkar11, , Eugene MalyshevEugene Malyshev22, and Sergey , and Sergey

ChivilikhinChivilikhin22

1Department of Chemical EngineeringCase Western Reserve University

Cleveland, OH 44106 and

2L-Chem, IncBeachwood, OH 44122 

Page 2: Simulations of ‘Bottom-up’ Fill in Via Plating of Semiconductor Interconnects Uziel Landau 1, Rohan Akolkar 1, Eugene Malyshev 2, and Sergey Chivilikhin

OutlineOutline• Significance and ObjectivesSignificance and Objectives• Parameters Controlling the Bottom-Parameters Controlling the Bottom-Up FillUp Fill• Simulation MethodSimulation Method• Sample SimulationsSample Simulations• ConclusionsConclusions

Page 3: Simulations of ‘Bottom-up’ Fill in Via Plating of Semiconductor Interconnects Uziel Landau 1, Rohan Akolkar 1, Eugene Malyshev 2, and Sergey Chivilikhin

Prior WorkPrior Work•Andricacos, Uzoh, Dukovic, Horkans and Deligianni, IBM J. R&D 1998:

- Additives blocking model- Adjustable Parameters + steady-state additives diffusion

•Georgiadou, Veyret, Sani and Alkire, J. Electrochem. Soc. 2001:

- Convective flow + additives transport

•Cao, Taephaisitphongse, Chalupa and West, J. Electrochem. Soc., 2001:

- Diffusion controlled additives transport + adsorption isotherms

• Josell, Baker, Witt, Wheeler and Moffat, J. Electrochem. Soc., 2002:

- Curvature enhanced SPS coverage

Page 4: Simulations of ‘Bottom-up’ Fill in Via Plating of Semiconductor Interconnects Uziel Landau 1, Rohan Akolkar 1, Eugene Malyshev 2, and Sergey Chivilikhin

ObjectivesObjectives Develop a Simulation for the Bottom-Develop a Simulation for the Bottom-

Up FillUp Fill

Based on Experimental DataBased on Experimental Data

Without Adjustable Parameters & Without Adjustable Parameters &

Without Without Invoking Extreme Invoking Extreme

AssumptionsAssumptions

Simulation should correlate Simulation should correlate

experimental experimental

observations observations

Page 5: Simulations of ‘Bottom-up’ Fill in Via Plating of Semiconductor Interconnects Uziel Landau 1, Rohan Akolkar 1, Eugene Malyshev 2, and Sergey Chivilikhin

Gap-Fill Gap-Fill ModesModes

Bottom-up Fill

(Good!)

Pinch

Conventional Plating

(unacceptable)

Seam

Conformal Plating

(unacceptable)

Page 6: Simulations of ‘Bottom-up’ Fill in Via Plating of Semiconductor Interconnects Uziel Landau 1, Rohan Akolkar 1, Eugene Malyshev 2, and Sergey Chivilikhin

Seam

Void

Fill~ 2.5 min~ 50 sec~ 30 sec

‘Conventional’ Plating

Conformal Plating

Bottom-up Plating

Stages in ‘Gap-Fill’

Page 7: Simulations of ‘Bottom-up’ Fill in Via Plating of Semiconductor Interconnects Uziel Landau 1, Rohan Akolkar 1, Eugene Malyshev 2, and Sergey Chivilikhin

Variable Adsorption leads to Variable Variable Adsorption leads to Variable Kinetics and to ‘Bottom-up’ fill:Kinetics and to ‘Bottom-up’ fill:

Suppressor, e.g. PAG

Slow deposition

Fast deposition

‘Enhancer’, e.g. Organic di-sulfide

Page 8: Simulations of ‘Bottom-up’ Fill in Via Plating of Semiconductor Interconnects Uziel Landau 1, Rohan Akolkar 1, Eugene Malyshev 2, and Sergey Chivilikhin

Variable Deposition Rates Due to Non-uniform Variable Deposition Rates Due to Non-uniform InhibitionInhibition

i

[mA/cm2]

V

Polarization Curves

Enhanced Kinetics (via)

Suppressed Kinetics

(‘flat’ wafer)10

300 mV

100

Page 9: Simulations of ‘Bottom-up’ Fill in Via Plating of Semiconductor Interconnects Uziel Landau 1, Rohan Akolkar 1, Eugene Malyshev 2, and Sergey Chivilikhin

< 50 Sec

2-3 Min

Rapid Fill of Vias and Rapid Fill of Vias and TrenchesTrenches

Page 10: Simulations of ‘Bottom-up’ Fill in Via Plating of Semiconductor Interconnects Uziel Landau 1, Rohan Akolkar 1, Eugene Malyshev 2, and Sergey Chivilikhin

Nernst-Plank Equation (ionic transport):

Navier-Stokes Equation (fluid-flow–momentum balance):

VVVV 2

Pt

C (Boundary

Layer)

Transport Equations --Transport Equations --

Electroneutrality:

Zj Cj = 0

jjjjjjj CCUFZCDt

C

V

Pseudo Steady-State

Diffusion Electric Migration

Convection

Page 11: Simulations of ‘Bottom-up’ Fill in Via Plating of Semiconductor Interconnects Uziel Landau 1, Rohan Akolkar 1, Eugene Malyshev 2, and Sergey Chivilikhin

Scaling Analysis of the Nernst Plank Scaling Analysis of the Nernst Plank Equation*:Equation*: 02 jjjjj CFUZCD

Diffusion Electric Migration

Cb

2 = 0Thin boundary layerBoundary conditions:

Electrode: = V – E0 – ηa – ηC

Insulator: i = 0 (i = - κ ) = 0

Ohmic Control on the Macro-Scale

μm500mm0.5 L

sticcharacteri iFn

TRL

Thin Boundary Layer Approximation

2 = 0 (Laplace’s eqn. for the potential is solved within the cell)

* U. Landau, The Electrochem. Soc. Proceedings Volume 94-9, 1994.

Page 12: Simulations of ‘Bottom-up’ Fill in Via Plating of Semiconductor Interconnects Uziel Landau 1, Rohan Akolkar 1, Eugene Malyshev 2, and Sergey Chivilikhin

Scaling Analysis of the Nernst Plank Scaling Analysis of the Nernst Plank Equation*:Equation*: 02 jjjjj CFUZCD

Diffusion Electric Migration

Cb

2 = 0

Mass Transport Control on the Micro-Scale

μm500mm0.5 L

sticcharacteri iFn

TRL

2 C = 0 (Laplace’s eqn. for the Concentration, solved in the boundary layer)Boundary conditions:

Electrode: ηC = V – E0– ηa -

outer edge of diffusion layer: y = C = CB

Insulator: i = 0 (i = - κ ) C = 0

* U. Landau, The Electrochem. Soc. Proceedings Volume 94-9, 1994.

Boundary layer

Page 13: Simulations of ‘Bottom-up’ Fill in Via Plating of Semiconductor Interconnects Uziel Landau 1, Rohan Akolkar 1, Eugene Malyshev 2, and Sergey Chivilikhin

The Software PackageThe Software Package‘Cell-Design’ Features:

Current Distribution + Fluid Flow (BEM + FD)

Current Distribution: (BEM)

• Macro-scale:

• Micro-scale:• Moving boundaries• Variable Kinetics

Fluid-Flow (FD):

• Complete solution of the Navier-Stokes equation

• Integrated with the electrochemical modeling

• Solution of the Nernst-Plank equation• Export C

Fast, Robust, Menu driven

2 2 C = 0C = 0

22 = 0 = 0

Boundary Element (BEM)

Finite Differences (FD)

Page 14: Simulations of ‘Bottom-up’ Fill in Via Plating of Semiconductor Interconnects Uziel Landau 1, Rohan Akolkar 1, Eugene Malyshev 2, and Sergey Chivilikhin

Simulation of Deposit Simulation of Deposit PropagationPropagationVariable kinetics + Moving

boundaries

2 =0 2 C =0

i = f (η)

Passivated kinetics (PEG+SPS) [Measured, f(t)]

Accelerated kinetics (SPS)

Variable kinetics [Partially passivated, f(t)]

Virtual electrode;Outer edge of diffusion layer

C

Page 15: Simulations of ‘Bottom-up’ Fill in Via Plating of Semiconductor Interconnects Uziel Landau 1, Rohan Akolkar 1, Eugene Malyshev 2, and Sergey Chivilikhin

Flow SimulationsFlow Simulations

60 RPM + 4 GPM Impinging Flow

Wafer Wafer ScaleScale

‘Cell-Design’ Simulations

Page 16: Simulations of ‘Bottom-up’ Fill in Via Plating of Semiconductor Interconnects Uziel Landau 1, Rohan Akolkar 1, Eugene Malyshev 2, and Sergey Chivilikhin

Flow Flow SimulationsSimulationsMicro-ScaleMicro-Scale

Transport within the via is due to diffusion

‘Cell-Design’ Simulations

Page 17: Simulations of ‘Bottom-up’ Fill in Via Plating of Semiconductor Interconnects Uziel Landau 1, Rohan Akolkar 1, Eugene Malyshev 2, and Sergey Chivilikhin

‘Cell-Design’ Simulations

Concentration MapConcentration Map

Page 18: Simulations of ‘Bottom-up’ Fill in Via Plating of Semiconductor Interconnects Uziel Landau 1, Rohan Akolkar 1, Eugene Malyshev 2, and Sergey Chivilikhin

0

10

20

30

40

50

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45

Activation Overpotential, a, [V]

i

[mA/cm2]

SPS (Stagnant

) PEG (Stagnant

)

Steady-State Polarization Steady-State Polarization DataData

Page 19: Simulations of ‘Bottom-up’ Fill in Via Plating of Semiconductor Interconnects Uziel Landau 1, Rohan Akolkar 1, Eugene Malyshev 2, and Sergey Chivilikhin

0.00 0.05 0.10 0.15 0.20 0.25 0.300

10

20

30

40

50

60

70

80 SPS steady state PEG+SPS unsteady state PEG steady state

slow SPSactivity

t=50s t=20st=10s

t=0s(PEG)

Current Density, i [mA/cm2]

Activation Overpotential, a [V]

Initial state

Polarization Transients: PEG + SPSPolarization Transients: PEG + SPS

50 s 20 s10 sec

0 sec(PEG)

SPS Steady-

state

Time

Page 20: Simulations of ‘Bottom-up’ Fill in Via Plating of Semiconductor Interconnects Uziel Landau 1, Rohan Akolkar 1, Eugene Malyshev 2, and Sergey Chivilikhin

0 2 4 6 8 100.0

0.2

0.4

0.6

0.8

1.0PEG Penetration Depth, z*=z/h

Time, t (s)

Fast PEG transport to upper via sidewalls

Slow PEG transport to the via-bottom

PEG Penetration PEG Penetration DepthDepth

Short time SPS

coverage

Short time PEG

coverage

Page 21: Simulations of ‘Bottom-up’ Fill in Via Plating of Semiconductor Interconnects Uziel Landau 1, Rohan Akolkar 1, Eugene Malyshev 2, and Sergey Chivilikhin

0 2 4 6 8 100.0

0.2

0.4

0.6

0.8

1.0PEG Penetration Depth, z*=z/h

Time, t (s)

Fast PEG transport to upper via sidewalls

Slow PEG transport to the via-bottom

PEG Penetration PEG Penetration DepthDepth

Longer time PEG coverage

Longer time SPS

coverage

Slow SPS depolarizati

on

Page 22: Simulations of ‘Bottom-up’ Fill in Via Plating of Semiconductor Interconnects Uziel Landau 1, Rohan Akolkar 1, Eugene Malyshev 2, and Sergey Chivilikhin

SiO2

2 sec

4 sec

8 sec

12 sec

16 sec

24 sec

32 sec

40 sec

44 sec

Electrolyte

47 sec

‘Cell-Design’ Simulations

Via Fill Via Fill SimulationSimulationFill Time: 47 sec.

Overpotential: - 124 mV

Bottom: i = 60 mA/cm2

i0 = 1.12 mA/cm2 C = 0.83

Top & Sidewalls: i = 0.24 mA/cm2 3.4 mA/cm2

Depolarization by SPS:i0 = 3.1 μA/cm2 46 μA/cm2

C = 0.9

Page 23: Simulations of ‘Bottom-up’ Fill in Via Plating of Semiconductor Interconnects Uziel Landau 1, Rohan Akolkar 1, Eugene Malyshev 2, and Sergey Chivilikhin

SiO2

Electrolyte

2 sec

6 sec

16 sec

32 sec

10 sec

22 sec

42 sec

50 sec

‘Cell-Design’ Simulations

Via Fill Via Fill SimulationSimulationFill Time: 49 sec.

Overpotential: - 124 mV

Bottom: i = 60 mA/cm2

i0 = 1.12 mA/cm2 C = 0.83

Top & Sidewalls: i = 0.24 mA/cm2 6.8 mA/cm2

Depolarization by SPS:i0 = 3.1 μA/cm2 92 μA/cm2

C = 0.9

Page 24: Simulations of ‘Bottom-up’ Fill in Via Plating of Semiconductor Interconnects Uziel Landau 1, Rohan Akolkar 1, Eugene Malyshev 2, and Sergey Chivilikhin

SiO2

Electrolyte

‘Cell-Design’ Simulations

SiO2

Electrolyte

1 sec time intervals

Variable Kinetics along the Sidewalls

Via Fill Via Fill SimulationSimulation

Fill Time: 48 sec.

Overpotential: - 124 mV

Bottom: i = 60 mA/cm2

i0 = 1.12 mA/cm2 C = 0.83

Top: i = 0.24 mA/cm2 3.4 mA/cm2

Depolarization by SPS:i0 = 3.1 μA/cm2 46 μA/cm2

C = 0.9

Sidewalls: Interpolated kinetics between Top and Bottom

Page 25: Simulations of ‘Bottom-up’ Fill in Via Plating of Semiconductor Interconnects Uziel Landau 1, Rohan Akolkar 1, Eugene Malyshev 2, and Sergey Chivilikhin

SiO2

Electrolyte

Seam

‘Cell-Design’ Simulations

Via Fill Via Fill SimulationSimulation

Plating Time: ~147 sec.

Overpotential: - 80 mV

Bottom: i = 10 mA/cmi = 10 mA/cm22

i0 = 1.12 mA/cm2 C = 0.83

Top: i = 0.05 mA/cm2 4.8 mA/cm2

High Depolarization by SPS:i0 = 3.1 μA/cm2 0.28 mA/cm2 C = 0.9

Sidewalls: Interpolated kinetics between Top and Bottom

Current density has been Current density has been lowered: lowered: No Bottom-Up FillNo Bottom-Up Fill

1 sec time intervals

Page 26: Simulations of ‘Bottom-up’ Fill in Via Plating of Semiconductor Interconnects Uziel Landau 1, Rohan Akolkar 1, Eugene Malyshev 2, and Sergey Chivilikhin

Deposit Propagation in Deposit Propagation in Feature Clusters and Wide Feature Clusters and Wide

FeaturesFeatures

Flat regions - Passivated: i0 =5x10-4 A/cm2

Ac

Bottom – Pure copper: i0 =10-3 A/cm2

Ac

Side-walls - interpolated

Cluster

Wide Feature

‘Cell-Design’ Simulations

Page 27: Simulations of ‘Bottom-up’ Fill in Via Plating of Semiconductor Interconnects Uziel Landau 1, Rohan Akolkar 1, Eugene Malyshev 2, and Sergey Chivilikhin

ConclusionsConclusions Simulation of bottom-up fill has been carried Simulation of bottom-up fill has been carried

w/o invoking arbitrary assumptions w/o invoking arbitrary assumptions

Simulation is based on, and implements Simulation is based on, and implements ‘variable‘ kinetics = f(time, position)‘variable‘ kinetics = f(time, position)

A commercial CAD program that accomodates A commercial CAD program that accomodates moving boundaries and variable kinetics was moving boundaries and variable kinetics was usedused

Different process parameters have been Different process parameters have been explored: explored:

Transport and adsorption kinetics of inhibiting Transport and adsorption kinetics of inhibiting and depolarizing additives must match processand depolarizing additives must match process

Operating conditions (i, V) must be within Operating conditions (i, V) must be within

rangerange

Page 28: Simulations of ‘Bottom-up’ Fill in Via Plating of Semiconductor Interconnects Uziel Landau 1, Rohan Akolkar 1, Eugene Malyshev 2, and Sergey Chivilikhin

AcknowledgementAcknowledgementss

• Yezdi Dordi – Yezdi Dordi – Applied materialsApplied materials• Peter Hey – Peter Hey – Applied MaterialsApplied Materials• Andrew Lipin – Andrew Lipin – L-ChemL-Chem

Page 29: Simulations of ‘Bottom-up’ Fill in Via Plating of Semiconductor Interconnects Uziel Landau 1, Rohan Akolkar 1, Eugene Malyshev 2, and Sergey Chivilikhin

Thank you for Thank you for your your

attentionattention