EEE/CSE 120

Simulation Lab 2 Answer Sheet 4-Bit Full Adder, Multiplexer & Decoder

Name:____Genaro Romero______________________

Instructor:__________________________

Class Time:________________________

Date:________________________

Task 2-1: Design a Full Adder

Write down the canonical POS expressions for the Cout and SUM function of a full adder. Be sure to check the lab manual for more detailed information. :_____________________________________________

_____________________________________________________________________________________

_____________________________________________________________________________________

Cut and paste your LogicWorks™ circuit that implements your canonical SUM and Cout functions here:

A

B

Cin

Cout

0 1

0 10 1

1

1

Follow the testing procedures outlined in the laboratory manual on your circuit and record your results in Table 1.

Table 1Cin A B SUM Cout

0 0 0 0 00 0 1 1 00 1 0 1 0 0 1 1 0 1 1 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1

2

Task 2-2: Build, Debug and Test a 1-Bit Full Adder

Cut and paste your LogicWorks™ 1-bit minimal form full-adder circuit here:

A

B

Cin

Cout

SUM

Test your minimal form full-adder circuit and record your results in Table 2. Cut and paste your LogicWorks 1-bit minimal form full-adder circuit testing set up.

A

B

Cin

Cout

SUM

0 10 1

0 1

0

0

3

Table 2 Debug CheckmarkCin A B SUM Cout

0 0 0 0 0 X0 0 1 1 0 X0 1 0 1 0 X0 1 1 0 1 X1 0 0 1 0 X1 0 1 0 1 X1 1 0 0 1 X1 1 1 1 1 X

Cut and paste your LogicWorks™ 1-bit full adder subcircuit here:

CinBA

CoutSUM

FA_1

Test your subcircuit and place a mark in the checkmark column of Table 2 next to values you tested. Cut and paste your LogicWorks 1-bit full-adder subcircuit testing set up.

CinBA

CoutSUM

FA_1 1

1

01

01

01

Task 2-3: Design, Build and Test a 4-Bit Full Adder

Cut and paste your LogicWorks™ 4-bit full-adder circuit here:

4

CinBA

CoutSUM

FA_1

CinBA

CoutSUM

FA_1

CinBA

CoutSUM

FA_1

CinBA

CoutSUM

FA_1

A0B0Cin

A1B1

A2B2

A3B3

Y0

Y3Cout

Y1

Y2

Develop a test plan and record your results in Table 3 (Note: Do NOT test all input combinations. Table 3 may not need to be entirely filled in). Connect a hex keyboard to the inputs A and B as well as a hex display to SUM. It is left to you to decide what constitutes a sufficient test set. Give justification as to why completing your tests make it likely that the 4-bit full-adder circuit is operating correctly:_____________________________________________________________________________

Cut and paste your LogicWorks™ 4-bit full-adder testing set up.

5

CinBA

CoutSUM

FA_1

CinBA

CoutSUM

FA_1

CinBA

CoutSUM

FA_1

CinBA

CoutSUM

FA_1

A0B0Cin

A1B1

A2B2

A3B3

Y0

Y3Cout

Y1

Y2

0

0

0

0

0

0 101

010 1

0 1

0 101

0101

6

Table 3 Debug Checkmark

CinA

(hex)B

(hex)SUM(hex)

Cout

7

0 A A 4 1 X0 B B 6 1 X0 C C 8 1 X0 D D A 1 X0 E E C 1 X

0 F F E 1 X

0 1 1 2 0 X1 A A 5 1 X1 B B 7 1 X1 C C 9 1 X1 D D B 1 X1 E E D 1 X1 F F F 1 X1 1 1 3 0 X

Cut and paste your LogicWorks™ 4-bit full-adder subcircuit here:

CinB0B1B2B3A0A1A2A3

CoutY0Y1Y2Y3

FA_4

Test your subcircuit and place a mark in the checkmark column of Table 3 next to values you used to verify your subcircuit. Cut and paste your LogicWorks™ 4-bit full-adder subcircuit testing set up.

CinB0B1B2B3A0A1A2A3

CoutY0Y1Y2Y3

FA_40 1 2 34 5 6 78 9 A BC D E F

0 1 2 34 5 6 78 9 A BC D E F

4

1

+5V

8

Task 2-4: Design, Build and Test a MUX

Cut and paste your LogicWorks™ 1-bit MUX circuit here:

Y

A/~B

B

A

Test your 1-bit MUX circuit and record your results in Table 4. Cut and paste your LogicWorks 1-bit MUX circuit testing set up.

Y

A/~B

B

A

0101

01

1

Table 4 Debug checkmarkA B A/~B Y

0 0 0 0 X0 0 1 1 X0 1 0 0 X0 1 1 1 X1 0 0 0 X1 0 1 0 X1 1 0 1 X1 1 1 1 X

9

Cut and paste your LogicWorks™ 1-bit MUX subcircuit here:

A/~BBA

Y

MUX_1

Test your 1-bit Mux subcircuit and place a mark in the checkmark column of Table 4 to indicate the values you checked. Cut and paste your LogicWorks 1-bit MUX subcircuit testing set up.

A/~BBA

Y

MUX_11

01

01

01

Task 2-5: Build a 2-Input 4-Bit Multiplexer

Cut and paste your LogicWorks™ 4-bit MUX circuit here:

10

A/~BBA

Y

MUX_1

A/~BBA

Y

MUX_1

A/~BBA

Y

MUX_1

A/~BBA

Y

MUX_1

A0B0B0

A1A1A1B1

A2A2B2

A3B3B3

Y0

Y1

Y2

Y3

A/~B

Test your MUX and record your results in Table 5. It is left to you to decide what test combination to use. Note all of Table 5 may not need to be filled in. Cut and paste your LogicWorks 4-bit MUX circuit testing set up.

11

A/~BBA

Y

MUX_1

A/~BBA

Y

MUX_1

A/~BBA

Y

MUX_1

A/~BBA

Y

MUX_1

A0B0B0

A1A1A1B1

A2A2B2

A3B3B3

Y0

Y1

Y2

Y3

A/~B0 1

0 1

0 10 1

0 10 1

0 1

0 10 1

1

1

1

1

Table 5 A

(hex)B

(hex)A/~B Y

(hex)Debug

checkmark A A 1 5 X

B B 1 4 X

C C 1 3 X

D D 1 2 X

E E 1 1 X

F F 0 0 X

1 1 0 F X

2 2 0 E X

3 3 0 D X

12

Cut and paste your LogicWorks™ 4-bit MUX subcircuit here:

A/~BB0B1B2B3A0A1A2A3

Y0Y1Y2Y3

MUX_4

Test and verify your subcircuit is working properly using and place a mark in the checkmark column of Table 5 next to values you used to verify your subcircuit. Cut and paste your LogicWorks 4-bit MUX subcircuit testing set up.

A/~BB0B1B2B3A0A1A2A3

Y0Y1Y2Y3

MUX_41

1

0101

0101

010101

0101

Task 2-6: Build and Test a 1-to-2 Demultiplexer

Cut and paste your LogicWorks™ 1-bit , 1-to-2 demux circuit here:

13

D

Y/~Z

Z

Y

Cut and paste your LogicWorks™1-bit , 1-to-2 demux subcircuit here:

DY/~Z

YZ

DEMUX_1

Test your 1-bit , 1-to-2 demux subcircuit and record the results in Table 6. Cut and paste your LogicWorks 1-to-2 demux subcircuit testing set up.

DY/~Z

YZ

DEMUX_1

01

01

0

0

14

Table 6 Debug checkmark

Debug checkmark

Y/~Z D Y Z Circuit Subcricuit0 0 0 0 X X0 1 0 1 X X1 0 0 0 X X1 1 1 0 X X0 0 0 0 X X0 1 0 1 X X1 0 0 0 X X1 1 1 0 X X

Task 2-7: Repackage the 1-to-2 Demux as a 1-to-2 Decoder

Cut and paste your LogicWorks™ 1-to-2 decoder subcircuit here:

ENA0

Y1Y0

DECODER_1

Test your 1-to-2 Decoder subcircuit and record your results in Table 7. Cut and paste your LogicWorks 1-to-2 decoder subcircuit testing set up.

ENA0

Y1Y0

DECODER_1

01

01

0

0

Table 7EN A0 Y0 Y10 0 0 0 0 1 1 01 0 0 01 1 0 1 0 0 0 00 1 1 01 0 0 0 1 1 0 1

15

Task 2-8: Build and Test a 2-to-4 Decoder

Cut and paste your LogicWorks™ 2-to-4 decoder circuit here:

EN

A0

A1

Y0

Y1

Y2

Y3

Test your 2-to-4 decoder circuit and record your results in Table 8. Cut and paste your LogicWorks 2-to4 decoder subcircuit testing set up.

ENA0A1

Y3Y2Y1Y0

DECODER_2

01

01

01

0

00

0

Table 8 Debug checkmarkEN A1 A0 Y0 Y1 Y2 Y3

0 0 0 0 0 0 0 X

0 0 1 0 0 0 0 X

0 1 0 0 0 0 0 X

0 1 1 0 0 0 0 X

16

1 0 0 1 0 0 0 X

1 0 1 0 1 0 0 X

1 1 0 0 0 1 0 X

1 1 1 0 0 0 1 X

Cut and paste your LogicWorks™ 2-to-4 decoder subcircuit here:

ENA0A1

Y3Y2Y1Y0

DECODER_2

Test and verify your 2-to-4 decoder subcircuit and place a mark in the checkmark column of Table 8 for the values you test. Cut and paste your LogicWorks 2-4 decoder subcircuit testing set up.

ENA0A1

Y3Y2Y1Y0

DECODER_201

01

01

0

00

0

Task 2-9: Design, Build & Test a 4-to16 Decoder Using 2-to-4 Decoders

Cut and paste your LogicWorks™ 4-to-16 decoder circuit, constructed from copies of the subcircuit developed in Task 2-7, here:

17

ENA0A1

Y3Y2Y1Y0

DECODER_2

ENA0A1

Y3Y2Y1Y0

DECODER_2

ENA0A1

Y3Y2Y1Y0

DECODER_2

ENA0A1

Y3Y2Y1Y0

DECODER_2

ENA0A1

Y3Y2Y1Y0

DECODER_2

A1A0

A3A2EN

Y00Y01Y02Y03

Y04Y05Y06Y07

Y08Y09Y10Y11

Y12Y13Y14Y14Y15

18

Test your circuit, with EN set to 1, and record your results in Table 9. Cut and paste your LogicWorks 4-16 decoder circuit testing set up.

ENA0A1

Y3Y2Y1Y0

DECODER_2

ENA0A1

Y3Y2Y1Y0

DECODER_2

ENA0A1

Y3Y2Y1Y0

DECODER_2

ENA0A1

Y3Y2Y1Y0

DECODER_2

ENA0A1

Y3Y2Y1Y0

DECODER_2

A1A0

A3A2EN

Y00Y01

Y02Y03

Y04

Y05Y06

Y07

Y08Y09

Y10

Y11

Y12

Y13

Y14Y14Y15

0 1

0 1

0 10 1

0 10

0

0

0

00

0

00

0

0

00

00

Table 9Debug

checkmark

A3 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y150 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X

0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 X

1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 X

1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 X

1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 X

19

Cut and paste your LogicWorks™ 4-to-16 Decoder subcircuit here:

ENA0A1A2A3

Y15Y14Y13Y12Y11Y10Y09Y08Y07Y06Y05Y04Y03Y02Y01Y00

DECODER_4

Test and verify that your subcircuit is working properly and place a mark in the checkmark column of Table 9 next to values that you tested. Cut and paste your LogicWorks 4-to-16 subcircuit testing set up.

ENA0A1A2A3

Y15Y14Y13Y12Y11Y10Y09Y08Y07Y06Y05Y04Y03Y02Y01Y00

DECODER_4

0

0

0

0

0

0 1

01

01

01

Task 2-10: Backup Your Files

Did you backup your files to a NEW directory?_________YES___

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SIMULATION LAB 2: LAB REPORT GRADE SHEET

Name:Instructor Assessment

Grading Criteria Max Points Points Lost

Template

Neatness, Clarity, and Concision 5

Description of Assigned Tasks, Work Performed & Outcomes MetTask 2-1: Design a Full Adder 10

Task 2-2: Build, Debug and Test a 1-Bit Full Adder 10Task 2-3: Design, Build and Test a 4-Bit Full Adder 11Task 2-4: Design, Build and Test a MUX 10

Task 2-5: Build a 2-Input 4-Bit Multiplexer 10Task 2-6: Build and Test a 1-to-2 Demultiplexer 12Task 2-7: Repackage the 1-to-2 Demux as a 1-to-2 Decoder 10Task 2-8: Build and Test a 2-to-4 Decoder 12Task 2-9: Design, Build & Test a 4-to-16 Decoder Using 2-to-4 12

Self-Assessment Worksheet (The content of the self-assessment worksheet will not be graded. Full credit is given for including the completed worksheet.)

(5 extra points)

Points Lost

Lab Score Late Lab

Lab Score

21

SELF-ASSESSMENT WORKSHEET

Put “X’s” in the table below indicating how strongly you agree or disagree that the outcomes of the assigned tasks were achieved. Use ‘5’ to indicate that you ‘strongly agree’, ‘3’ to indicate that you are 'neutral', and ‘1’ to indicate that you ‘strongly disagree’. Use ‘NA’, ‘Not Applicable’, when the tasks you performed did not elicit this outcome. Credit will be given for including this worksheet with your lab report; however, your responses will not be graded. They are for your instructor’s information only.

Table __: Self-Assessment of Outcomes for Simulation Lab 2: 4-Bit Full Adder, Multiplexer & Decoder.

After completing the assigned tasks and report, I am able to:

5 4 3 2 1 NA

A POS or SOP form of a full adder. X

A 4-bit full adder. X

A 2-to-1 multiplexer. X

A 4-bit, 2-to-1 multiplexer. X

A 1-to-2 decoder. X

A 2-to-4 decoder. X

A 4-to-16 decoder. X

Write below any suggestions you have for improving this laboratory exercise so that the stated learning outcomes

are achieved.

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