SIMULATION AND ANALYSIS OF AREA, DELAY EFFICIENT FFT

SIMULATION AND ANALYSIS OF AREA, DELAY EFFICIENT FFT ARCHITECTURE FOR OFDM

APPLICATIONS

Manimaran.A

Associate Professor, Department of ECE, Karpaga Vinayaga College of Engineering and Technology,

Chinna Kolambakkam - 603308 , Tamil Nadu

Dr.Aby.k.Thomas

Professor, Department of ECE, Hindustan institute of technology and science,

Padur,Chennai , Tamil Nadu

Abstract Objectives: The proposed work is to simulate and to find an efficient method that providesReduction in Delays, LUT’s,

Slices and Power Consumption. (i)R4SDC FFT structure offers 4.54% reduction in Slices, 8.78% reduction in LUTs,

40.83% reduction in delay and 18.18% reduction in power consumption than the R2SDF FFT structure. (ii) SDF FFT is

better in the perspective of high speed & high throughput and MDC FFT is better in the perspective of less hardware

utilization & lower power consumption. Hence Adaptive FFT is used for high speed, low area and low power applications.

(iii) 32-pt Split Radix Multipath delay commutator offers 25.1% reduction in LUTs, 47.13% reduction in Flipflops and

30.89% reduction in slices and 43.63% power reduction than Mixed Radix-2,4 and 8 FFT. (iv) Phase-1 proposal i.e.

Combined Radix-2,4 and 8 based SDF offers 49.75% Reduction in LUT’s, 31.29% Reduction in Slices, 13.09% Reduction in

Delay and 45.84% Reduction in Power Consumption than R2SDF.

Findings:32-point Split Radix based Multipath Delay Commutator is efficient in terms of area, delay and power.

Keywords:Fast Fourier Transform (FFT), Discrete Fourier Transform (DFT),Decimation in Time (DIT), Decimation in

Frequency (DIF), Look Up Tables (LUTs), Single PathDelay Feedback (SDF), Single Path Delay Commutator (SDC), Multipath

Delay Commutator (MDC), Multipath Delay Feedback (MDF), Very Large Scale Integration (VLSI),OFDM

1. INTRODUCTION

FFT is an important aspect of many Digital Signal

Processing Applications and Systems. FFT speeds up

the computation of DFT. The results of the FFT are

same as that of DFT; the only difference is that the

algorithm usually runs much faster and with less

resources. Wide band Orthogonal Frequency Division

Modulation (OFDM) Systems, Biomedical

Instrumentation and Radar Usage in Military Domain

are some of the applications requiring high speed and

large point FFT Systems as one of the key components.

Orthogonal Frequency Division Multiplexing (OFDM)

and Software Defined Radio (SDR) technology

provides efficiency in

cost, flexibility and power to drive and establish long

distance communications.

Traditionally, it is not possible to transmit

timing signal over a long distance. Thus it is required to

design the conversion process of timing signal into

frequency signal. Fast Fourier Transformation (FFT)

technique is one of the important frequency

transformation techniques in which twiddle factor

multiplication performs the conversion process.

Twiddle factor is also referred to as rotational factor. In

twiddle factor multiplication, the frequency response of

corresponding timing signal should be found with the

help of amplitude and phase shift of the corresponding

signal. In OFDM transmitter, Inverse Fast Fourier

Transformation (IFFT) technique is used to convert

frequency signal into time domain signals. Similarly

Journal of Xi'an University of Architecture & Technology

Volume XII, Issue IV, 2020

ISSN No : 1006-7930

Page No: 5548

OFDM receiver has Fast Fourier Transformation (FFT)

technique is used to convert time domain signal into

frequency domain signals.

Based on conversion techniques, FFT can be

designed in two forms such as Decimation in Time

(DIT) FFT and Decimation in Frequency (DIF) FFT.

Decimation in Time (DIT) FFT:

DIT Algorithm is used to calculate the DFT of an N-

point sequence. Initially the N-point sequence is divided

into two N/2-point sequences, which have even and odd

members of x(n). The N/2-point DFTs of these two

sequences are evaluated and combined to give the N-

point DFT. Similarly the N/2-point DFTs can be

expressed as a combination of N/4-point DFTs. This

process is continued till we are left with 2-point DFT.

Here the sequence x(n) is splitted into smaller sub-

sequences.In case of 2-point DIT FFT, complex

addition and subtraction functions can be exhibited after

performing the twiddle factor multiplications only. The

inputs are bit reversed and the outputs are in natural

order.

Decimation in Frequency (DIF) FFT:

In DIF, the output sequence X(k) is divided into two

N/2-point sequence and each N/2-point sequence are

further divided into two N/4-point sequence. In DIF

FFT complex addition and subtraction functions can be

exhibited before performing the twiddle factor

multiplications. The inputs are in natural order and the

outputs are bit reversed.

BASIC FFT ALGORITHMS:

Radix-2 Algorithm

Figure 1. Radix-2 butterfly FFT.

The radix-2 FFT algorithms (Qadeer S et al.,) are the

simplest form of FFT algorithms. It takes two inputs

and give two outputs. The hardware cost is very cheap,

only two complex adders and one complex multiplier

are needed. The smaller number of FFT outputs are

reused to compute many outputs, thus greatly reducing

the total computation cost. FFTs gain their speed by

reusing the results of smaller and intermediate

computation.

Radix-4 Algorithm

Figure 2. Radix-4 butterfly FFT.

Radix-4 FFT Algorithm is used to enhance the speed by

reducing the computational path. In radix-4 FFT,

thenumber of stages is reduced to 50%. Shorter FFT

outputs are reused to calculate many outputs. Thus the

total computational cost is greatly reduced. In

comparision of radix-2 FFT, the number of complex

multiplication is reduced by 25%, but the number of

complex additions is increased by 50% in radix-4 FFT.

In radix-4 butterfly structure, 8 complex adders and 3

complex multipliers are needed. Hardware

implementation cost is three times more than that of

radix-2 FFT.

Radix-8 Algorithm

Figure 3. Radix-8 butterfly FFT

Radix- 8 FFT algorithm, was used to enhance the speed

of the FFT processor. In radix-8 FFT, the number of

computational stages are reduced to 75%. Compared with radix-2 and radix-4 FFT, the computational path

will be significantly reduced in radix-8 FFT.

Radix-8 FFT



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In Radix-2 FFT, the real addition is 1032, and

real multiplication is 264. In Radix-4 FFT, the real

addition is 976, and real multiplication is 208. In Radix-

8 FFT, the real addition is 972, and the real

multiplication is 204.

PIPELINE FFT STRUCTURES:

Different types of feedback and commutator structures

are used in frequency transformation process. The types

of feedback and commutator structures are as follows,

Single path Delay Feedback (SDF) FFT

Multipath Delay Commutator (MDC) FFT

Single path Delay Commutator (SDC) FFT

Multipath Delay Feedback (MDF) FFT

In perspective of Very Large Scale Integration (VLSI)

system design, every feedback structure provide high

speed operation and every commutator structures

provide less area utilization and lower power

consumption. In other hand, SDC and MDF

architectures are used to combine both advantages.

2. EXISTING WORK

(i)OFDM USING ADAPTIVE FFT

R2SDF:

8-point R2SDF has 3 stages and each stage has 1 delay.

In each stage N/2 delay element is used. It performs

signed addition of 8 bits and signed subtraction of 8

bits. Since less number of computations are performed,

the speed will be high. Since the butterfly structure is

complex, silicon size and power consumption will

increase.

R2MDC:

Based on pipelining technique, delay elements are

increased in order to reduce the chip size. Since number

of delay elements increases, the speed will be low. Chip

size and power consumption will be greatly reduced.

Adaptive FFT:

This model consists of both R2SDF and R2MDC

Structures. It also uses a control logic block to select the

required structure based on the SNR Values.

`

Figure 4. ADAPTIVE FFT

When SNR=0, the signal strength is weak and the

adaptive model detects SDF FFT for performing high

speed operation.

When SNR=1, the signal strength is high and the

adaptive model detects MDC FFT for low area and low

power application. Future application of Adaptive FFT

are OFDM, SDR and MANET (Mobile Ad-Hoc

Network).

(ii)PIPELINED R4SDC FFT:

R4SDC provides high throughput rate and low

hardware complexity. Pipelined R4SDC is efficient in

terms of latency, speed, area and frequency.

R4SDC reduces hardware utilization than R4SDF. It

offers 4.54% Reduction in Slices, 8.78% Reduction in

LUTs, 40.83% Reduction in Delay and 18.18%

Reduction in Power Consumption than R4SDF.

R4SDF:

Inputs are given serially. R4SDF increases speed but

does not reduce hardware utilization, power

consumption and frequency. R4SDF is efficient in

terms of utilization of memory and multipliers. Memory

requirement is N-1.

R4SDC:

Each and every stage is connected with commutator

instead of feedback. It is effective to reduce area, delay

and power consumption. It increases frequency. It

reduces hardware utilization, power consumption and

improves speed of the processor.

R4SDC has less computational path to perform

FFT Function.The R4SDC FFT architecture provides

high throughput rate and low hardware complexity.

Control Logic

(SNR values

from

Modulation

technique)

R2SDF

FFT

R2MDC

FFT

Modulation

signals

For high speed

application

For lower

power

consumption

application



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Figure 5. ARCHITECTURE OF 16-PT R4SDC

R4SDC Architecture consists of Processing Elements,

Commutator and Delay. Complex Value Addition and

Subtraction operation are done in the processing

element. Commutator is used to convert one form of

signal to another form of signal. Twiddle factoris used

to reduce shift and adder values. Multiplexer is used to

control signals.

(iii)32-PT SPLIT RADIX BASED MDC

FFT:

It reduces hardware utilization and power consumption.

Split Radix using MDC increases speed and throughput

of the processor. It reduces power, slices and LUTs.32

point split radix MDC FFT is used to reduce the number

of adder and subtractor operation. FFT processor can

achieve high throughput by using pipelined data path

scheme and multipath delay Commutator structure.

Processor performance can be improved by using

multiple number of delays. The number of arithmetic

operations in Split Radix based MDC is greatly

reduced.

MDC achieves N times throughput of SDF at the cost of

high memories, high number of complex adders and

multipliers.32-point Split Radix using MDC gives area

reduction of 17.72% and gives power reduction of

43.63%. It gives better performance and is efficient

compared to 32-point Mixed Radix-2,Radix-4 and

Radix-8 FFT.It offers 25.1% Reduction in LUTs,

47.13% Reduction in Flipflops, 30.89% Reduction in

Slices and 43.63% Power Reduction.

Figure 6.32-PT SPLIT RADIX BASED MDC

(iv)COMBINED RADIX-2,4 AND 8

BASED SDF:

This method has lesser amount of computational path

and also enhance the performance of the FFT Processor.

In SDF architecture, the data sequences of inputs pass

through one single path. The butterfly processing

element performs the computation on data. The addition

and subtraction operation is done in butterfly elements.

The carry select adder circuit is used for adder

operation. This adder structure is very efficient in this

architecture. It drastically reduces the occupied slices,

power consumption and latency. Computational stages

are reduced than the R2SDF.

Used for low power applications. It has identical

number of multipliers but smaller number of stages than

R2SDF FFT. It offers 49.75% reduction in LUTs,

31.29% reduction in Slices, 13.09% reduction in delay

and 45.84% reduction in power consumption than

R2SDF FFT.



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Figure 7. COMBINED RADIX-2,4 & 8 BASED SDF

3. PROPOSED WORK

The proposed work is to simulate and to find an

efficient method for providing reduction in delays,

number of LUT’s, slices and power consumption by

comparing the Existing works : OFDM using Adaptive

FFT, Pipelined R4SDC FFT, 32-Pt Split Radix based

MDC and Combined Radix-2,4 and 8 based SDF. The

Device Utiliztion Summary, Delay Analysis and Power

Analysis results of the above 4 methods are compared to

find the efficient method of FFT.

4. RESULTS AND DISCUSSION

By using MODELSIM 6.3C, the Adaptive FFT,

Pipelined R4SDC, 32-Pt Split Radix based MDC and

Combined Radix-2, 4, and 8 based SDF FFT has been

simulated.

The simulation result of Adaptive FFT is shown

in the Figure 8.

Figure 8. SIMULATION RESULT – ADAPTIVE FFT

The simulation result of Pipelined R4SDC is

shown in the Figure 9.

Figure 9. SIMULATION RESULT – R4MDC



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The simulation result of 32-pt Split Radix based

MDC is shown in the Figure 10.

Figure 10. SIMULATION RESULT – 32-PT SPLIT

RADIX MDC

The simulation result of Combined Radix-2, 4

and 8 FFT based SDF is shown inthe Figure 11.

Figure 11. SIMULATION RESULT – COMBINED

RADIX-2,4 & 8 SDF

The Xilinx ISE 12.4C design tool is used for

synthesizing the performance of the FFT architecture.

Table 1 illustrates the comparison analysis of

the Number of Occupied Slices, LUT’s, Delays and

Power Consumption by using the methods : Adaptive

FFT, Pipelined R4SDC, 32-Pt Split Radix based MDC

and Combined Radix-2, 4, and 8 based SDF FFT.

Parameters Slices LUTs Delay

(ns)

Power

(w)

Adaptive

FFT

600 1157 4.931 1.007

Pipelined

R4MDC

676 1313 1.943 2.432

Split Radix

– MDC

63 45 1.061 0.321

Combined

Radix-SDF

303 266 1.971 1.007

Table 1. COMPARISION ANALYSIS

Figure 12 illustrates the performance evaluation

of Adaptive FFT, Pipelined R4SDC, 32-Pt Split Radix

based MDC and Combined Radix-2, 4, and 8 based SDF

FFT.

Figure 12. PERFORMANCE EVALUATION

60

0

11

57

4.9

31

1.0

07

67

6

13

13

1.9

43

2.4

32

63

45

1.0

61

0.3

21

30

3

26

6

1.9

71

1.0

07

NO . OF OCCUPIED

SL ICES

NO. OF LUTS

D ELA Y(NS) POWER(W)

ADAPTIVE FFT

R4SDC

SPLIT RADIX - MDC

COMBINED RADIX-2,4 AND 8 - SDF



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5. CONCLUSION

The comparision analysis is done based on the Number

of LUT’s, Slices, Delay and Power Consumption. The

goal is to find the efficient method which provides

better reduction in Slices, LUT’s, Delay and Power.

The performance evaluation chart in Figure 12

illustrates that the 32-point Split Radix based Multipath

Delay Commutator is efficient in terms of area, delay

and power.Thus, this design is particularly useful for

low area and low power applications such as WLAN,

OFDM etc.

6. REFERENCES

1. Manimaran.A, Sudheer.S.K. A Novel VLSI Based

Pipelined Radix-4 Single-Path Delay Commutator

(R4SDC) FFT. International Journal of Computer

Technology and Applications 2016; 9(6), 2016, pp. 2767-

2775. 2. Manimaran.A, Aby.K.Thomas. A Novel FFTArchitecture

for an efficient utilization of OFDM using Adaptive FFT.

3. Manimaran.A, Aby.K.Thomas. Design of 32 point Split

Radix based Multipath Delay Commutator FFT

architecture for low power application. 4. Jayakumar.D, Logashanmugam.E. Design of Combined

Radix-2, Radix- 4 and Radix-8 based Single Path Delay

Feedback (SDF) FFT. Indian Journal of Science and

Technology, 2016; Vol 9(45), DOI:

10.17485/ijst/2016/v9i45/103389, December 2016. 5. Malathy.K and Rabi.BJ. ANovel VLSI based Radix-2

Single Path Delay Commutator (R2SDC) FFT

Architecture Design. Indian Journal of Science and

Technology, 2016 ; 9(11). 6. Jayaram K, Arun C. Survey report for Radix-2, 4 and 8

FFT algorithms. International Journal of Innovative

Research in Science, Engineering and Technology. 2015;

4(7).

7. Wang.Z. Liu.X, He.B, Yu.F, A combined SDC-SDF

Architecture for Normal I/O Pipelined Radix-2 FFT.

IEEE Transactions on Very Large Scale Integration

(VLSI) Systems, Vol.23, No.5, pp.973-977, 2015.

8. Arik.S.O, Askarov.D and Kahn.J.M, Adaptive

Frequency-domain equalization in mode-division

multiplexing systems. Journal of Lightwave

Technology, Vol.32, Issue.10,pp: 1841-1852, 2014. 9. Kim.G, Shin.S.K, Sunwoo.MH, New Parallel MDC FFT

Processor with efficient scheduling scheme. Circuits and

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SIMULATION AND ANALYSIS OF AREA, DELAY EFFICIENT FFT