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1) PROGRAM:Write a VHDL program to implement a half -adder using logic gates.entity a1r is

Port ( a : in STD_LOGIC;

b : in STD_LOGIC;

sum : out STD_LOGIC;

carry : out STD_LOGIC);

end a1r;

architectureBehavioral of a1r is

begin

sum

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2) PROGRAM:Write a VHDL program to implement a full adder using basic logic gates.entity a2r is

Port ( a : in STD_LOGIC;

b : in STD_LOGIC;

c : in STD_LOGIC;

sum : out STD_LOGIC;

carry : out STD_LOGIC);

end a2r;

architecture Behavioral of a2r is

begin

sum

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3) PROGRAM:Write a VHDL program to implement a Full Adder using half-adder.entity a21r is

Port ( a : in STD_LOGIC;

b : in STD_LOGIC;

c : in STD_LOGIC;

sumfinal :inout STD_LOGIC;

carry_out : out STD_LOGIC);

end a21r;

architecture Behavioral of a21r is

component halfadder

port(x,y :in std_logic;

sum,carry:outstd_logic);

end component;

component orgate

port(x,y:in std_logic;

n:out std_logic);

end component;

signal sum1,carry1,carryfinal:std_logic;

begin

out1: halfadder port map(a,b,sum1,carry1);

out2:halfadder port map(sum1,c,sumfinal,carryfinal);

out3:orgate port map(carry1,carryfinal,carry_out);

endBehavioral;

entityhalfadder is

port (x,y : in bit ;

sum,carry : out bit);

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endhalfadder;

architecture Behavioural of halfadder is

begin

sum

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4) PROGRAM:Write a VHDL program to implement a 4x1 mux using ?: statement.entity mulcond2 is

Port ( a : in STD_LOGIC;

b : in STD_LOGIC;

c : in STD_LOGIC;

d : in STD_LOGIC;

sel : in STD_LOGIC_VECTOR (1 downto 0);

x : out STD_LOGIC);

end mulcond2;

architectureBehavioral of mulcond2 is

begin

x

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5) PROGRAM:Write a VHDL program to implement a 4x1 mux using If-else statement.entity mul2rk is

Port ( a : in STD_LOGIC;

b : in STD_LOGIC;

c : in STD_LOGIC;

d : in STD_LOGIC;

sel : in STD_LOGIC_VECTOR (1 downto 0);

x : out STD_LOGIC);

end mul2rk;

architectureBehavioral of mul2rk is

begin

process(sel)

begin

ifsel="00"then

x

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6) PROGRAM: Write a VHDL program to design a 4x1 mux using case statement.entity mul1r is

Port ( a : in STD_LOGIC;

b : in STD_LOGIC;

c : in STD_LOGIC;

d : in STD_LOGIC;

x : out STD_LOGIC;

sel : in STD_LOGIC_VECTOR (1 downto 0));

end mul1r;

architectureBehavioral of mul1r is

begin

process(sel,a,b,c,d)

begin

CASE (sel) is

when "00"=>xxxx

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7) PROGRAM: Write a VHDL program to implement a BCD to Gray converter.entitybcd is

Port ( a : in STD_LOGIC_VECTOR (3 downto 0);

b : out STD_LOGIC_VECTOR (3 downto 0));

endbcd;

architectureBehavioral of bcd is

begin

b(3)

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8) PROGRAM:Write a program to implement a J-K flip flop.entity jk1 is

Port ( clk : in STD_LOGIC;

reset : in STD_LOGIC;

J : in STD_LOGIC;

K : in STD_LOGIC;

Q : out STD_LOGIC;

QBAR : out STD_LOGIC);

end jk1;

architectureBehavioral of jk1 is

signal state: std_logic;

signal input: std_logic_vector(1 downto 0);

begin

input

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when others =>

null;

end case;

end if;

end process;

Q

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9) PROGRAM:Write a program to implement a D flip-flop.entity dff1 is

Port ( d,clk : in STD_LOGIC;

reset : in STD_LOGIC;

q : out STD_LOGIC);

end dff1;

architectureBehavioral of dff1 is

begin

process(clk,reset)

begin

if(reset='1')then

q

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10)PROGRAM: Write a program to implement a 4-bit unsigned comparator.entity comp is

Port ( a : in STD_LOGIC_VECTOR (3 downto 0);

b : in STD_LOGIC_VECTOR (3 downto 0);

less : out STD_LOGIC;

greater : out STD_LOGIC;

equal : out STD_LOGIC);

end comp;

architectureBehavioral of comp is

begin

process(a,b)

begin

if(a

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endBehavioral;

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11)PROGRAM:Write a VHDL program to implement a BCD counter.entity counter is

Port ( clk : in STD_LOGIC;

rst : in STD_LOGIC;

count : out STD_LOGIC_VECTOR (3 downto 0));

end counter;

architectureBehavioral of counter is

TYPE state IS (zero, one, two, three, four, five, six, seven, eight, nine);

SIGNAL pr_state, nx_state: state;

BEGIN

PROCESS (rst, clk)

BEGIN

IF (rst='1') THEN

pr_state

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nx_state

count

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END PROCESS;

END Behavioral;

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12)PROGRAM: Write a VHDL program to implement a four-bit adder.entity adder1 is

Port ( a,b : in STD_LOGIC_VECTOR (3 downto 0);

sum : out STD_LOGIC_VECTOR (3 downto 0);

carry : out STD_LOGIC);

end adder1;

architectureBehavioral of adder1 is

signal total: STD_LOGIC_VECTOR (4 downto 0);

totalsum

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13)PROGRAM: Write a VHDL program to implement a 0 to 15 counter.entity count1 is

Port ( clk,reset : in STD_LOGIC;

led : out STD_LOGIC_VECTOR(3 downto 0));

end count1;

architectureBehavioral of count1 is

signal counter: std_logic_vector(3 downto 0);

signalprescalar: std_logic_vector(25 downto 0);

begin

process(clk)

begin

if reset ='1' then

counter'0');

prescalar'0');

elsif(clk 'event and clk='1')then

ifprescalar