Silicon single-electron transistors with sidewall depletion gates and their application to dynamic single-electron transistor logic

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 49, NO. 4, APRIL 2002 627

Silicon Single-Electron Transistors With SidewallDepletion Gates and Their Application to Dynamic

Single-Electron Transistor LogicDae Hwan Kim, Suk-Kang Sung, Kyung Rok Kim, Jong Duk Lee, Member, IEEE, Byung-Gook Park, Member, IEEE,

Bum Ho Choi, Sung Woo Hwang, and Doyeol Ahn

Abstract—Novel single-electron transistors (SETs) with side-wall depletion gates on a silicon–on–insulator nanometer-scalewire are proposed and fabricated, using the combination of theconventional lithography and process technology. Clear Coulomboscillation originated from the two electrically induced tunneljunctions and the single Si island between them is observed at77 K. The island size dependence of the electrical characteristicsshows the good controllability and reproducibility of the proposedfabrication method. Furthermore, the device characteristics areimmune to gate bias conditions, and the position of Coulomboscillation peak is controlled by the sidewall depletion gatevoltage, without the additional gate electrode. Based on thecurrent switching by sidewall gate voltage, the basic operationof the dynamic four-input multifunctional SET logic circuit isdemonstrated at 10 K. The proposed SET offers the feasibility ofthe device design and optimization for SET logic circuits, in thatits device parameters and circuit parameters are controllable bythe conventional VLSI technology.

Index Terms—Controllability, conventional lithography, processtechnology, reproducibility, sidewall depletion gates, SOI.

I. INTRODUCTION

SINGLE-ELECTRON transistors (SETs) have recentlyattracted much attention for their potential as the building

blocks of ultra-high density, low power nanoelectronic in-tegrated circuits. Among many approaches using variousmaterials, Si-based SETs have a few advantages in terms of thematurity and variety of the process technology and the possi-bility of integration with conventional MOSFETs. Up to now,various pioneering works for the room temperature operationbased on novel fabrication methods have been demonstrated[1]–[6], but often the purpose of the room temperature operationhas deteriorated the controllability and reproducibility of SETs.Most SETs operating at a high temperature have depended on

Manuscript received July 30, 2001; revised January 2, 2002. This work wassupported by the BK 21 Program and the national program for “Tera-bit LevelNano Device Project” as a part of the 21st Century Frontier Project. The workat iQUIPS was supported by the Creative Research Initiative (CRI) program,Korean Ministry of Science and Technology. The review of this paper was ar-ranged by Editor M. Hirose.

D. H. Kim, S.-K. Sung, K. R. Kim, J. D. Lee, and B.-G. Park are with theInter-University Semiconductor Research Center (ISRC) and School of Elec-trical Engineering, Seoul National University, School of Electrical Engineering,Seoul 151-742, Korea (e-mail: [email protected]).

B. H. Choi, S. W. Hwang, and D. Ahn are with the Institute of Quantum Infor-mation Processing and Systems (iQUIPS), University of Seoul, Seoul 130-743,Korea.

Publisher Item Identifier S 0018-9383(02)03055-1.

somewhat fortuitous phenomena such as unintentionally intro-duced impurities [7], the disorder in quantum wires [8], channeldepletion in constricted part [3], electron-beam irregularity[2], and randomly distributed nanocrystals [9] so that theircontrollability and reproducibility have not been guaranteed.Only a few researchers have described the controllability andreproducibility of their experimental data [10], [11]. In parallelwith the two requirements, it is strongly required that SETs withthe dimension beyond the limit of state-of-the-art lithographyshould be fabricated by the conventional VLSI technologyto optimize the device parameters for the single-electroncircuit and evaluate the usefulness of the hybrid circuit by thecombination of SETs and CMOS devices [12].

On the other hand, SETs with the depletion gate that are basedon an electrically formed island [13]–[15] have the merit in thattheir clear formation mechanism of the tunnel junctions andthe island give the room for the device design and optimiza-tion. However, they also have two main drawbacks: the oper-ation temperature is below the liquid He temperature, and theswitching performance is degraded sensitively by the gate biascondition. The former stems from the limit of lithography, andthe latter from the complicated competition between electricfields of various gate biases.

In this paper, novel SETs with sidewall depletion gates on asilicon–on–insulator (SOI) nanometer-scale wire are proposedand fabricated, using the combination of the conventionallithography and process technology. The important feature ofour fabrication method is that all critical dimensions depend onnot the limit of lithography but the controllability of the con-ventional VLSI technology. The size dependence of the devicecharacteristics shows good controllability and reproducibility.Moreover, fabricated SETs show some unique properties suchas the controllability of the current peak position without anadditional gate, and the device characteristics immune to thegate bias condition. Based on the current peak position controlby the sidewall depletion gates, the feasibility of the dynamicfour-input multifunctional SET logic circuit consisted of twoSETs and one NMOSFET is successfully demonstrated.

II. DEVICE STRUCTURE AND FABRICATION PROCESS

Fig. 1 shows a schematic and cross-section of SET with side-wall depletion gates on an SOI nanowire. Electron channel inan SOI nanowire is formed by the back-gate voltage, and

0018-9383/02$17.00 © 2002 IEEE

628 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 49, NO. 4, APRIL 2002

(a)

(b)

Fig. 1. (a) Schematic diagram of the SET with sidewall depletion gates onan SOI nanowire. The thickness and width of nanowire are 45 nm and 30 nm,respectively. (b) Cross-section of the fabricated SET. Geometrical parametersare marked.

two tunnel junctions are formed by the sidewall depletion gatevoltage . The charge of the electrically formed island is con-trolled by the control gate voltage . The devices were fab-ricated on the 4 10 cm p-type 60-nm-thick top layerof an SOI (100) wafer prepared by SIMOX (separation by im-planted oxygen). This top layer is separated from the Si sub-strate by 415-nm-thick buried oxide. SOI nanowire is formedby the sidewall patterning technique, which is the key processof our fabrication [16]. Fig. 2 shows the schematic diagram ofthe process sequence of SOI nanowire formation. First of all, a40-nm-thick SiO and an 80-nm-thick SiN layer were sequen-tially deposited on the top layer, and patterned by the conven-tional photolithography and reactive ion etching (RIE). Next,amorphous Si is deposited using an low pressure chemical vapordeposition (LPCVD) system so that the edge of the nitride layeris fully covered. Then, the amorphous Si layer is anisotropicallyetched using Clreactive-ion plasma until the whole layer is re-moved except the part at the edge corner of the SiN layer.This amorphous Si sidewall serves as an etch mask for the def-inition of the SOI nanowire. The subsequent chemical etchingof Si N , anisotropic etching of SiOin CHF /CF reactive-ionplasma, and anisotropic etching of Si in Clreactive-ion plasmaform the final SOI nanowire. After stripping the SiOoxidelayer on the Si wire in the HF solution, the oxide spacer isformed around the SOI nanowire, which plays an important rolein the step coverage of the poly-Si sidewall, which will act asthe depletion gate, by substituting smoothly curvilinear shapefor step-like shape around SOI wire. Then, 30-nm-thick SiOlayer is subsequently deposited by a PECVD (plasma enhanced

Fig. 2. Schematics of the process sequence of the formation of SOI nanowireby sidewall patterning technique.

(a)

(b)

Fig. 3. SEM images of SOI nanowire (a) before and (b) after the gateoxidation. Good uniformity of 30-nm-wide SOI wire by the sidewall patterningtechnique efficiently eliminates the possibility of the unintentional tunneljunction formation during the gate oxidation.

chemical vapor deposition) system, forming the sidewall deple-tion gate oxide. Fig. 3 shows SEM (scanning electron micro-scope) images of an SOI nanowire formed by the sidewall pat-terning technique. Very uniform 30-nm-wide Si wire with noirregularities can be created by this method, which effectivelysuppresses naturally formed tunnel junctions during the gate ox-idation, in comparison with the nano-meter scale wire definedby electron-beam lithography [17].

For the electrically induced tunnel junction, two poly-crystalline silicon (poly-Si) sidewall depletion gates aresubsequently formed on an SOI nanowire as follows. The80-nm-thick SiN layer is deposited on the sidewall depletiongate oxide, and then the groove pattern was lithographicallytransferred into SiN layer. After the growth of 8-nm-thickSiO by thermal oxidation, during which the gate oxidebecomes thicker locally only under SiN groove, two poly-Si

KIM et al.: SILICON SINGLE-ELECTRON TRANSISTORS 629

(a) (b)

(c) (d)

Fig. 4. SEM images of poly-Si sidewall depletion gates. Space between two sidewall gates (S ) is (a) 40 nm, (b) 90 nm, (c) 140 nm, and (d) 190 nm, respectively.

sidewalls are formed around the edge of SiN groove by the de-position and plasma etching of 35-nm-thick phosphorus-dopedpoly-Si. These sidewalls play a role of the depletion gateswrapping an SOI nanowire. After the deposition of the controlgate oxide, subsequent formation of the poly-Si control gate,ion implantation into regions of source/drain and the controlgate, and the formation of aluminum electrodes have beenperformed. This sequence is compatible with the conventionalCMOS process technology.

The final width of the SOI wire , its thickness, the thick-ness of the control gate oxide , the thickness of the sidewallgate oxide , and the width of sidewall gate were 30 nm,45 nm, 60 nm, 38 nm, and 30 nm, respectively, while the separa-tion between two sidewall gates was controlled in the rangeof 40–190 nm by varying the width of the SiN groove on thesame SOI wafer, which means that the size of Si island is con-trolled. Fig. 4 shows SEM images of poly-Si sidewall depletiongates on SOI nanowire. The sidewall gate structure has a meritin that it can implement a feature size smaller than the limitof lithography and depends on not the lithographical limit butthe controllability of the conventional VLSI technology such asCVD (chemical vapor deposition) and RIE [18]. The proposedstructure is suitable for the planar integration, and the improve-ment of packing density in the integration of SET logic circuitis promising, according to the shape of the SiN groove andthe self-aligned doping technique by the ion implantation.

III. SIZE DEPENDENCE OFDEVICE CHARACTERISTICS

AND DESIGN SCOPE

Fabricated SETs are based on the electrically formed Si islandin an SOI MOSFET inversion layer, so that the shape of island

is close to a thin panel whose top surface is a rectangle with thearea of . Device parameters can be estimated fromthe following simple formulae:

(1)

(2)

(3)

where is the capacitance between the control gate and is-land, and are source/drain tunnel junction capacitances,

is the voltage gain of SETs,is a dielectric constant,is a depletion layer depth by , is a size shrinkage factor ofthe electrically formed island, and is a size-shrinkage factorof the tunnel junction.

The current–voltage (– ) characteristics were measuredwith an HP 4155A precision semiconductor parameter ana-lyzer. The island size dependence of the device characteristicsis shown in Fig. 5. The current oscillation period in the

(drain current)– curve is 80, 123, 210, and 675 mV (cor-responding to 2.0, 1.3, 0.76, and 0.24 aF) respectively,and the maximum Coulomb gap is 45, 59, 76, and104 mV respectively, and the total capacitance of the Si island

is 5.08, 4.14, 3.44, and 2.86 aF respectively, as isvaried from 190 nm to 40 nm. This was extracted fromthe measured contour as a function of and , which iscalled the Coulomb diamond. For example, Fig. 6 shows thecontour plot of an SET with 190 nm of at 15 K. This islandsize dependence suggests that the observed current oscillationstems from single-electron tunneling effect by two electricallyinduced tunnel junctions and the single Si island between them.


(a)

(b)

Fig. 5. The island size dependence of (a) theI –V characteristics, and(b) theI –V characteristics. The curves are vertically shifted by (a) 0.5 nAand (b) 10 nA respectively, for clarity.

Comparing with the device geometry, a shrinkage factorisfrom 0.63 to 0.38, as varies from 190 nm to 40 nm. Thus, thesize of the island is eventually shrunk to 4060% of the definedsize, which can be attributed to two physical origins. One is thatthe size of island along the channel length direction is smallerthan , by the electric field effect by . The other is that theelectron channel is formed in the deeper location than the topSi/control gate oxide interface due to , so that the effective

increases. If we assume that the length of depletion regionpenetrating into the defined is nearly independent of ,is naturally the increasing function of , which is consistentwith our dependence of .

In order to check the reproducibility of the dependenceof and , we collected the dependences of sev-eral devices, as shown in Fig. 7. Note that the data in Fig. 7 aretaken from the seven different SETs with the same, and theerror bar shows the standard deviation for the twenty-one data(setting to be 0, 0.05, and 0.1 V in each SET). Fig. 8shows the size dependence of the critical device parameters de-rived from Fig. 7. Comparing the dependence of and

Fig. 6. The drain current contour plot of an SET with 190 nm ofS at 15 K.C andK are 5.08 aF and 1.3 from the Coulomb diamond. The guidinglines are marked, considering the oscillation period and the broadening due tothe thermal energy.

Fig. 7. Island size dependence of�V and �V . They are clearlymodulated by the island size. Data are taken from the seven different SETswith the same island, and the error bar shows the standard deviation for the 21data (settingV to be 0,�0.05, and�0.1 V in each SET).

in Fig. 8 with the form of (1) and (2), extracted fromthe experimental shows a good linearity with , whichis very reasonable, since the length of depletion region just pro-vides an offset to . On the other hand, we put emphasis onthat the linear dependence of on is much more promi-nent than that of . The error bars of make the linear depen-dence much less meaningful, in comparison with those of.In addition, increases from 0.185 to 1.3, as the island size orthe capacitive coupling between the gate and island increases.Fig. 8 verifies that the device parameters in (1)–(3) can be repro-duced and controlled by the conventional Si VLSI technology.In comparison with other researches for the controllability andreproducibility of the fabrication of Si-based SETs [10], [11],our data show the size dependence of both gate capacitance and


Fig. 8. Island size dependence of the device parameters. There is a tradeoffbetween the operation temperature and the voltage gain. The lines by the linearregression agree very well with the form of (1)–(3).

tunnel junction capacitance, and clear oscillation of ratherthan that of conductance at 77 K.

In terms of the optimization of device parameters, (1)–(3)suggest that there is a tradeoff between the operation temper-ature and in and . Considering that a largewould hinder the effective tunneling of electron, (e.g.,thickness or doping concentration of an SOI nanowire) is prob-ably the most efficient control parameter for the high temper-ature operation and the high voltage gain. From the viewpointof SET logic application, the strong coupling between the de-pletion gate and the SOI wire as well as the strong coupling be-tween the control gate and the island is desirable, and our oxidespacer around the SOI wire described previously in Section IIis advantageous for these two requirements, because the controlgate as well as the sidewall depletion gates is wrapping the SOInanowire, i.e., because the region of SOI wire between two side-wall gates is coupled with the control gate in the edge surfaceas well as in the top surface.

IV. BIAS DEPENDENCE OFDEVICE CHARACTERISTICS

AND CURRENT PEAK POSITION CONTROL

In the case of the previously reported SETs based on the elec-trically induced island, the merit of clear formation mechanismof tunnel junctions and island has been cancelled by the devicecharacteristics sensitive to gate bias conditions. A small numberof current peaks are observed only in the subthreshold region[14], [15], and the Coulomb oscillation is washed out at a con-stant depletion gate voltage and a constant temperature, as thecontrol gate voltage increases. These experimental results aredue to the complicated competition between electric field ef-fects of various gates.

Fig. 9 shows the gate bias dependence of the Coulomb os-cillation of the fabricated SET. As increases at a constant

, the PVR (peak-to-valley ratio) of the current oscillation ismaintained, and is invariant. These characteristics meanthat the potential barrier is immune to the field effect ofi.e., the strong controllability of the potential barrier by .

Fig. 9. Gate bias dependence of characteristics of SET withS of 40 nm at77 K. The position of Coulomb oscillation peak is modulated byV , which isdue to the sharing of island charge between the top control gate and sidewalldepletion gates. The level ofI decreases as the tunneling resistance increasesby V .

Fig. 10. Electron concentration along an SOI wire length direction. Poissonequation is solved by 3-D device simulator DAVINCI. The geometry parametersfor simulation are:S = 90 nm,W = 30 nm,T = 60 nm,T = 38 nm,L = 2�m. The size of Si island is seldom influenced, when increasingV .The potential of the island is independently controlled byV .

This immunity stems from the three-dimensional (3-D) struc-ture of the sidewall depletion gate wrapping the SOI nanowire.This bias dependence can be reproduced by 3-D device simu-lator DAVINCI, into which 3-D structure of sidewall depletiongate wrapping an SOI nanowire is incorporated. Fig. 10 showsthe simulation result for the dependence of the electron con-centration. The potential barrier is well maintained and the po-tential in the island is independently controlled by .

On the other hand, in the case of varying with a fixed ,both the current level and the position of Coulomb oscillationpeak are modulated by , as shown in Fig. 9. The modulationof the level of is well explained by the increase of tunnelingresistance by . And the modulation of the peak position isoriginated from the sharing of the island charge between the topcontrol gate and sidewall depletion gates. Since the modulationof the depletion width by the variation of results in the mod-ulation of the lateral size of Si island, is expected to in-crease as becomes negatively larger. As is changed from0.1 V to 0.1 V, however, is seldom varied. In order to


Fig. 11. TheV dependence of electrostatic potential along an SOI wirelength direction, which is calculated by 3-D device simulator DAVINCI.

understand this phenomenon, it should be noted that the varia-tion of the width of potential barrier by is about ten percentof the lateral size of Si island, which is confirmed by the 3-Ddevice simulation result in Fig. 11. In addition, the value ofat the current peak should increase, in order to compensate theincrease of the potential energy at the Si island due to the ex-pansion of the depletion region. Thus, at the current peak, thesize of the island remains more or less the same. This is anotherphysical origin of the immunity of to .

The position of Coulomb oscillation peak controlled byis very useful, from the viewpoint of SET logic. Based on theconservation of the island charge, the relationship between thedisplacement of the oscillation peak in the axis bythe change of is derived as follows

(4)

where is the capacitance between the sidewall gate and theisland, which is determined by the device geometry. Equation(4) suggests that the shift of Coulomb oscillation peak can becontrolled by the process parameter such asand , whosedimension is determined not by the lithography but by CVD,RIE, and thermal oxidation.

In comparison with other works based on physically formedSi single island [1], [10], our device structure has a unique prop-erty in that the sidewall depletion gate can control the positionof Coulomb oscillation peak without additional gates, and thetunneling resistance can be optimized by. This is an advan-tageous feature in implementing SET multi-input logic gates,which is demonstrated in Section V.

V. DYNAMIC MULTI-FUNCTIONAL SET LOGIC CIRCUITS

When compared with the static CMOS-type SET logic [19],[20], the concept of dynamic SET logic [21] is more promising,because the inherent drawback of low voltage gain becomes lessconspicuous. In the dynamic SET logic, SETs play the role oflow power current switches, i.e., pull-down devices.

On the other hand, the feasibility of multigate SET logic hasbeen already demonstrated [22], though its signal was limited

Fig. 12. Equivalent circuit diagram of the dynamic multifunctional SET logicgate composed of one NMOSFET and two SETs.V s are two logic inputs, andthe output is determined by the states of the combinations of twoV s.

(a)

(b)

Fig. 13. Gate bias dependence of (a) SET1 and (b) SET2. Logical “HIGH”state corresponds to 0.1 V and “LOW” state to 0 V.

to SET current. Besides, the concept of multifunctional SETlogic based on the control of peak position has been recentlyproposed, using a nonvolatile memory operation [6].

In this work, the dynamic four-input multifunctional SETlogic circuit composed of two SETs and one NMOSFET isdemonstrated at 10 K, based on the peak position controlby . Fig. 12 shows the equivalent circuit diagram of thedynamic multifunctional SET logic, where , ,and are four logical inputs. NMOSFET switching by theclock signal is utilized as a pull-up device.

Fig. 13(a) and (b) show the device characteristics of two SETsused in the implementation of dynamic SET logic. Both SET1and SET2 have the of 90 nm, which correspond to of210 mV and of 0.76 aF. In the case of SET1, the position


Fig. 14. Experimental demonstration of the basic operation of the dynamicmultifunctional SET logic circuit. The measurement was performed at 10 K,and the supply voltage was 20 mV. Though voltage levels of input andoutput are mismatched, the waveform of output voltage shows the full swingoperation. Four waveforms of output voltages show the successful operationsof V + V , V � V , V � V , andV � V , respectively,corresponding to the combinations ofV andV .

of Coulomb oscillation peak is shifted by 70 mV, when ischanged by 100 mV as shown in Fig. 13(a). From (4), ofSET1 can be extracted to be about 0.27 aF. Considering that thesupply voltage of SET logic, , is generally given by a half of

and the input voltage is nearly , the control of par-tial circuit parameters by the conventional VLSI technology isfeasible in the proposed SET structure. Fine peaks of the currentof SET2 in Fig. 13(b) can be attributed to the quantum energylevel, but more detailed discussion is necessary. For givensof two SETs, SET current flowing through the pull-down pathis determined by the states of the combinations of twos, asshown in Fig. 13(a) and (b).

Fig. 14 shows the experimental demonstration of the basic op-eration of dynamic multifunctional SET logic circuit in Fig. 12.The output load capacitance is charged up to 20 mV duringthe “precharge” period i.e., the ON state of the NMOSFET,and the “evaluation” is executed during the OFF state of theNMOSFET. Four waveforms of output voltages show the suc-cessful operations of , , , and

, respectively, with four combinations of two s.Though voltage levels of input and output are mismatched, the

waveform of output voltage shows the full swing operation.Taking inherently low into account, a voltage amplifier isrequired to match the logic levels of inputs and that of output.

VI. CONCLUSIONS

New SETs with sidewall depletion gates on an SOI nanowireare proposed and fabricated, using the combination of the con-ventional lithography and process technology. The key featureof the proposed fabrication method is that all critical dimensionsdepend on not the limit of lithography but the controllability ofthe conventional VLSI technology such as CVD and RIE. Theclear Coulomb oscillation originated from the two electricallyinduced tunnel junctions and the Si single island between themis observed at 77 K. Furthermore, the island size dependenceof the device characteristics shows the good controllability andreproducibility. Fabricated SET shows some unique propertiessuch as the controllability of the current peak position withoutan additional gate and the device characteristics immune to thegate bias condition. Based on the control of current peak posi-tion by the sidewall depletion gates, the basic operation of thedynamic four-input multifunctional SET logic circuit composedof two SETs, and one NMOSFET is successfully demonstratedat 10 K.

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Dae Hwan Kim was born in Korea on October 24,1972. He received the B.S. and M.S. degrees fromthe School of Electrical Engineering, Seoul NationalUniversity, Seoul, Korea, in 1996 and 1998, respec-tively, where he is pursuing the Ph.D. degree.

His current research interests are Si nanoelectronicdevices and nanoscale CMOS devices.

Suk-Kang Sung was born in Korea in 1973. Hereceived the B.S. and M.S. degrees from School ofElectrical Engineering, Seoul National University,Seoul, Korea, in 1997 and 1999, respectively, wherehe is pursuing the Ph.D. degree.

His current research interests are Si nanoelectronicdevices and single-electron memory.

Kyung Rok Kim received the B.S. and M.S. degreesfrom the School of Electrical Engineering, Seoul Na-tional University, Seoul, Korea, in 1999 and 2001, re-spectively, where he is pursuing the Ph.D. degree.

His current research interest is Si quantumtunneling devices.

Jong Duk Lee (M’79) was born in Youngchun,Kyungpook, Korea, on January 10, 1944. Hereceived the B.S. degree in physics from SeoulNational University, Seoul, Korea, in 1966, andthe Ph.D. degree from the Department of Physics,University of North Carolina, Chapel Hill, in 1975.

He was an Assistant Professor with the De-partment of Electronics Engineering, KyungpookNational University, from 1975 to 1978. In 1978,he studied microelectric technology in HP-ICL,Palo Alto, CA, and soon afterward worked for

the Korean Institute of Electronic Technology (KIET) as the Director ofthe Semiconductor Division. He established the KIET Kumi Facility andintroduced the first polysilicon gate technology in Korea by developing 4 KSRAM, 32 K, and 64 K Mask ROMs, and one-chip 8-bit microcomputers.In July 1983, he moved to the Department of Electronics Engineering, SeoulNational University, as an Associate Professor, which merged with the Schoolof Electrical Engineering in 1992, where he has been Professor since 1988.He established the Inter-University Semiconductor Research Center (ISRC) in1985, and served as the Director until 1989. He served as the Chairman of theElectronics Engineering Department from 1994 to 1996. He was with SamsungDisplay Devices Co., Ltd., as the Head of Display Research and DevelopmentCenter in 1996, on leave from Seoul National University. He concentrated hisstudy on the image sensors such as Vidicon type, MOS type, and also CCDs,for Samsung Display Devices Co. and Samsung Electronics Co. from 1984to 1991. His current research interests include sub-0.1 mm CMOS structureand technology, FEDs, CMOS image sensors, and high-speed SRAM design.He published over 130 papers in the major international scientific journals,including over 65 SCI papers. He has presented more than 180 papers,including 80 international conference papers. He also has registered 11 U.S.,three Japanese, and eight Korean patents.

Dr. Lee is a member of the Steering Committee for International VacuumMicroelectronics Conference (IVMC) and the Korean Conference on Semicon-ductors (KCS). He was the Conference Chairman of IVMC’97 and KCS’98who led the IVMC’97 and the KCS’98. He was also a member of the Interna-tional Electron Devices Meeting (IEDM) Subcommittee on Detectors, Sensors,and Displays operated by IEEE Electron Devices Society from 1998 to 1999.In June 1999, he was elected First President of the Korean Information DisplaySociety.

Byung-Gook Park (M’96) received the B.S. andM.S. degrees in electronics engineering from SeoulNational University, Seoul, Korea, in 1982 and1984, respectively, and the Ph.D. degree in electricalengineering from Stanford University, Stanford, CA,in 1990.

From 1990 to 1993, he worked at the AT&T BellLaboratories, Murray Hill, NJ, where he contributedto the development of 0.1-mm CMOS and its charac-terization. From 1993 to 1994, he was with Texas In-struments, Dallas, TX, developing 0.25-mm CMOS.

In 1994, he joined the School of Electrical Engineering, Seoul National Uni-versity, as an Assistant Professor, and he is currently an Associate Professor.His current research interests are nanoscale CMOS devices, Si single-electrondevices, organic electroluminescent display, and scanning probe microscopysystem.

Dr. Park was a member of the International Electron Devices Meeting (IEDM)Subcommittee on Solid State Devices, operated by IEEE Electron Devices So-ciety in 2001.

Bum Ho Choi received B.S. and M.S. degrees in electronic engineering fromKorea University, Seoul, Korea, in 1996 and 1998, respectively. He is currentlypursuing the Ph.D. degree in electronic engineering from Korea University.

His main research interests are electron transport in low dimensional systemsuch as single-electron devices for the future application to VLSI circuit.


Sung Woo Hwang received the B.S. and M.S. degrees in electronicsengineering from Seoul National University, Seoul, Korea, in 1985 and 1987,respectively, and the Ph.D. degree in electrical engineering from PrincetonUniversity, Princeton, NJ, in 1993.

From 1993 to 1995, he was with the NEC Fundamental Research Laboratory,Tukuba, Japan. Since 1995, he has been with the Department of Electrical Engi-neering, Korea University, Seoul, as an Associate Professor. His research inter-ests are nanostructure fabrication, beam and probe manipulation, quantum de-vices, and single-electronics. He has co-authored more than 60 refereed journaland conference papers. He has been an Associated Director of the Institute ofQuantum Information Processing & Systems, University of Seoul, since 1998.

Dr. Hwang is a member of the American Physical Society.

Doyeol Ahn received the Ph.D. degree in electrical engineering from theUniversity of Illinois, Urbana, in 1988.

While at the University of Illinois, he held a GTE Fellowship. After grad-uation, he worked at the IBM Thomas J. Watson Research Center, YorktownHeights, NY. His work at IBM covered theoretical modeling of quantum-effectdevices and Monte Carlo simulation of the electron transport in submicrom-eter devices. From 1992 to 1996, he was with LG Electronics Research Center,Seoul, Korea, as a Chief Scientist. He is now an Associate Professor with theDepartment of Electrical Engineering, University of Seoul, Seoul, Korea. He isalso a Director of the Institute of Quantum Information Processing & Systems(iQUIPS), which was established in 1998 by the National Creative ResearchInitiatives with Korean government support. He has been working on the theoryof nanostructures and their application to optoelectronic devices, many-bodytheory, the reduced-density-operator description of quantum kinetics in highlyexcited semiconductors, and, more recently, quantum information and quantumcomputation theory. He holds six U.S. patents, has written three book chapters,and has co-authored more than 80 refereed journal and conference papers.

Dr. Ahn is a Member of Tau Beta Pi, Phi Kappa Pi, and the AmericanPhysical Society. He was the recipient of the Ross J. Martin Award and theRobert T. Chien Award from the College of Engineering, University of Illinois,in April 1988, for excellence in research.

Documents

Silicon single-electron transistors with sidewall depletion gates and their application to dynamic single-electron transistor logic