Silicon photonics front-end integration in high-speed 0.25µm SiGe BiCMOS

Lars Zimmermann1 , Karsten Voigt1 , Georg Winzer1 , Dirk Wolansky2 , Sebastian Geisler2 , Harald Richter2

Bernd Tillack2 1Technische Universität Berlin, Fachgebiet Hochfrequenztechnik HFT4 , Einsteinufer 25, 10587 Berlin, Germany

2IHP, Im Technologiepark 25, 15236 Frankfurt/Oder, Germany

Abstract- Modular integration of photonic functionality in the front-end of line of a qualified 0.25 µm SiGe BiCMOS technology is considered. First measurements of electronic & waveguide test structures are presented.

I. INTRODUCTION

A major issue currently under debate in silicon photonics is the optimum integration of photonic functionality in advanced electronics manufacturing processes. Basically, developments follow two major directions: 1. Separation of electronic and photonic manufacturing and integration at the back-end of line (e.g. by stacking of electronic and photonic layers [1]). 2. Quasi-monolithic integration of waveguide optics at the front-end of line, followed by hybrid integration of light sources, if needed. The latter option is so far chiefly pursued by the company Luxtera, who demonstrated true integration of photonic and an electronic layer in photonic integrated circuits (PIC), such as 4x 10 Gb/s transceivers ([2]). In line with current efforts to provide a foundry-like service ([3]) of Silicon photonics fabrication to enable fabless research and development, it would be desirable to have available a foundry service of a front-end integrated Silicon photonics technology. Luxtera’s fabrication technology is, however, based on a proprietary 0.13 µm CMOS process. We propose Silicon photonics front-end integration in a qualified microelectronics fabrication technology, which is already accessible via EUROPRACTICE, a world-wide microelectronics service for shared-cost prototyping. The technology is a 0.25 µm SiGe BiCMOS, which offers very high speed in the bipolar part. SiGe BiCMOS technologies are the ideal baseline for the integration of fast electronics with photonic components. Especially, the SiGe based heterojunction bipolar transistors (HBTs) as key BiCMOS devices offer excellent high speed performance [4, 5]. They enable the fabrication of fast drivers for photonic components such as modulators [6]. The objective of the development work is modular integration of photonic functionality in the existing technology scheme. In the following, first results of the adaptation of bulk Silicon BiCMOS to SOI BiCMOS will be presented. Then, first test results of SOI waveguides realized in the shallow-trench module will be provided.

II. SIGE BICMOS FOR SILICON PHOTONICS

The monolithic integration of photonic components into BiCMOS technology requires SOI substrates to ensure the proper functionality of the waveguide optics. Therefore, the first task is the demonstration of the SiGe BiCMOS performance on SOI substrates.

In the present paper, a qualified 0.25µm BiCMOS technology was adapted from Silicon bulk substrate to 1.4µm SOI substrate with a 1µm buried oxide and compared for both substrate types. In Table 1, basic MOS and HBT parameters are summarized.

Table 1: Basic transistor parameters of 0.25µm BiCMOS measured on Silicon bulk and on SOI substrates

Si-Bulk SOIVT V 0,596 0,592Ioff fA/µm 315 322Ion µA/µm 496 477VT V -0,531 -0,541Ioff fA/µm -505 -414Ion µA/µm -241 -228Beta 151 151IC nA 834 831fT GHz 119 116fmax GHz 180 177τG ps 5,72 5,80

nMOS

pMOS

HBT

Comparing the n- and p channel MOS devices on Si and

SOI substrates, only small differences in threshold voltage (VT), on and off currents (ION), (IOFF) especially for the pMOS are shown. No tuning of these parameters was made because the purpose of this paper was a feasibility study of BiCMOS on SOI.

For the HBT, a very good agreement for all parameters is achieved: Both the static parameters current gain (Beta), collector current (IC), and the dynamic parameters maximum transit frequency (fT), and the maximum oscillation frequency (fmax) show no dependence on the substrate type. Even the gate delay (τG) of CML ring oscillators with 53 stages, used

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to benchmark high frequency performance of digital circuits, delivered nearly no difference for both substrate types.

In result, it was demonstrated that a similar BiCMOS performance on SOI substrate compared to Silicon substrate was achieved. Therefore, the first condition for a successful monolithic integration of photonic components in a BiCMOS technology on SOI was fulfilled.

III. RIB WAVEGUIDES IN SHALLOW TRENCH MODULE

SOI rib waveguide test structures were fabricated using the shallow trench etch. The SOI material featured a BOX layer of 1.0 µm and a Silicon height of 1.4 µm. The rib height was approximately 0.5 µm, requiring the rib width to be smaller 2.0 µm for single mode operation. A cross section through a rib waveguide is shown in Fig. 1 (a). The already noticeable fraction of evanescent field for the chosen waveguide geometry is visible in Fig. 1 (b).

(a) (b) Fig. 1 (a) SEM cross section of SOI rib waveguide realized in ST etch, rib width 1.7 µm, rib height 0.5 µm. (b) Field distribution of fundamental mode.

Waveguides were measured on sample dies from 8”

wafers. Samples were edge polished and an anti-reflection coating was applied. End-fire coupling was used for optical testing. Lensed fibers with a beam-waist diameter of ~ 3µm were employed for the measurements. Intrinsic waveguide losses were determined by the cut-back method using waveguides of different lengths on the same chip. Fig. 2 shows some exemplifying loss data. We obtained an upper limit for the intrinsic loss determined by the measurement error. The intrinsic loss of the rib waveguide was < 0.3 dB/cm, which is low loss considering the waveguide dimensions. Transmission loss values always refer to the average across the C-band.

Fig. 2 Intrinsic loss measurements using waveguides of 2 lengths. The measurement error determines an upper limit for the loss: 0.3 dB /cm

We also measured the curvature loss of the waveguides.

Fig. 3 depicts transmission loss data of 70 waveguides, with a variation of bend radius ranging from R > 5000 µm to R = 400 µm. The graph shows the set-on of noticeable polarization dependence around R = 800 µm. The waveguide do therefore not allow for dense integration comparable to photonic nanowires. Fig. 3 shows what is also visible when plotting data from all over the 8” wafer (these data are not presented here). The transmission data show a remarkable uniformity, which we attribute to excellent process control in terms of etch depth, lithographic definitions and roughness. Defective waveguides are very rare.

Fig. 3 Transmission loss data of 70 waveguides, with a variation of bend radius ranging from R > 5000 µm (S-bend) to R = 400 µm. Waveguides of R = 200 µm were not measured.

Simple multi-mode interference coupler structures were

designed and realized using 1.4 µm Silicon rib waveguide technology. To test the 2×2 coupler properties, Mach-Zehnder-interferometer (MZI) structures were included in the test design, featuring a free spectral range (FSR) of 40 GHz at 1550 nm. An MZI filter curve across the C-band is depicted in Fig. 4.

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Fig. 4 Transmission filter curve of 40 GHz MZI structures. Excess loss increases toward the transition to the L-band

The filter curve exhibits almost uniform insertion loss

across the C-band, only toward the edge of the L-band extra excess loss becomes noticeable. Excess loss compared to simple waveguides amounts to ~ 3 dB, i.e. ~1.5 dB per coupler, which is comparable to results achieved in 4 µm SOI rib waveguide technology [7]. The extinction ratio of the MZI continuously exceeds 20 dB. However, a certain degree of fluctuation is also visible.

The phase offset at the coupler outputs can be deduced from the shift between the respective filter curves. Fig. 5 depicts the filter curves measured at the II-port and at the X-port. The curves demonstrate the expected phase offset for a 2×2 device. Also the imbalance between the 2 output ports remains small (< 0.5 dB).

Fig. 5 Resolved filter curves at the II- and at the X-ports of the MZI. The designed FSR of 40 GHz (320 pm at 1.55 µm) is well matched. The coupler exhibits the correct phase offset between the outputs.

IV. CONCLUSIONS

Front-end integration of photonic functionality in an existing 0.25 µm BiCMOS technology requires the bulk-electronics to be adapted to SOI substrates. We have presented experimental data proving that the use of 1.4 µm SOI does not have a detrimental effect on static or dynamic performance of nMOS, pMOS, and HBTs in 0.25 µm SiGe BiCMOS. We have also shown that low-loss rib waveguide structures can be realized using the shallow-trench etch. The next step will be the modular integration of waveguide structures in the standard BiCMOS process flow. Keeping in mind the mentioned high-speed capabilities of HBTs, integration in BiCMOS offers an attractive alternative to integration in CMOS.

ACKNOWLEDGMENTS We gratefully acknowledge the support by the European

Network of Excellence ePIXnet.

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