H I R A M O T O - KO B AYA S H I L A B .[Si l icon-Based Integrated Nano-Devices]

Department of Informatics and Electronics

Integrated Device Engineer ing

http://v ls i . i i s .u-tokyo.ac. jp/Department of E lectr ica l Engineer ing and Informat ion

Si l icon Nanotechnology Aiming at Large Scale Integrat ion Ee-206

Towards VLSIs integrating everythingVery large scale integration (VLSI) is the basis of contemporary advanced IT society.

Hiramoto/Kobayashi Lab. aims at solving worldwide problems by the technologicalinnovation of future integrated nanoelectronics from the device side. Prof. M. Kobayashi,formerly a researcher in IBM Watson Research, joined the lab in 2014. Based on thevision in Fig. A, we are pursuing the extreme form of integrated nanodevices.

Fig. A. A vision map of the integrated nanoelectronics, drawn by Prof. Hiramoto in Semiconductor Technology RoadmapCommittee of Japan (STRJ). A new field of “Extended CMOS” will be created by integrating “Beyond CMOS” and “More ThanMoore” into CMOS base technology. This map is found in International Technology Roadmap for Semiconductor (ITRS).

Fig. 1. Silicon nano-wire transistors were fabricated and the quantum effects were evaluated.

Fig. 3. CMOS-compatible ferroelectric nano film is anenabler for ultralow power logic and memorytechnology.

Fig. 6. Single electron transistor,one of Beyond CMOS devices,operating at room temperature isintegrated into CMOS, which canbe applied to quantum bits forquantum computers.

Fig. 2. The silicon power deviceproject was started. The currentdensity of IGBT was improved by thescaling concept keeping high blockingvoltage of 3000V.

Fig. 4. Nonvolatile memories will realize smartpower management and hardware AI.

Fig. 5. Negative capacitancetransistor can break the physical limitand achieve sub-60mV/dec steepsubthreshold slope.

year

Beyond CMOS

Elements

ERD-WG in Japan

Existing technologies

New technologies

Evolution of Extended CMOS

Gate

S D

BOX

nanowires

Gate1

Gate2

Gate3

Gate4

Lead1

Lead2

Lead3

Lead4

Source

Drain

Poly-Si gate

Point contactchannel

-3 -2 -1 0 1 2 3-30

-20

-10

0

10

20

30

Polar

izatio

n (µ

C /cm

2 )

Voltage (V)

V=1.0V V=1.5V V=2.0V V=2.5V V=3.0V

PWR

BL

WLWL

PL PL

GND BL

FE-HfO2 cap.

WLPWR

GNDPL

N1 N2

BL BL

50nm

TiNHZO

TiN 9nm

Metal 1

Ferroelectric Thin film

Metal 2

2.6x at Vov=0.5V

60mV/dec

60mV/dec

SSmin=21mV/dec

Vg sweep

MFMIS-FET MISFET

Vg (V) Vg (V)

Vd=1V Vd=1V

10x at Vg=0.4V

2.6x at Vg=0.5V

Ferroelectric HfO2 gate insulator

Vg

Ψs

CFE

CS

Vox

Spontaneous polarization

4nm HfZrO2

Si-sub.

HfZrO2

100nm Si-sub.