Silicon Lab’s Si5348 Network Synchronizer with Marvell’s ... · Marvell PHY (88X5123) and a SiLabs Si5348 Network Synchronizer meets the requirements of G.8262 (Jan 2015) using

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Silicon Lab’s Si5348 Network Synchronizer with Marvell’s 100G 88X5123 PHY tested using the Calnex Paragon-100G

ITU-T G.8262 Compliance Report Document Revision 1.0, March 2018

ITU’s standard ITU-T G.8262 [Timing characteristics of a synchronous Ethernet equipment slave clock] defines the performance of PLLs to be used in two different types of Ethernet Equipment Clocks (EECs): EEC Option 1, which is based on a 2048 kbps rate and is used in Europe and Asia, and EEC Option 2, which is based on a 1544 kbps and is used in North America. Silicon Labs’ Si534x family of jitter attenuator clock synthesizers are SyncE compliant and as such represent an ideal solution for the implementation of SyncE NEs. They can accept TDM or Ethernet recovered clock frequencies and generate Ethernet clock frequencies that easily meet the jitter performance of 10/40 Gigabit Ethernet PHYs with significant margin. This document presents the results of testing criteria performed on Si5348 devices, and it shows that they are fully compliant with the SyncE timing characteristics defined by the G.8262 standard, hence qualifying them as EECs. This compliance report demonstrates that the synchronization path within a network element consisting of a 100G Marvell PHY (88X5123) and a SiLabs Si5348 Network Synchronizer meets the requirements of G.8262 (Jan 2015) using a Calnex Paragon-100G where noted. G.8262 compliance tests may have contributions from both the PHY and the PLL vs just the PLL or OCXO and have been noted in Table 1. Note that the PLL+PHY testing was done with the Si5348 Rev E device and the PLL only testing was done previously with the Si5348 Rev D device.

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Contents

Contents ....................................................................................................................................................................... 2

Introduction .................................................................................................................................................................. 4

ITU-T G.8262 standards matrix – compliance results summary .............................................................................. 4

Equipment & hardware used in testing (Si5348 + 100G PHY) .................................................................................. 6

Si5348 frequency plan used in testing (Si5348 + 100G PHY) ................................................................................... 7

Equipment & hardware used in testing (Si5348 only) ............................................................................................... 7

Si5348 frequency plan used in testing (Si5348 only) ................................................................................................ 8

Considerations on the use of TCXOs and OCXOs as reference clocks .................................................................. 8

Timing characteristics ................................................................................................................................................. 9

Free-run accuracy ....................................................................................................................................................................... 9 Description................................................................................................................................................................................. 9 Test set-up diagram ................................................................................................................................................................... 9 Test methodology....................................................................................................................................................................... 9 Input, output and filtering parameters ......................................................................................................................................... 9 Clock Builder Pro frequency plan files ........................................................................................................................................ 9 EEC Option 1 results: Passed .............................................................................................................................................. 10 EEC Option 2 results: Passed ............................................................................................................................................... 11

Pull-in / Hold-in .......................................................................................................................................................................... 12 Description............................................................................................................................................................................... 12 Test set-up diagram ................................................................................................................................................................. 12 Test methodology..................................................................................................................................................................... 12 Input, output and filtering parameters ....................................................................................................................................... 12 Clock Builder Pro frequency plan files ...................................................................................................................................... 13 EEC Option 1 results: Passed .............................................................................................................................................. 13 EEC Option 2 results: Passed .............................................................................................................................................. 14

Wander generation .................................................................................................................................................................... 15 Description............................................................................................................................................................................... 15 Test set-up diagram ................................................................................................................................................................. 16 Test methodology..................................................................................................................................................................... 16 Input, output and filtering parameters ....................................................................................................................................... 16 Clock Builder Pro frequency plan files ...................................................................................................................................... 17 EEC Option 1 results: Passed .............................................................................................................................................. 17 EEC Option 2 results: Passed .............................................................................................................................................. 18

Jitter generation ........................................................................................................................................................................ 18 Description............................................................................................................................................................................... 18 Test set-up diagram ................................................................................................................................................................. 19 Test methodology..................................................................................................................................................................... 20 EEC Option 1 results: Passed .............................................................................................................................................. 20 EEC Option 2 results: Passed .............................................................................................................................................. 21

Wander tolerance....................................................................................................................................................................... 22 Description............................................................................................................................................................................... 22 Test set-up diagram ................................................................................................................................................................. 22 Test methodology..................................................................................................................................................................... 22 Input, output and filtering parameters ....................................................................................................................................... 23 Clock Builder Pro frequency plan files ...................................................................................................................................... 23 EEC Option 1 results: Passed .............................................................................................................................................. 23 EEC Option 2 results: Passed .............................................................................................................................................. 26

Jitter tolerance ........................................................................................................................................................................... 28 Description............................................................................................................................................................................... 28 Test set-up diagram ................................................................................................................................................................. 28 Test methodology..................................................................................................................................................................... 29

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EEC Option 1 results: Passed .............................................................................................................................................. 29 EEC Option 2 results: Passed .............................................................................................................................................. 29

Wander transfer ......................................................................................................................................................................... 30 Description............................................................................................................................................................................... 30 Test set-up diagram ................................................................................................................................................................. 30 Test methodology..................................................................................................................................................................... 30 Input, output and filtering parameters ....................................................................................................................................... 30 Clock Builder Pro frequency plan files ...................................................................................................................................... 31 EEC Option 1 results: Passed .............................................................................................................................................. 31 EEC Option 2 results: Passed .............................................................................................................................................. 32

Short term phase transient ....................................................................................................................................................... 34 Description............................................................................................................................................................................... 34 Test set-up diagram ................................................................................................................................................................. 34 Test methodology..................................................................................................................................................................... 35 EEC Option 1 results: Passed .............................................................................................................................................. 35 EEC Option 2 results: Passed .............................................................................................................................................. 36

Holdover ..................................................................................................................................................................................... 37 Description............................................................................................................................................................................... 37 Test set-up diagram ................................................................................................................................................................. 38 Test methodology..................................................................................................................................................................... 38 EEC Options1&2 results: Passed ........................................................................................................................................ 39

Phase transient with signal interruptions ................................................................................................................................ 39 Description............................................................................................................................................................................... 39 Test Set-up Diagram ................................................................................................................................................................ 40 Test methodology..................................................................................................................................................................... 40 Input, output and filtering parameters ....................................................................................................................................... 40 Clock Builder Pro frequency plan files ...................................................................................................................................... 41 EEC Option 1 results: Passed .............................................................................................................................................. 42 EEC Option 2 results: not tested since there is no standard defined for EEC Option 2. ............................................................ 42

Phase Discontinuity .................................................................................................................................................................. 43 Description............................................................................................................................................................................... 43 Test set-up diagram ................................................................................................................................................................. 43 Test methodology..................................................................................................................................................................... 44 Input, output and filtering parameters ....................................................................................................................................... 44 Clock Builder Pro frequency plan files ...................................................................................................................................... 44 EEC Option 1 results: Passed .............................................................................................................................................. 45 EEC Option 2 results: Passed .............................................................................................................................................. 46

Conclusions................................................................................................................................................................ 46

References .................................................................................................................................................................. 46

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Introduction

The ITU standards specify the synchronization requirements at the input and output of the network element itself, as shown in Figure 1. In other words, it considers the network element as a black box. The PLL is the main contributor to the performance of synchronization path, but since the PHY provides the interface to the external network it is also an important part of the total synchronization solution. In this system the PLL is the Silicon Labs Si5348 Network Synchronizer and the PHY is the Marvell 4 x 25G/ lane 100G 88X5123 PHY.

Figure 1: Components of a Network Element Synchronization Chain

ITU-T G.8262 standards matrix – compliance results summary

The following table summarizes the timing characteristics tested, along with the corresponding references to each of

the EEC Options and the results of each test. All tests performed in this report passed the G.8262 specification. The

table specifies the device dependence. For the purposes of this report, only the testing dependent on the Si5348,

OCXO and PHY were done with the Calnex Paragon-100G.

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Table 1: G.8262 Test Plan Summary

Timing Characteristic EEC Performance

Dependence Standard Section Compliance Result

Frequency Accuracy: Measures free running accuracy of the PLL output

Frequency Accuracy Option 1

Option 2

OCXO

OCXO

G.8262 - 6.1

G.8262 - 6.2

Passed

Passed

Pull-in, Hold-in, Pull-Out: Measures pull-in , hold-in, pull-out range of the PLL

Pull-in / Hold-in/Pull

out

Option 1

Option 2

Si5348 Only

Si5348 Only

G.8262 - 7.1.1

G.8262 - 7.1.2

Passed

Passed

Noise Generation: Measures wander and jitter generation at the output of the PHY when locked to an ideal

input

Wander Generation Option 1

Option 2

Si5348/OCXO

Si5348/OCXO

G.8262 - 8.1.1

G.8262 - 8.1.2

Passed

Passed

Jitter Generation Option 1

Option 2

Si5348 + PHY

Si5348 + PHY

G.8262 - 8.3.1

G.8262 - 8.3.1

Passed

Passed

Noise Tolerance: Measures the level of wander and jitter applied at the input before triggering the following

events: Alarms (Loss of lock, loss of signal, out of frequency), Input switchovers, entry into holdover

Wander Tolerance Option 1

Option 2

Si5348 Only

Si5348 Only

G.8262 - 9.1.1

G.8262 - 9.1.2 Passed

Jitter Tolerance Options 1 & 2 Si5348 + PHY G.8262 - 9.2.1 Passed

Noise Transfer: Measures how much input wander gets transferred to the output. This depends on the PLL

loop bandwidth because the PHY does not filter wander (BW >10Hz)

Wander Transfer -

Peaking

Option 1

Option 2

Si5348 Only

Si5348 Only

G.8262 - 10.1

G.8262 - 10.2

Not Applicable

Passed

Wander Transfer Option 1

Option 2

Si5348 Only

Si5348 Only

G.8262 - 10.1

G.8262 - 10.2 Passed

Transient Response and Holdover Performance: Measures phase transients due to automatic clock input

switching, internal equipment re-arrangements, entry and exit into holdover

Short Term Phase

Transient

Option 1

Option 2

Si5348 + PHY

Si5348 + PHY

G.8262 - 11.1.1

G.8262 - 11.1.2

Passed

Passed

Holdover Options 1 & 2 Si5348 + PHY G.8262 - 11.2.1 Passed

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Phase Transient with

Signal Interruptions

Option 1

Option 2

Si5348 Only

Si5348 Only

G.8262 - 11.3.1

G.8262 - 11.3.2

Passed

Not Applicable

Phase Discontinuity Option 1

Option 2

Si5348 Only

Si5348 Only

G.8262 - 11.4.1

G.8262 - 11.4.2

Passed

Passed

Equipment & hardware used in PLL + 100G PHY Tests (Si5348 + 88X5123)

The following table includes all equipment and special hardware used for compliance tests Si5348 and 88X5123.

Table 2: Equipment List (Si5348 + 100G PHY Testing)

Manufacturer Model Number Description Additional Notes

Calnex 100G 100GE G.8262 test system Info available here:

Calnex Paragon-100G

Stanford Research

Systems CG635

Synthesized Clock

Generator

Option 3 (Rubidium time

base) installed

Agilent / Keysight 53131A Universal Frequency

Counter

External time base

connected to rubidium

reference

Used for signal

monitoring purposes in

most tests

Agilent / Keysight DSOX3034A Digital Storage Oscilloscope Used only for signal

monitoring purposes

Silicon Labs Si5348-EB Rev. 2.1 Si5348 Rev. E Evaluation

Boards

Available at

www.silabs.com

Marvell 100G 88X5123 25Gx4 100G PHY

Evaluation board

Board was used with

Fiber cables to connect

to the Calnex Paragon-

100G

Rakon STP3158-LF OCXO Used as reference for

Si5348 EVB

https://calnexsol.com/en/docman/brochures/115-paragon-100g-brochure-1/file

http://www.silabs.com/

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Configuration for PLL + 100G PHY Compliance Tests (Si5348 + 88X5123)

The Si5348 was configured in the following way for both Option 1 and Option 2 using ClockBuilder Pro software

v2.21:

Crystal input: 48MHz

Reference input frequency: 12.8 MHz OCXO

IN0 DSPLL A,C,D 10.07080078125MHz

IN1 DSPLL A,C,D 10.07080078125MHz

Input reference clock select mode: automatic

Highest priority IN0, lowest IN1

Automatic clock selection using auto revert

Outputs:

o OUT0: DSPLLA 156.25MHz

o OUT1: DSPLLA 156.25MHz

Loop bandwidth: Option 1 (10Hz) Option 2 (100mHz)

Fastlock enabled: 100Hz

Enable hitless switching

Enable fine hitless switching

Preserve holdover history

LOLA set threshold 10ppm/ clear threshold 1ppm

Equipment & hardware used in PLL-Only Tests (Si5348)

Table 3 lists all equipment and hardware that was used for the Si5348-only compliance tests.

Table 3: Equipment List (Si5348-only)

Manufacturer Model Number Description Additional Notes

Stanford Research

Systems CG635

Synthesized Clock

Generator

Option 3 (Rubidium time

base) installed*

IXIA / Anue Systems 3500 Network Synchronization

Test Solution

SW version 2.0.2

External time base


reference

Keithley 2230-30-1 Triple Channel DC Power

Supply

Used to power OCXO

and Silicon Labs Apollo

board

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Agilent / Keysight 53131A Universal Frequency

Counter

External time base


reference

Used for signal

monitoring purposes in

most tests

Agilent / Keysight 33250A Arbitrary Waveform

Generator

External time base


reference

Agilent / Keysight DSOX3034A Digital Storage Oscilloscope Used only for signal

monitoring purposes

Silicon Labs Si5348-EB Rev. 2.1 Si5348 Rev. D Evaluation

Board

Available at

www.silabs.com

Silicon Labs Apollo

Multi-purpose board with

high speed CML muxing and

clock gapper circuitries

Not available

commercially**

* A 10 MHz Rubidium time base was selected in-lieu of a GPS reference because some of the tests performed during

this compliance testing were very long (some runtimes exceeded 36 hours) and a GPS signal can have corrections

that could impact the results of such long tests.

** The SiLabs Apollo board is an internally developed engineering tool and is not available commercially. However,

some of the functions that it implements can be easily and similarly achieved with commercially available components

(i.e. high speed logic multiplexers) or with commercially available instrumentation (Bit Error Rate Testers [BERTs] or

Programmable Pattern Generators [PPGs], which can be used to provide signal interruptions or clock gaps).

Si5348 frequency plan used in testing (Si5348 only) Considerations on the use of TCXOs and OCXOs as reference clocks

Temperature compensated crystal oscillators (TCXOs) and oven compensated crystal oscillators (OCXOs) provide the

required stability necessary to meet requirements such as wander generation and holdover when the input reference

clock is unavailable.

The Si5348 family of devices will achieve industry leading low phase noise performance and superior temperature

stability when the external reference has been properly selected for parameters such as frequency, Q factor, proper

termination, etc.

Silicon Labs’ application note AN905 “Si534x External references; optimizing performance” provides a set of detailed

guidelines that should be followed in order to get the best performance from the Si5348.

Such guidelines were followed when performing the testing described herein. It is important to note that a 40 MHz

Rakon RTX Series 513872 TCXO was used as an external reference for all testing described herein.

http://www.silabs.com/

http://www.silabs.com/documents/public/application-notes/AN905.pdf

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Timing characteristics

Free-run accuracy (PLL Only)

Description

Per the standard:

EEC Option 1: “under free-running conditions, the EEC output frequency accuracy should not be greater than 4.6

ppm with regard to a reference traceable to a clock”.

EEC Option 2: “under prolonged holdover conditions, the output frequency accuracy of the different types of node

clocks should not exceed 4.6 ppm with regard to a reference traceable to a primary reference clock”.

Test set-up diagram

Figure 2: Test set-up used for free-run measurements

Test methodology

A frequency plan with the input and output characteristics described in the following section was programmed into the

device through ClockBuilder Pro (CBPro). The reference clock (REF) was provided by an airflow-shielded OCXO. No

input clock was provided to the device, hence forcing it to remain in free-run mode. Then the output frequency was

measured with the frequency counter (using a resolution of 1 Hz) every 4 seconds over 3.5 hours and the ppm offset

relative to the reference clock was plotted.

Input, output and filtering parameters

References:

XA/XB: 48 MHz crystal

REF: 12.8 MHz OCXO

Input Frequency @ IN0: no signal to allow device to free-run

Output Frequency @ OUT0/0B: 40 MHz

Bandwidth:

EEC Option 1: nominal bandwidth = 4 Hz; fast-lock bandwidth = 100 Hz

EEC Option 2: nominal bandwidth = 0.1 Hz; fast-lock bandwidth = 10 Hz

Clock Builder Pro frequency plan files

Si5348-Frequency_Accuracy_Option1.slabtimeproj

Si534x-EB Rev 2.1

IN0 REF

IN1 . .

OUT0 OUT0B

IN2

53131A Counter

PC

40MHz

10MHz

Q Q* CMOS REFOUT

[BACK]

USB SR CG635

CH1 CH2

10MHz

Supply OCXO

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Si5348-Frequency_Accuracy_Option2.slabtimeproj

EEC Option 1 results: Passed

As it can be seen from the plot shown below, the output frequency remained within +/- 4.6 ppm with respect to the

Rubidium reference for the entire duration of the test while the device was in free-run mode. The blue trace shows the

measured results, which remained constant at 0.025 ppm. It is important to note that the overall offset corresponds to

the offset of the OCXO relative to the Rubidium reference.

Figure 3: EEC Option 1 free-run accuracy test result

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As it can be seen from the plot shown below, the output frequency remained within +/- 4.6 ppm with respect to the

Rubidium reference for the entire duration of the test while the device was in free-run mode. The blue trace shows the

measured results, which remained constant at 0.025 ppm. It is important to note that the overall offset corresponds to

the offset of the OCXO relative to the Rubidium reference.

Figure 4: EEC Option 2 free-run accuracy test result

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Pull-in / Hold-in

Description

Per the standard, for both EEC Options: “the minimum pull-in range should be +/- 4.6 ppm, whatever the internal

oscillator frequency offset may be”.

Test set-up diagram

Figure 5: Test set-up used for pull-in measurements

Test methodology

The frequency plan in the following section was and was generated using CBPro v2.21. The reference clock (REF) was

generated with the clock generator (traceable to the Rubidium time base) whereas the input clock was generated with

the AWG (also traceable to the Rubidium time base) and this clock was multiplexed using SiLabs Apollo board. The

output of the mux was connected to the device’s input (IN1) and also to the oscilloscope for observation purposes. The

device’s output (OUT0/0B) was monitored with the frequency counter.

Through automation performed with Visual Studio and GPIB instrument control a loop was implemented where first the

reference clock was set to a +4.6 ppm offset and the input clock set to a -4.6 ppm offset from the ideal 40 MHz reference,

respectively. Initially the input clock was disabled (through the mux) so that the part would be free-running. The

frequency counter was triggered to start measuring and 2-3 seconds later the input clock was enabled (through the

mux), taking the device out of free-run state and pulling-in the frequency offset until lock was achieved. The procedure

was repeated with the opposite offsets (-4.6 and 4.6 ppm respectively for the reference and input clocks). The resulting

output frequency measurements were plotted.


References:


REF: 12.8 MHz, traceable to Rubidium reference

Input Frequency @ IN1: 40 MHz

Si534x-EB Rev 2.1

IN0 REF

IN1 . .

OUT0 OUT0B

IN2

53131A Counter

PC

40MHz

10MHz

Q Q* CMOS REFOUT

[BACK]

USB SR CG635

CH1 CH2

10MHz

33250A AWG

OUT

10MHz

40MHz +/- 4.6ppm

12.8MHz +/- 4.6ppm

Silicon Labs

Gapper Board

Mux IN1

Mux IN2

Mux OUT

CH1 CH2 CH3 CH4

Oscilloscope

BNC Ports: 1 – 10 MHz Reference

2 – Wander Generator

3 – Wander Measurer 1


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Bandwidth:

EEC Option 1: nominal bandwidth = 4 Hz; fast-lock bandwidth disabled



Si5348-PullIn_Option1.slabtimeproj

Si5348-PullIn_Option2.slabtimeproj


The plot below shows the results of the two cases tested (i.e. opposite offsets at the reference and the input of +4.6

and -4.6 ppm or vice versa). The blue traces correspond to the measured frequency offset (Y axis) across readings in

time (X axis). Readings were performed as fast as the frequency counter was capable of measuring with a resolution

of 1 Hz (i.e. roughly 1 reading per second). The grey dotted traces show the status of the HOFRX alarm (X=A or C,

depending on the DSPLL being used for the test), which corresponds to the Holdover/Freerun register. The purple

dotted traces show the status of the LOLX alarm, which serves as the lock indicator. These two variables are plotted

against a secondary Y axis on the right. When HOFRX = 1 the part is in Holdover/Freerun state. It can be seen that as

soon as HOFRX toggles to 0 the device starts the locking process, pulling in the frequencies to achieve a total pull of

9.2 ppm in both cases until the device declares lock (LOLX = 0).

It can be seen that, due to the 4 Hz of nominal bandwidth programmed on the device, a full pull of 9.2 ppm is achieved

in roughly 12 seconds after the device starts pulling in.

Figure 6: EEC Option 1 pull-in / hold-in test result

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The plot below shows the results of the two cases tested (i.e. opposite offsets at the reference and the input of +4.6

and -4.6 ppm or vice versa). The blue traces correspond to the measured frequency offset (Y axis) across readings in

time (X axis). Readings were performed as fast as the frequency counter was capable of measuring with a resolution

of 1 Hz (i.e. roughly 1 reading per second). The grey dotted traces show the status of the HOFRX alarm (X=A or C,

depending on the DSPLL being used for the test), which corresponds to the Holdover/Freerun register. The purple

dotted traces show the status of the LOLX alarm, which serves as the lock indicator. These two variables are plotted

against a secondary Y axis on the right. When HOFRX = 1 the part is in Holdover/Freerun state. It can be seen that as

soon as HOFRX toggles to 0 the device starts the locking process, pulling in the frequencies to achieve a total pull of

9.2 ppm in both cases until the device declares lock (LOLX = 0).

It can be seen that, due to the 0.1 Hz of nominal bandwidth (with a fast lock bandwidth of 1 Hz) programmed on the

device, a full pull of 9.2 ppm is achieved in roughly 33 seconds after the device starts pulling in.

Figure 7: EEC Option 2 pull-in / hold-in test result

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Wander generation

Description

Per the standard: “The noise generation of an EEC represents the amount of phase noise produced at the output when

there is an ideal input reference signal or the clock is in holdover state. A suitable reference, for practical testing

purposes, implies a performance level at least 10 times more stable than the output requirements. The ability of the

clock to limit this noise is described by its frequency stability. The measures maximum time interval error (MTIE) and

time deviation (TDEV) are useful for the characterization of noise generation performance”.

EEC Option 1:

MTIE: “When the EEC is in the locked mode of operation synchronized to a wander-free reference, the MTIE

measured using the synchronized clock configuration defined in Figure 1a of ITU-T G.810 should have the

limits shown on the table below, if the temperature is constant (within ±1 °K)”.

MTIE limit [ns] Observation interval [s]

40 0.1 < ≤ 1

40 0.1 1 < ≤ 100

25.25 0.2 100 < ≤ 1000

TDEV: “When the EEC is in the locked mode of operation, the TDEV measured using the synchronized clock

configuration defined in Figure 1a of ITU-T G.810 should have the limits shown on the table below, if the

temperature is constant (within ±1 °K)”.

TDEV limit [ns] Observation interval [s]

3.2 0.1 < ≤ 25

0.64 0.5 25 < ≤ 100

6.4 100 < ≤ 1000

EEC Option 2:

MTIE: “When the EEC is in the locked mode of operation synchronized to a wander-free reference, the MTIE

measured using the synchronized clock configuration defined in Figure 1a of ITU-T G.810 should have the

limits shown on the table below, if the temperature is constant (within ±1 °K)”.


20 0.1 < ≤ 1

20 0.48 1 < ≤ 10

60 10 < ≤ 1000

TDEV: “When the EEC is in the locked mode of operation, the TDEV measured using the synchronized clock

configuration defined in Figure 1a of ITU-T G.810 should have the limits shown on the table below, if the

temperature is constant (within ±1 °K)”.


3.2 -0.5 0.1 < ≤ 25

https://www.itu.int/rec/T-REC-G.810/en




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2 2.5 < ≤ 40

0.32 0.5 40 < ≤ 1000

10 1000 < ≤ 10000

Test set-up diagram

Figure 8: Test set-up used for wander generation / tolerance / transfer and holdover measurements

Test methodology


provided by an airflow-shielded OCXO. A 25 MHz input was generated with the Anue 3500 (at IN0) and the device’s

output (at OUT0/0B) was also monitored with the Anue, which was used to perform MTIE and TDEV measurements

during the recommended observation intervals and compare the results to the masks also defined by the standards.


References:


REF: 12.8 MHz OCXO



Bandwidth:



OCXO

Si534x-EB Rev 2.1

IN0

ANUE 3500

25MHz

REF

2 4

1 3 S

S

BNC Connect

IN1 . .

OUT0 OUT0B

IN2

53131A Counter

Management

PC

100 MHz/4 = 25MHz

25MHz

10MHz

Q Q* CMOS REFOUT

[BACK]

USB

Supply

SR CG635

CH1 CH2

10MHz





17


Si5348_WanderGeneration_Options1_2.slabtimeproj


As it can be seen on the plot shown below, the measured MTIE (solid green line) and TDEV (solid blue line) results

were below the MTIE and TDEV masks (dashed green and blue lines, respectively) defined by the standards.

Figure 9: EEC Option 1 wander generation test result

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As it can be seen on the plot shown below, the measured MTIE (solid green line) and TDEV (solid blue line) results

were below the MTIE and TDEV masks (dashed green and blue lines, respectively) defined by the standards.

Figure 10: EEC Option 2 wander generation test result

Jitter generation

This test was done with the Si5348 and the 100G PHY.

Description

Per the standard: “In the absence of input jitter at the synchronization interface, the intrinsic jitter at the synchronous

Ethernet output interfaces, as measured over a 60-second interval, should not exceed the limits given” (below).

EEC Option 1 and 2:

Interface Measuring filter Peak to peak amplitude (UI)

25G

(Note 1,4,5,6)

20kHz to 200MHz 1.2

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NOTE 1 – There is no specific high-band jitter requirement for synchronous Ethernet. The relevant IEEE 802.3 jitter

requirements shall be met in addition to the specific synchronous Ethernet wideband jitter requirements specified in

this table. [IEEE 802.3] defines measurement methodologies. The applicability for those measurement methodologies

in a synchronization network environment is for further study.

NOTE 4 – 25G includes multi-lane interfaces consisting of 25G lanes including 100GBASE-LR4/ER4

NOTE 5 1G: (1000BASE-KX, -SX, -LX) 1 UI = 0.8 ns 10G (10GBASE-SR/LR/ER, -LRM, 40GBASE-

KR4/CR4/SR4/LR4, 100GBASE-CR10/SR10): 1 UI = 96.97 ps 10G (10GBASE-SW/LW/EW): 1 UI = 100.47 ps 25G

(100GBASE-LR4/ER4): 1 UI = 38.79 ps

NOTE 6 – The peak-to-peak jitter amplitude for 25G lanes is increased from 0.5 UI to 1.2 UI, i.e., by a factor of 2.4. To

compensate for this increase, the high-pass corner frequency used for 10G should first be increased by a factor of

2.5 to take account of the increase in line rate from 10G, and then decreased by a factor of 2.4 to take account of the

increase in amplitude. This gives a high-pass corner frequency of 20.833 kHz, which has been rounded down to 20

kHz for convenience; this rounding to a lower value is slightly stricter.

Test set-up diagram

Calnex Paragon-100G

Si5348 SyncE PLL

100G PHY Tx

PLL

Marvell EVB

100G PHY Rx

CDRClk Clk

Recovered clock Filtered clock

Measure Jitter

10MHz

100GbE

(25Gx4)

10.0708 MHz

156.25 MHz

Rubidium Time

Base

OCXO

100GbE (25Gx4)

Figure 11: Jitter generation test set-up

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Test methodology

In the absence of input jitter at the synchronization interface from the Calnex Paragon-100G the intrinsic jitter at the

synchronous Ethernet output interface is measured over a 60 second interval and should not exceed the standards.

A low jitter 10.3125 MHz signal is generated from the Calnex Paragon-100G to the 100G PHY. The PHY sends

10.07080078125MHz to the Si5348 which then sends out 156.25MHz back to the PHY. The PHY transmits

156.25MHz and the signal is measured on the Calnex Paragon-100G. The maximum allowable peak-to-peak jitter

amplitude for 25G lanes is 1.2UI. This is the maximum budget for the combined jitter generated by both the PHY and

the PLL.


The results for option 1 show 1.12 UI pk-pk meeting the mask at 1.2UI pk-pk

Figure 12: 100G jitter generation EEC1

21


The results for Option 2 show 1.1 UI pk-pk meeting the mask of 1.2UI pk-pk.

Figure 13:100G jitter generation EEC2

22

Wander tolerance

Description

Per the standard:

“The noise tolerance of an EEC indicates the minimum phase noise level at the input of the clock that should be

accommodated whilst:

- maintaining the clock within prescribed performance limits. The exact performance limits are for further study;

- not causing any alarms;

- not causing the clock to switch reference;

- not causing the clock to go into holdover.”

Test set-up diagram

Please refer to the diagram shown on Figure 8.

Test methodology


device through CBPro. The reference clock (REF) was provided by an airflow-shielded OCXO. Different stimulus

signals (as described below) were generated and applied with the Anue 3500 at the device’s input (at IN0). Using

CBPro’s Evaluation Board (EVB) GUI the device’s main alarms were monitored prior, during and after the stimulus to

verify the device’s wander tolerance capability.

Per the standard “The TDEV signal used for a conformance test should be generated by adding white, Gaussian noise

sources, of which each has been filtered to obtain the proper type of noise process with the proper amplitude”. As

illustrated on the next two images, the generated stimuli (shown in the dark blue line) follow closely the standard

recommendation (dashed blue line).

Figure 14: EEC Option 1 wander tolerance stimulus TDEV

23

Figure 15: EEC Option 2 wander tolerance stimulus TDEV


References:


REF: 12.8 MHz OCXO



Bandwidth:




Si5348_WanderTolerance_Options1_2.slabtimeproj


The images below show an overlay of the CBPro EVB GUI illustrating the status of the device’s alarms at the beginning

and end of the test (note that the “Sticky” alarms are the most important here since they show that alarms were never

set during the duration of the test). The side-inserts also illustrate the concurrent start and end of the stimulus application

from the Anue “TIE playback” feature. Timestamps of the alarm monitoring readings can also be corroborated on the

images (at the bottom).

Note that:

a) These tests had a long duration and as such some of the timestamps can roll into the next day.

b) When an alarm is “clear” the corresponding alarm indicator should have a “white” status. When an alarm is

“set” the corresponding alarm indicator should have a “red” status.

c) Registers and alarms not relevant to the test were greyed out on the images to avoid confusion.

24

Figure 16: EEC Option 1 wander tolerance - device alarms prior to test

25

Figure 17: EEC Option 1 wander tolerance - device alarms after test

26


Figure 18: EEC Option 2 wander tolerance - device alarms prior to test

27

Figure 19: EEC Option 2 wander tolerance - device alarms after test

28

Jitter tolerance

Description

Per the standard:

EEC Options 1 & 2:

25G: “The lower limit of maximum tolerable input jitter for 25G Ethernet interfaces for EEC-Option 1 and

EEC-Option 2 is given by the table below”.

Peak-peak jitter amplitude (UI) Frequency f (Hz)

6445 10 < f ≤ 11.17

72000 f-1 11.17 < f ≤ 20 k

3.6 20 k < f ≤ 100 k

NOTE – 25G includes multi-lane interfaces consisting of 25G lanes including 100GBASE-LR4/ER4.

Test set-up diagram

Calnex Paragon-100G

Si5348 SyncE PLL

100G PHY Tx

PLL

Marvell EVB

100G PHY Rx

CDRClk Clk

Packets with superimposed

jitter

Recovered clock Filtered clock

Detection of dropped packets

Monitor Alarms

Monitor Alarms

Rubidium Time

Base

10MHz

10.0708 MHz

156.25 MHz

100GbE

(25G x 4)

OCXO

100 GbE

(25G x4)

Figure 20: Jitter tolerance test set-up

29

Test methodology

This test ensures that the system can tolerate the jitter amplitudes and dwell times prescribed by the standards

without triggering alarms at the PHY, at the PLL, or loss of packets collected by the Calnex Paragon-100G. An

otherwise clean signal is generated from the Calnex Paragon-100G with specified jitter amplitudes and dwell times

superimposed on the signal. The PHY is monitored for alarms. The Si5348 is monitored for LOS, LOL and OOF and

the Calnex Paragon-100G is tracking packet loss.


Figure 21:100G jitter tolerance EEC1


Figure 22:100G jitter tolerance EEC2

30

Wander transfer

Description

Per the standard: “The transfer characteristic of the EEC determines its properties with regard to the transfer of

excursions of the input phase relative to the carrier phase. The EEC can be viewed as a low-pass filter for the

differences between the actual input phase and the ideal input phase of the reference. The minimum and maximum

allowed bandwidths for this low-pass filter behavior are based on the considerations described in Appendix II of ITU-T

G.813 and are also indicated below.

In the passband, the phase gain of the EEC should be smaller than 0.2 dB (2.3%). The above applies to a linear EEC

model. However, this model should not restrict implementation”.

EEC Option 1:

“The minimum bandwidth requirement for an EEC is 1 Hz. The maximum bandwidth requirement for an EEC

is 10 Hz”.

EEC Option 2:

“Synchronous Ethernet or SDH NEs, when reference to a synchronous Ethernet or a STM-N timing signal

that meets the input TDEV mask in Figure 8 and Table 10 (of the standard), shall output signals that meet

the output TDEV limits shown on the table below. The resultant requirement is shown in the mask of Figure

11 (of the standard). The purpose of the masks is to ensure that the maximum bandwidth of an EEC is 0.1

Hz”.


10.2 0.1 < ≤ 1.73

5.88 1.73 < ≤ 30

32.26 0.5 30 < ≤ 1000

Test set-up diagram

Please refer to the diagram shown on Figure 8.

Test methodology


device through CBPro. The reference clock (REF) was provided by an airflow-shielded OCXO. Different stimulus

signals were generated and applied with the Anue 3500 at the device’s input (at IN0) and the device’s output (at

OUT0/0B) was also monitored with the Anue, which was used to measure the transfer function characteristics of both

EEC options and also to perform TDEV measurements for EEC Option 2 (since EEC Option 1 does not specify TDEV

requirements) during the recommended observation intervals and compare the results to the mask defined by the

standard.


References:


REF: 12.8 MHz OCXO



Bandwidth:




31



The same CBPro files that were used for wander tolerance apply to this section as well.


The image below shows the transfer function characteristics of the EEC clock. The device’s bandwidth was

programmed at 4 Hz, and as it can be observed, the resulting bandwidth was exactly 4 Hz (@ -3dB), with a maximum

peaking of 0.038 dB, thus also satisfying the peaking limit of 0.2 dB.

Figure 23: EEC Option 1 wander transfer characteristic test result

Note there is no wander transfer TDEV characteristic for Option 1.

-3dB point

32


The image below shows the transfer function characteristics of the EEC clock. The device’s bandwidth was

programmed at 0.1 Hz, and as it can be observed, the resulting bandwidth was 0.06 Hz (@ -3dB), with a maximum

peaking of 0.0347 dB, thus also satisfying the peaking limit of 0.2 dB.

Figure 24: EEC Option 2 wander transfer characteristic test result

-3dB point

33

The image below shows the transfer TDEV characteristics of the EEC clock. As it can be observed, the result (solid

blue line) is below the mask defined by the standard (dashed blue line).

Figure 25: EEC Option 2 wander transfer TDEV test result

34

Short term phase transient

Description

Per the standard: “This requirement reflects the performance of the clock in cases when the (selected) input reference

is lost due to a failure in the reference path and a second reference input signal, traceable to the same reference clock,

is available simultaneously, or shortly after the detection of the failure (e.g. in cases of autonomous restoration). In such

cases the reference is lost for at most 15 seconds. The output phase variation, relative to the input reference before it

was lost, is bounded by the following requirements”.

EEC Option 1:

“The phase error should not exceed t + 5 x 10-8 x S seconds over any period S up to 15 seconds. t

represents two phase jumps that may occur during the transition into and out of the holdover state which

both should not exceed 120 ns with a temporary frequency offset of no more than 7.5 ppm. In cases where

the input synchronization signal is lost for more than 15 seconds, the requirements for long-term phase

transient response (Holdover) should apply”.

EEC Option 2:

“During clock rearrangement operations (e.g. reference switching), the output of the clock should meet the

MTIE requirements shown below”.


Not specified ≤ 0.014

7.6 + 885 0.014 < ≤ 0.5

300 + 300 0.5 < ≤ 2.33

1000 2.33 <

Test set-up diagram

Calnex Paragon 100G

100G PHYTx

PLL

Marvell EVB

100G PHYRx

CDR

Signal Generator

Si5348 SyncE PLL

Input Clocks

X

Fiber Cut

Input Switchover

Rubidium Time

Base

10MHz

10.0708 MHz

156.25 MHz100GbE (25G x 4)

10MHz

10.0708 MHz

OCXO

100GbE

(25G x 4)

Figure 26: Short term phase transient test set-up

35

Test methodology

The phase transient response test is measuring the phase transient seen by the Calnex Paragon-100G after the fiber

going into the CDR of the PHY has been pulled. The 10.0708MHz output clock is quickly squelched by the PHY

when it notices the signal has been cut. The Si5348 quickly detects the LOS (Loos of Signal) from the PHY and does

an automatic hitless switch to the other input from the Stanford research signal generator. The small phase transient

from the Si5348 propagates to the PHY Tx and out to the Calnex Paragon-100G where it is measured.


Figure 27: 100G Phase transient response EEC 1

The short term phase transient when pulling the fiber from the PHY showed a 1 ns phase transient. This test was

repeated several times with similar performance to ensure accuracy of this result.

36


Figure 28: 100G Phase transient unplugged from the PHY cutting the fiber connection

This result showed less than 1ns phase transient when the fiber was pulled for option 2. This test was also repeated

several times to ensure the accuracy of the result.

37

Holdover

Description

Per the standard: “This requirement bounds the maximum excursions in the output timing signal. Additionally, it restricts

the accumulation of the phase movement during input signal impairments or internal disturbances”.

EEC Option 1:

“When the EEC loses all its references, it is said to enter the holdover state. The phase error, T, at the

output of the EEC relative to the input at the moment of loss of reference should not, over any period of S >

15 s, exceed the following limit:

∆𝑇(𝑆) = {(𝑎1 + 𝑎2)𝑆 + 0.5𝑏𝑆2 + 𝑐} [𝑛𝑠]

Where:

o a1 = 50 ns/s

o a2 = 2000 ns/s

o b = 1.16 x 10-4 ns/s2

o c = 120 ns”

EEC Option 2:

“When an EEC clock loses all its references, it enters the holdover state. The phase error, T, at the output

of the slave clock from the moment of loss or reference, should, over any period of S seconds, meet the

following:

|∆𝑇(𝑆)| ≤ {(𝑎1 + 𝑎2)𝑆 + 0.5𝑏𝑆2 + 𝑐} [𝑛𝑠]

The derivative of T(S), the fractional frequency offset, should, over any period of S seconds, meet the

following:

|𝑑(∆𝑇(𝑆))

𝑑𝑆| ≤ {𝑎1 + 𝑎2 + 𝑏𝑆} [

𝑛𝑠

𝑠]

The second derivative of T(S), the fractional frequency drift, should, over any period of S seconds, meet

the following:

|𝑑2(∆𝑇(𝑆))

𝑑𝑆2 | ≤ 𝑑 [𝑛𝑠

𝑠2]

Where:

Applies for S > TBD

a1 [ns/s] 50

a2 [ns/s] 300

b [ns/s2] 4.63 x 10-4

c [ns] 1000

38

d [ns/s2] 4.63 x 10-4

In applying the above requirements for the derivative of T(S) and the second derivative of T(S), the period

S must begin after any transient associated with entre into holdover is over”.

Test set-up diagram

Calnex Paragon 100G

100G PHY Tx

PLL

Marvell EVB

100G PHYRx

CDR

Si5348 SyncE PLL

Input Clock

X

Fiber Cut

Automatic Switch to holdover

OCXO

Rubidium Time

Base

10MHz

10.0708 MHz

156.25 MHz100GbE (25G x 4)

100GbE

(25G x 4)

Figure 29: Holdover test set-up

Test methodology

This test measures both the initial frequency offset and frequency stability while the Si5348 is in holdover mode. In

this test it is important that the Si5348 has had the time to collect a valid holdover history. This test is similar to the

phase transient test except that there is no second input clock to switch to. When the fiber is pulled, the PHY

squelches its recovered clock output. The Si5348 identifies a loss of signal and goes into holdover using the

holdover history data previously collected. With the part in holdover, it will track the OCXO. The stability of the OCXO

in this test is very important.

39

EEC Options1&2 results: Passed

Option 1 and Option 2 results are the same because the holdover performance is not affected by having a different

loop bandwidth.

Figure 30: 100G holdover results EEC1 and EEC2

Phase transient with signal interruptions

Description

Per the standard:

EEC Option 1:

“For short-term interruptions on synchronized input signals that do not cause reference switching, the output

phase variation should not exceed 120 ns, with a maximum frequency offset of 7.5 ppm for a maximum

period of 16 ms”.

EEC Option 2:

“This is for further study”.

40

Test Set-up Diagram

Figure 31: Test set-up used for phase transient with signal interruptions measurements

Test methodology


device through CBPro. The reference clock (REF) was provided by an airflow-shielded OCXO. A 28.5741286 MHz input

was generated with the CG635 signal generator and this clock was gapped1 using SiLabs Apollo board. A control signal

for the gapper at a rate of 3.125 MHz was generated with the AWG. The output of the clock gapper was connected to

the device’s input (IN0) and also to the oscilloscope for observation purposes. The device’s output (at OUT0/0B) was

monitored with the Anue, which was used to perform MTIE measurements during the recommended observation

intervals and compare the results to the masks also defined by the standards.


References:


REF: 12.8 MHz OCXO



Bandwidth:


1 Gapping a clock means introducing a missing period in a graceful manner. For the purposes of this test a 1/8 gapped clock was

used, which means 1 out of every 8 periods of the clock was removed, essentially creating a signal interruption at the input of the device. Due to this, the effective clock rate seen at the input of the device was 28.5741286 MHz * 7/8 = 25 MHz. The control signal generated by the AWG had a frequency of 25 MHz * 1/8 = 3.125 MHz.

Si534x-EB Rev 2.1

IN0

ANUE 3500

25MHz

REF

OCXO

2 4

1 3 S

S

BNC Connect

IN1 . .

OUT0 OUT0B

IN2

53131A Counter

Management

PC

28.5741286MHz

25MHz

10MHz

Q Q* CMOS REFOUT

[BACK]

USB

Supply

SR CG635 CH1 CH2

10MHz

Silicon Labs

Gapper Board

CLK IN

CKLK OUT GAP CMD CLK OUT*

CH1 CH2 CH3 CH4

Oscilloscope

25MHz (Gapped)

33250A AWG

OUT





41


Si5348_PhaseTransient_ShortHO_INTERRUPT_Option1.slabtimeproj

42


As it can be seen on the plot shown below (generated with Stable 32 based on TIE data collected with the Anue 3500),

a phase hit of ~0.9 ns took place when a signal interruption occurred at the input. These results are well below the

Option 1 standards of an initial 120 ns phase hit within 16 ms. Note that in this case the TIE data was collected with a

sampling constant () of 1 ms in order to easily comply with the 16 ms standard limit.

Figure 32: EEC Option 1 phase transient with signal interruptions phase vs. time test result

EEC Option 2 results: not tested since there is no standard defined for EEC Option 2.

Maximum phase hit ~0.9 ns

43

Phase Discontinuity

Description

Per the standard:

EEC Option 1:

“In cases of infrequent internal testing or other internal disturbances (but excluding major hardware failures,

e.g., those that would give rise to clock equipment protection switches) within the synchronous Ethernet

equipment clock, the following conditions should be met:

o The phase variation over any period S (ms) up to 16 ms should not exceed 7.5S ns;

o The phase variation over any period S (ms) from 16 ms up to 2.4 s should not exceed 120 ns;

o For periods greater than 2.4 s, the phase variation for each interval of 2.4 s should not exceed 120

ns with a temporary offset of no more than 7.5 ppm up to a total amount of 1 s”.

EEC Option 2:

“In cases of infrequent internal testing or rearrangement operations within the slave clock, the phase

transient at the output of EEC-Option 2 should meet the MTIE specifications defined on the table below”


Not specified ≤ 0.014

7.6 + 885 0.014 < ≤ 0.5

300 + 300 0.5 < ≤ 2.33

1000 2.33 <

Test set-up diagram

Figure 33: Test set-up used for phase discontinuity measurements

Si534x-EB Rev 2.1

IN0

ANUE 3500

25MHz

REF

OCXO

2 4

1 3 S

S

BNC Connect

IN1 . .

OUT0 OUT0B

IN2

53131A Counter

Management

PC

8kHz 25MHz

10MHz

Q Q* CMOS REFOUT

[BACK]

USB

Supply

SR CG635

CH1 CH2

10MHz

Phase matched cables





44

Test methodology


provided by an airflow-shielded OCXO. An 8 kHz differential input was generated with the CG635 signal generator and

each complimentary leg of the differential pair was connected to the IN0 and IN1 device inputs, respectively, essentially

providing two single-ended 8 kHz input clocks with complete phase discontinuity (180° apart). The device’s output (at

OUT0/0B) was monitored with the Anue, which was used to perform MTIE measurements during the recommended

observation intervals and compare the results to the masks also defined by the standards. During the execution of the

test the device was initially locked to the IN0 clock; then after a few seconds a manual switch was performed to switch

to the IN1 clock (180° apart). After 60 seconds another manual switch was performed to return to the IN0 clock.


References:


REF: 12.8 MHz OCXO

Input Frequency @ IN0 & IN1: 8 kHz


Bandwidth:




Si5348_PhaseDiscontinuity_Options1_2.slabtimeproj

45


As it can be seen on the plot shown below (generated with Stable 32 based on TIE data collected with the Anue 3500),

two output phase hits of ~0.3 and 0.16 ns respectively took place when two manual switches per performed at the

input. These results are well below the Option 1 standards of an initial 120 ns phase hit within 16 ms and 2.4 s. Note

that the observed phase hits were so small and within the noise of the measurement that it could be easy to miss where

the second phase discontinuity happened at the input; however, the test was designed so that second input switch

would take place exactly 60 seconds after the first one (which occurred at Time = 24 seconds).

Figure 34: EEC Option 1 phase discontinuity phase vs. time test result

Second input switch

Maximum phase hit ~ 0.16 ns

First input switch

Maximum phase hit ~ 0.3 ns

46


As it can be seen on the plot shown below, the measured MTIE (solid green line) result was below the MTIE mask

(dashed green line) defined by the standard.

Figure 35: EEC Option 2 phase discontinuity MTIE test result

Conclusions

This compliance report shows that the Silicon Labs Si5348 with the Marvell 25Gx4 100G PHY (88X5123) passes all

G.8262 tests. The Calnex Paragon-100G system made this testing very efficient and convenient to prove the system

performance.

References

1. https://www.itu.int/rec/T-REC-G.8262-201501-I/en

2. https://www.silabs.com/documents/public/miscellaneous/Si5348_ITU-

T_G.812_ComplianceTestResults_Rev1.0.pdf

3. https://calnexsol.com/en/docman/white-papers/72-100g-conformance-test-plan/file

https://www.itu.int/rec/T-REC-G.8262-201501-I/en

https://www.silabs.com/documents/public/miscellaneous/Si5348_ITU-T_G.812_ComplianceTestResults_Rev1.0.pdf

https://www.silabs.com/documents/public/miscellaneous/Si5348_ITU-T_G.812_ComplianceTestResults_Rev1.0.pdf

https://calnexsol.com/en/docman/white-papers/72-100g-conformance-test-plan/file

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