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Ionizing Radiation Effects on Advanced CMOS Technologies
Simone [email protected]
htt // t d i i d ithttp://rreact.dei.unipd.it
Reliability and Radiation Effects on Advanced CMOS Technologies
Theme
What is the impact of CMOS technologyWhat is the impact of CMOS technology evolution on the radiation sensitivity of modern digital integrated circuits?digital integrated circuits?
As we explore this issue we will investigate inAs we explore this issue, we will investigate in more details the basic mechanisms underlying the radiation response of CMOS circuits
S. Gerardin, Legnaro 23/4/2009 2
CMOS S li
Outline
CMOS ScalingFeature SizeNe Materials and Architect resNew Materials and ArchitecturesFrequency
Total Ionizing DoseTotal Ionizing DoseBasic MechanismsImpact of ScalingImpact of ScalingNew Phenomena
Single Event EffectsgSingle Event UpsetsSingle Event Transients
S. Gerardin, Legnaro 23/4/2009 3
The MOSFET
How to make it faster?faster?Until early 2000’s
Scaling!Scaling!Afterwards
Scaling and…Scaling and…New materialsNew device architectures
Intel 4004 featuring 10-μm MOSFETs
S. Gerardin, Legnaro 23/4/2009 4
www.intel.com/museum
The MOSFET
How to make it faster?faster?Until early 2000’s
Scaling!Scaling!Afterwards
Scaling and…Scaling and…New materialsNew device Core 2 Duo transistorarchitectures
M Bohr ISSCC 2009
Core 2 Duo transistorIntel 45-nm node, featuring strained silicon, high-k gate oxide, and metal gate
S. Gerardin, Legnaro 23/4/2009 5
M. Bohr, ISSCC 2009
Classic Scaling
Parameter Scaling FactorFeature Size tox, L, W 1/kDoping kVoltage 1/kCurrent 1/kCurrent 1/kCapacitance 1/kDelay Time 1/kP Di i i 1/k2Power Dissipation 1/k2
Power Density 1
Scaling of operating voltage has actually been slower than feature size reduction
S. Gerardin, Legnaro 23/4/2009 6
feature size reduction
Moore’s Law
Exponential decrease of the feature size with time
Exponential increase in transistor count
M. Bohr, ISSCC 2009
count
S. Gerardin, Legnaro 23/4/2009 7
Materials
TransistorsTransistorsHigh-k gate oxide ⇒
• ↑ channel control • ↓ leakage
Strained Silicon ⇒• ↑ drive current
Silicides ↓ i i t• ↓ series resistance
Back-endLow k inter metal layersLow-k inter-metal layers
• ↓ stray capacitanceCopper vs Aluminum
S. Gerardin, Legnaro 23/4/2009 8
Copper vs Aluminum• ↓ series resistance
www.intel.com/research
Materials < 1990s
H He
Li Be B C N O F Ne
Na Mg Al Si P S Cl Ar
K Ca Sc Ti V Cr Mn Fe Co Ni Cu Zn Ga Ge As Se Br Kr
Rb Sr Y Zr Nb Mo Tc Ru Rh Pd Ag Cd In Sn Sb Te I Xe
Cs Ba La Hf Ta W Re Os Ir Pt Au Hg Tl Pb Bi Po At Rng
Fr Ra Ac Rf Db Sg Bh Hs Mt Ds
Ce Pr Nd Pm Sm Eu Gd Tb Dy Ho Er Tm Yb Lu
Th Pa U Np Pu Am Cm Bk Cf Es Fm Md No Lr
S. Gerardin, Legnaro 23/4/2009 9
CMOS Materials > 1990s
H He
Li Be B C N O F Ne
Na Mg Al Si P S Cl Ar
K Ca Sc Ti V Cr Mn Fe Co Ni Cu Zn Ga Ge As Se Br Kr
Rb Sr Y Zr Nb Mo Tc Ru Rh Pd Ag Cd In Sn Sb Te I Xe
Cs Ba La Hf Ta W Re Os Ir Pt Au Hg Tl Pb Bi Po At Rng
Fr Ra Ac Rf Db Sg Bh Hs Mt Ds
Ce Pr Nd Pm Sm Eu Gd Tb Dy Ho Er Tm Yb Lu
Th Pa U Np Pu Am Cm Bk Cf Es Fm Md No Lr
S. Gerardin, Legnaro 23/4/2009 10
CMOS Materials today
H He
Li Be B C N O F Ne
Na Mg Al Si P S Cl Ar
K Ca Sc Ti V Cr Mn Fe Co Ni Cu Zn Ga Ge As Se Br Kr
Rb Sr Y Zr Nb Mo Tc Ru Rh Pd Ag Cd In Sn Sb Te I Xe
Cs Ba La Hf Ta W Re Os Ir Pt Au Hg Tl Pb Bi Po At Rng
Fr Ra Ac Rf Db Sg Bh Hs Mt Ds
Ce Pr Nd Pm Sm Eu Gd Tb Dy Ho Er Tm Yb Lu
Th Pa U Np Pu Am Cm Bk Cf Es Fm Md No Lr
S. Gerardin, Legnaro 23/4/2009 11
Device Architecture
Silicon On InsulatorSilicon On Insulator (SOI)
Partially DepletedPartially DepletedFully DepletedDouble Gate
Gate
FinFETsSeveral Advantages
Drain Source
Reduced CapacitanceImproved Electrostatics
B tt Sh t Ch l
Substrate
⇒ Better Short Channel Effects
S. Gerardin, Legnaro 23/4/2009 12
Bulk MOSFET
Device Architecture
Silicon On InsulatorSilicon On Insulator (SOI)
Partially DepletedGate
Partially DepletedFully DepletedDouble Gate
Drain Source
Buried OxideFinFETs
Several Advantages
SubstrateReduced CapacitanceImproved Electrostatics
B tt Sh t Ch l
Partially Depleted SOI MOSFET
⇒ Better Short Channel Effects
S. Gerardin, Legnaro 23/4/2009 13
Partially Depleted SOI MOSFET
Device Architecture
Silicon On InsulatorSilicon On Insulator (SOI)
Partially DepletedGate
Drain Source
Partially DepletedFully DepletedDouble Gate
Buried OxideFinFETs
Several Advantages
SubstrateReduced CapacitanceImproved Electrostatics
B tt Sh t Ch l
Fully Depleted SOI MOSFET
⇒ Better Short Channel Effects
S. Gerardin, Legnaro 23/4/2009 14
Fully Depleted SOI MOSFET
Device Architecture
Silicon On InsulatorSilicon On Insulator (SOI)
Partially DepletedGate1
Drain Source
Partially DepletedFully DepletedDouble Gate
Gate2FinFETs
Several Advantages
SubstrateReduced CapacitanceImproved Electrostatics
B tt Sh t Ch l
Double Gate SOI MOSFET
⇒ Better Short Channel Effects
S. Gerardin, Legnaro 23/4/2009 15
Double Gate SOI MOSFET
Device Architecture
Silicon On Insulator
WFIN
Silicon On Insulator (SOI)
Partially Depleted
L GATE
D L GATE
D L GATE
D L Gate
Drain Partially DepletedFully DepletedDouble Gate
HFIN
GateS S
(100)
(110)
S
Source
(100)
(110)
FinFETsSeveral Advantages
Oxide
BOX BOX BOX
Source
Buried Oxide
Reduced CapacitanceImproved Electrostatics
B tt Sh t Ch l
FinFET
⇒ Better Short Channel Effects
S. Gerardin, Legnaro 23/4/2009 16
Frequency and Parallelism
Until a few years ago, increasing g , gfrequency was the focusN d tNow, due to power dissipation constraints, parallelism (multi-core CPU) has become the majorbecome the major front
S. Gerardin, Legnaro 23/4/2009 17
Total Ionizing Dose
Parametric shifts in transistors parameters dueParametric shifts in transistors parameters due to the build-up of trapped positive charge and interface states caused by several low-LETinterface states caused by several low LET particles striking a chip
Total Ionizing Dose affects dielectric layers (e.g., gate oxide, isolation oxides)
S. Gerardin, Legnaro 23/4/2009 18
Basic Mechanisms – Part 1
Radiation strikes generating e-h pairsRadiation strikes generating e-h pairsA large part of the e-h pairs recombineSurviving electrons are quickly swept out of the oxide
S. Gerardin, Legnaro 23/4/2009 19
g q y pSurviving holes slowly transport in the opposite direction
Basic Mechanisms – Part 2
Holes hop through shallow defects and release HydrogenHoles get trapped close to the interfaceH d t i t f t
S. Gerardin, Legnaro 23/4/2009 20
Hydrogen generates interface traps
Charge Yield
A large part of the initial e-h pairs recombinerecombine immediately after generation
↑Electric field ↑⇒Charge Yield ↑LET ↑⇒ ChargeLET ↑⇒ Charge Yield ↓
F. B. McLean, et al., Tech. Rep. HDL-TR-2129, 1987.
S. Gerardin, Legnaro 23/4/2009 21
M. R. Shaneyfelt, et al., IEEE Trans. Nucl. Sci., Dec. 1991.
Hole Trapping vs Field
Cross section of oxide traps depends on the electric fieldon the electric fieldWorst-case bias conditions depend on charge yield and oxide-trap dependence on pelectric field
M. R. Shaneyfelt, et al., IEEE Trans. Nucl. Sci., 1990
S. Gerardin, Legnaro 23/4/2009 22
y
Interface States vs Time
Interface trap pgeneration occurs over time, after radiation exposureradiation exposure, due to holes and Hydrogen transport t th i t fto the interfaceBias conditions play a fundamental rolea fundamental role
M R Shaneyfelt et al IEEE Trans Nucl Sci 1992
S. Gerardin, Legnaro 23/4/2009 23
M. R. Shaneyfelt, et al., IEEE Trans. Nucl. Sci., 1992.
Interface-States vs Dose Rate
No true dose-rate dependenceGiven equal time from the irradiationfrom the irradiation, the same amount of interface state and t d h illtrapped charge will occur, regardless of dose rate
D M Fleetwood et al IEEE Trans Nucl 1988
S. Gerardin, Legnaro 23/4/2009 24
D. M. Fleetwood, et al., IEEE Trans. Nucl.1988.
Hole Trapping vs Time
T d hTrapped charge changes over time
No dose-rate effects
D. M. Fleetwood, et al., IEEE Trans. Nucl.1988.
S. Gerardin, Legnaro 23/4/2009 25
Annealing Mechanisms
Neutralization of t d h ltrapped holes due
Tunneling Thermal Emission
Annealing ofAnnealing of interface traps does not occur
P. J. McWhorter, et al., IEEE Trans. Nucl. Sci., 1990.
does o occuat room temperature
S. Gerardin, Legnaro 23/4/2009 26
Oxide Thickness Scaling
Si l d l f h i d dSimple model for charge trapping dependence on oxide thickness:
ΔVt = Qot/Cox = k ⋅ tox2
The thinner the oxide, the smaller the degradation
Actually, things go even better for ultra-thin oxides (< 10 nm)…
S. Gerardin, Legnaro 23/4/2009 27
Oxide Thickness
Rapidly decreasing charge trapping andSaks and Ancona, 1986
S. Gerardin, Legnaro 23/4/2009 28
Rapidly decreasing charge trapping and interface state formation in ultra-thin oxides
Gate Leakage Current
100
10-21.2 nm
1 5
Fowler-Nordheim
2 ]
10
10-4
1.5 nm
1.8 nm2.1 nm 2 8 4.0 nm
tunnelingDirect tunneling
J g[A
/cm
2
10-6
10 8
2.8 nm
3.5 nm
tunnelingLeakage is a limit to
10-8
10-105.2 nm
scaling
10-12
0 1 2 3 4 5 6D.J. Frank et al., Proc. IEEE, 2001
S. Gerardin, Legnaro 23/4/2009 29
Vg [V]
Fowler-Nordheim Tunneling
φ
Electron tunneling through a triangular barrier
2 expFN oxBJ A EE
⎛ ⎞= ⋅ ⋅ −⎜ ⎟⎝ ⎠Cathode
φS
oxE⎝ ⎠SiO2 Anode
3
2
oq mA ⋅=
324 2 ox SmB φ⋅ ⋅ ⋅
=216 ox Smπ φ⋅⋅ ⋅h 3 q⋅ ⋅h
S. Gerardin, Legnaro 23/4/2009 30
R. Fowler and L. Nordheim, Proc. Roy. Soc. A, 1928
Direct Tunneling
Electron tunneling through a trapezoidal barrier
324 2
3ox SmBqφ⋅ ⋅ ⋅
=⋅ ⋅h
Cathode
φS
3
216o
ox S
q mAmπ φ⋅
⋅=
⋅ ⋅h
SiO2
Cathode
Anode
( )33
2 22
2 32
expS S ox oxox
Dox SS
q E tA E BJEq E t
φ φ
φφ
⎡ ⎤− − ⋅ ⋅⋅ ⎢ ⎥= ⋅ − ⋅⎢ ⎥⎛ ⎞⋅ ⋅ ⎣ ⎦1
SS ox ox
S
q E t φφφ
⎢ ⎥⎛ ⎞− ⋅ ⋅ ⎣ ⎦−⎜ ⎟⎝ ⎠
S. Gerardin, Legnaro 23/4/2009 31
Wentzel-Kramers-Brillouin (WKB) approximation
Radiation Induced Leakage Current
10-4
58-MeV e, tox=6nm • When tox<7 nm
i di ti i d
²)
10-5
10-650
Dose (Mrad(Si))
irradiation induces leakage current at low fields
J g(A
/cm
²
10-7
10-8 4
50• Radiation Induced
Leakage Current (RILC)J
10-9
10-10
fresh(RILC)
• True DC conduction2 3 4 5 6 7 8
Eox (MV/cm)
10• Not depending on
radiation LET
S. Gerardin, Legnaro 23/4/2009 32
Model
Radiation induced defects: electron neutral traps
C
φ
Conduction mechanism: inelastic electron Trap Assisted Tunneling (TAT)
ΔUModeled by WKB or other methods
O id fi ld d d ttox
Oxide field dependent
Most effective RILC defects at ≈ tox/2at tox/2
Generation mechanism correlated to the trapped
iti h
S. Gerardin, Legnaro 23/4/2009 33
positive charge
Fitting RILC
10-7
8
measured8 MeV electrons
Defectcharacteristics:
10-8
10-9
8 MeV electrons1.3 eV below oxide Ec
D it10
10-10
negative
positive
Density proportional to dose
10-11
positive
i l t d
Independent of radiation
10-12
1 2 3 4 5 |Vgate| (V)
simulated LET (for low LET)
S. Gerardin, Legnaro 23/4/2009 34
L. Larcher et al., IEEE-TNS, 1999
Floating Gate Memories
El t t d iElectrons stored in the FG
VTH grows(CG)
VTH grows
Writing (Flash):Channel Hot
(FG)
Channel Hot Electron tunnelling
Tunnel Oxide
Erasing (Flash): Fowler-NordheimM i li bilit i Nordheim tunnelling
Main reliability issues:- Endurance (W/R/E cycles)- Data retention
S. Gerardin, Legnaro 23/4/2009 35
Long-term Effects
L t il ft
ity
93.4%
99.99%
2x107ions/cm2
Large tails after heavy ions irradiation
e pr
obab
ili
0 67%
4.8%
30.7% 2x10 ions/cmNumber of bits in tail does not d d i
umul
ativ
e0 012%
0.09%
0.67%
Fresh
I depend on ion LET (only on fluence)
3 4 5 6 7 8
Cu
0.002%
0.012% FreshNi Ag fluence)ΔVTH strongly depends on ion 3 4 5 6 7 8
VTH (V)LET
Only hit cells are considered in next experiments
S. Gerardin, Legnaro 23/4/2009 36
Cellere et al, T-NS, 2003, 2004, and APL, 2005
Long-term Effects
99 99%Only hit FGs were
obab
ility
30.7%93.4%
99.99%After 20 days
programmed
After only ulat
ive
pro
0 09%0.67%4.8%
y30min a clear tail appears… C
umu
0.002%0.012%
0.09%
…which increases
d
3 4 5 6 7 8
VTH (V)After program
After 30 imore and
more with time RILC (R di ti I d d L k C t)
programminCellere et al, T-NS, 2003, 2004, and APL, 2005
S. Gerardin, Legnaro 23/4/2009 37
time RILC (Radiation Induced Leakage Current)
Long-term Effects
What’s going on?Floating gate(electrons stored)
What’s going on?Ion generates a plasma of electrons and holes
Oxi
de
(electrons stored)
Ion track
electrons and holes
unne
l O holeselectrons
TuSubstrate
Larcher et al T-NS 2003
S. Gerardin, Legnaro 23/4/2009 38
Larcher et al, T NS, 2003Cellere et al, T-NS, 2005
Long-term Effects
What’s going on?Floating gate(electrons stored)
What’s going on?Ion generates a plasma of electrons and holes
Oxi
de
(electrons stored)electrons and holesPrompt columnar recombination
unne
l O holeselectrons
TuSubstrate
Larcher et al T-NS 2003
S. Gerardin, Legnaro 23/4/2009 39
Larcher et al, T NS, 2003Cellere et al, T-NS, 2005
Long-term Effects
What’s going on?Floating gate(electrons stored)
What’s going on?Ion generates a plasma of electrons and holes
Oxi
de
(electrons stored)electrons and holesPrompt columnar recombination
unne
l O holeselectrons
Followed/accompanied by generation of oxide defects
Tu Oxide defects
Substrate
Larcher et al T-NS 2003
S. Gerardin, Legnaro 23/4/2009 40
Larcher et al, T NS, 2003Cellere et al, T-NS, 2005
Long-term Effects
What’s going on?Floating gate(electrons stored)
What’s going on?Ion generates a plasma of electrons and holes
Oxi
de
(electrons stored)electrons and holesPrompt columnar recombination
unne
l O
Electron tunnelingFollowed/accompanied by generation of oxide defects
Oxide defects are used Tu Oxide defectsOxide defects are used by electrons to escape the FG
Substratethe FG
multi-Trap Assisted Tunneling (m-TAT)
Larcher et al T-NS 2003
S. Gerardin, Legnaro 23/4/2009 41
Larcher et al, T NS, 2003Cellere et al, T-NS, 2005
Long-term Effects
How can we evaluate the current along this path?Floating gate( )C id th i t k
Oxi
de
(electrons stored)
Randomly generate a G i di ib i
Consider the ion track
unne
l OGaussian distribution of defects I=ΣIn
TuEvaluate the current through each possible path (phonon assisted) Substrate
σ=8nm
path (phonon-assisted)
Then sum all the t Larcher et al T NS 2003
S. Gerardin, Legnaro 23/4/2009 42
currents Larcher et al, T-NS, 2003Cellere et al, T-NS, 2005, 2006
Long-term Effects
1818
Symbols average
10-18
10-19
10-20
10-18
10-19
10-20average, experimental dataBars variance IG
(A) 10-21
10-22
10-23I G (A
) 10-21
10-22
10-23Bars variance (spread) of experimental data Experimental
Si l t d
10 23
10-24
10-25 ExperimentalSi l t d
10 23
10-24
10-25
Lines calculations FOX (MV/cm)
Simulated0.8 1 1.2 1.4 1.6 1.8
10-26
FOX (MV/cm)
Simulated0.8 1 1.2 1.4 1.6 1.8
10-26
Current as low as 10-24A 1n(fA)
S. Gerardin, Legnaro 23/4/2009 43
Larcher et al, T-NS, 2003
(Long-term Effects)
O l d ith d l f th FG ll th l kOnce coupled with a model of the FG cell, the leakage model can be used to derive the VTH evolution over time
1
0.1
1
obab
ility
164h
Symbols = exp.Lines = sim.After Iodine
(LET=640.01
ativ
e pr
o1.5h
164h
96h
(LET=64 MeVcm2/mg)irradiation
0 0001
0.001
Cum
ula
0.00014 6 8 10
VTH (V)
S. Gerardin, Legnaro 23/4/2009 44
Cellere et al, T-NS, 2005
Nitrided Gate Oxides
Wh Ni id d O id ?Why Nitrided Oxides?Improve dielectric constantRed ce leakage c rrentReduce leakage currentPrevent boron penetrationBetter hot carrier reliabilityBetter hot carrier reliability
Radiation HardnessRadiation HardnessSuppression of interface states, Nitrogen layer acts as a barrier for Hydrogen diffusionComparable density of oxide charge-traps in SiON and SiO2
S. Gerardin, Legnaro 23/4/2009 45
High-k Gate Oxides
R h di tiResearch on radiation effects in high-k oxides far less advanced than in
SiO2
far less advanced than in SiO2
Different Band StructureSmaller bandgap ⇒ less energy for e-h pair generation
HfO2 SiMetalGate generation
Recombination, Charge Yield?P i i d f
Gate
Pre-existing defectsDifferent barriers ⇒different carrier tunneling
S. Gerardin, Legnaro 23/4/2009 46
gprobabilities
Thick High-k Gate Oxides
Thi k idThicker oxides, a return to charge trapping?trapping?Significant number ofnumber of electron traps in HfO2 in addition to 2 hole trapsMinimal charge trapping for thin HfO2 with buffer SiO l
Gate oxide:1nm SiO2 + 7.5nm HfO2 EOT = 2.3nm
S. Gerardin, Legnaro 23/4/2009 47
SiO2 layerS. K. Dixit, et al., IEEE Trans. Nucl. 2007.
Thin High-k Gate Oxides
Thi k idThicker oxides, a return to charge trapping?trapping?Significant number ofnumber of electron traps in HfO2 in addition to 2 hole trapsMinimal charge
Gate oxide:1nm SiO2 + 3.0nm HfO2 EOT = 1.5nmtrapping for thin HfO2 with buffer SiO l
S. Gerardin, Legnaro 23/4/2009 48
S. K. Dixit, et al., IEEE Trans. Nucl. 2007 SiO2 layer
SOI: Partially Depleted Devices
Thi k b i d id
Gate
Thick buried oxide sensitive to radiationA t f hGate
Drain Source
Amount of charge trapping depends on SOI waferDrain Source
Buried Oxide (SiO )
SOI wafer technology (SIMOX vs wafer-bonding)
+++++++++++++++++++++++
Substrate
Buried Oxide (SiO2)g)
Parasitic Source-Drain leakage
Substrate develops in partially depleted devices
S. Gerardin, Legnaro 23/4/2009 49
SOI: Partially Depleted Devices (2)
J.R. Schwank, et al., IEEE Trans. Nucl. 2008
Threshold voltage shift in the parasitic back gate transistor leads to drain-source leakage
S. Gerardin, Legnaro 23/4/2009 50
SOI: Fully Depleted Devices
Thi k b i d id
Gate
Thick buried oxide sensitive to radiationA t f hGate
Drain SourceAmount of charge trapping depends on SOI wafer
Buried Oxide (SiO2)
SOI wafer technology (SIMOX vs wafer-bonding)
+++++++++++++++++++++++
Substrate
g)Coupling with the back gate leads to
Substrate changes in the front gate t i t
S. Gerardin, Legnaro 23/4/2009 51
transistor
SOI: Fully Depleted Devices (2)
J.R. Schwank, et al., IEEE Trans. Nucl. 2003
Coupling means back gate Vth shift leads to changes
S. Gerardin, Legnaro 23/4/2009 52
in front-gate Vth
Single Event Effects
S h i ff d i l i l hi iStochastic effects due to a single particle hitting the sensitive area of a device
SRAMSi l E t U t (SEU)Single Event Upsets (SEU)Single Bit Upsets (SBU)Multiple Cell Upsets (MCU)Multiple Cell Upsets (MCU)Muliple Bit Upsets (MBU)
Combinational LogicSingle Event Transients (SET)
S. Gerardin, Legnaro 23/4/2009 53
g ( )
Simulated heavy ion e-h track in Si
Fe ions 275 MeVLET=24 MeVcm2/mgLET=24 MeVcm /mg
LET metrics in Si:
1 MeVcm2/mg
6.4.104 e-h pairs/μm
10 fC/
Electron-Hole density (cm-3)
10 fC/μm
S. Gerardin, Legnaro 23/4/2009 54
Electron Hole density (cm )P. Foulliat, EWRHE 2004
Heavy ion e-h track in Si vs. CMOS minimum size
CMOS generationg
0.35 μm
0 250.25 μm
0.18 μm
0.13 μm
9090 nm
…
S. Gerardin, Legnaro 23/4/2009 55
32 nm
SEU vs MBU
Two generations after
S. Gerardin, Legnaro 23/4/2009 56
Two generations after…
Single Bit Upsets, Neutrons
SEU/bit constant or even decreasing!
N. Seifert, et al., IRPS 2008 High-k gate
id
S. Gerardin, Legnaro 23/4/2009 57
Area effect wins over reduction in capacitance oxide
Multiple Bit Upsets, Neutrons
Percentage of Multiple Bit Upsets increases (even
N. Seifert, et al., IRPS 2008
S. Gerardin, Legnaro 23/4/2009 58
more for other vendors)
Multiple Bit Upsets, Neutrons (2)
MCU lMCU cluster size almost independentindependent of technology nodeodeThe number of affected bits grows with each generation
S. Gerardin, Legnaro 23/4/2009 59
N. Seifert, et al., IRPS 2008
Multiple Bit Upsets, Heavy Ions
Strong dependence on LETN. Seifert, et al., IRPS 2008
S. Gerardin, Legnaro 23/4/2009 60
MCU’s dominate at high LET
SOI & Single Event Upset
R d i f
GateHeavy ion
Reduction of sensitive volume (less chargeGate
Drain Source+-+
(less charge collection)BipolarDrain
(n)Source
(n)-++-+--+
Bipolar amplification may increase sensitivity
Substrate
Buried Oxide (SiO2)y
Bipolar amplification
Substrate important also on bulk devices
S. Gerardin, Legnaro 23/4/2009 61
MCU: Bulk vs SOI
MCU i b lkMCUs in some bulk technologies
occur preferentially yalong bitlines (inside p-wells)increase with increasing supply voltage (contrary to SBU)due to bipolar amplification (“battery” effect), i i ll
G. Gasiot, et al., IRPS 2008increase in well potential due to particle strike affects many devices
S. Gerardin, Legnaro 23/4/2009 62
many devices
MCU: Bulk vs SOI
MCU i SOIMCUs in SOI due to geometrical effectseffectsdevices are separate (no common well)
G. Gasiot, et al., IRPS 2008
S. Gerardin, Legnaro 23/4/2009 63
Single Event Transients
M l ’ h lMemory elements aren’t the only resource sensitive to ionizing radiation, also combinatorial logic can be affectedlogic can be affected
Single Event Transients (SET) can originate fromSingle Event Transients (SET) can originate from particle strikes in reverse-biased pn junctionsbelonging to the combinatorial part of a circuitbelonging to the combinatorial part of a circuit
SETs can eventually propagate to memorySETs can eventually propagate to memory elements and be latched
S. Gerardin, Legnaro 23/4/2009 64
SET: clock frequency
SET
Combinational Logic D QLogic Q
Logical masking can block SET’sClock
The higher the frequency, the larger the probability of catching a transient (temporal masking)
S. Gerardin, Legnaro 23/4/2009 65
Electrical masking…
SET: attenuated propagation
Low LET below
iti l LETcritical LET, attenuated propagationpropagation
S. Gerardin, Legnaro 23/4/2009 66
P. Dodd et al., IEEE-TNS 2004
SET: non-attenuated propagation
High LET above
iti l LETcritical LET, non-attenuatedattenuated propagation
S. Gerardin, Legnaro 23/4/2009 67
P. Dodd et al., IEEE-TNS 2004
SET: width and scaling
The higher the LET, the l thlonger the pulseC lComplex dependence onon technology
S. Gerardin, Legnaro 23/4/2009 68
P. Dodd et al., IEEE-TNS 2004
SET: critical LET
C iti l LETCritical LET for non-attenuated propagation decreases with featurewith feature sizeSOI lessSOI less sensitivethan bulk CMOS
P Dodd et al IEEE TNS 2004
CMOS (shorter transients)
S. Gerardin, Legnaro 23/4/2009 69
P. Dodd et al., IEEE-TNS 2004 )
SET vs SEU
SETs are expected to d i t thdominate the radiation sensitivity insensitivity in future technologies, g ,for high performance applications
S. Gerardin, Legnaro 23/4/2009 70
R. Baumann, IEEE-TDMR 2003
Conclusions
Simple scaling is no longer enough to sustain the pace of Moore’s law, new materials and device architectures have been/will have to be introduced that may affect radiation responseGate oxide sensitivity to TID Effects has improvedthanks to scaling with no major issue from high kthanks to scaling, with no major issue from high-k layers. Isolation oxide may be still a problemRadiation Induced Leakage Current can be an gissue for the reliability of Flash Memories and DRAMsThe presence of the buried oxide in SOI may be detrimental to TID sensitivity but help with SEEdetrimental to TID sensitivity but help with SEEMultiple Cell/Bit Upsets and Single Event Transients are a growing concern for digital circuits
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g g g
Acknoledgment
M h kMany thanks to :
Alessandro Paccagnella, Padova UniversityGiorgio Cellere, Padova UniversityJim Schwank, SANDIA National LabsAll the referenced authors
For providing useful suggestions and/or part of the material this presentation is based upon
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