SiC Activation and Oxidation Technology and related Production … · 2018-11-16 · SiC Activation and Oxidation Technology and related Production Tools Patrick Schmid, Senior Manager

SiC Activation and Oxidation Technology and related Production Tools

Patrick Schmid,

Senior Manager Process & Technology

Centrotherm international AG

Württemberger Str. 31, 89143 Blaubeuren, Germany

m: [email protected], p: +49 7344 918 6228

15. Nov. 2018

mailto:[email protected]

© centrotherm international AG

Outline

▪ Motivation for SiC

▪ SiC activation

▪ SiC activation techniques / tools

▪ SiC annealing aspects

▪ SiC carbon vacancy generation and annihilation

▪ SiC trench annealing process

▪ Temperature monitoring of annealing tool

▪ SiC oxidation

▪ SiC Oxidation and POA aspects

▪ SiC Oxidation and POA process windows

▪ Uniformity aspects Si vs. SiC

▪ High temperature oxide conformality

▪ El. MOSCAP & MOSFET data

▪ Conclusions


Motivation: Why SiC and not Si?

Activator_Oxidator_2017.07.14.pptx Confidential 3

Benefits of SiC:

▪ 10x higher breakdown field

▪ 100x lower RON

▪ 10x higher blocking voltage

▪ 3x higher Energy gap:

▪ Junction Temp. > 200 °C possible

▪ Current density > 1 kA/cm2 possible

▪ > 3x thermal conductivity

▪ > 10x higher power density


Excellent Perspectives for SiC & GaN Market (source IHS Markit)

▪CAGR: 28% till 2020 then 40% till 2020 and beyond


In 10 years

SiC & GaN market is

predicted to grow by factor

20-30!

Today


SiC has good line compatibility

▪For SiC power device manufacturing most Si equipment can be used simply by adjusting the process conditions

▪However some additional SiC specific components are needed

▪Enabling components: ▪SiC wafers + SiC epi

▪HT (high temperature) activation

▪Etc.

▪Better to have components:▪HT implantation

▪HT oxidation and nitridation tools

▪Special contact formation (RTP & Laser)

▪Specific thinning & dicing

▪ Inspection metrology (for transparent wafers)

▪Bonding & packaging (sintering..)

▪Etc. (this list becomes longer with maturity of SiC)



A

SiC Frontend Applications - MOSFET

6

Conventional Trench MOSFET from Rohm

Activation of implants (c.ACTIVATOR150)

Smoothing of trench (c.ACTIVATOR150)

Gate oxide formation (c.OXIDATOR150)

Metal contact annealing (c.RAPID200)

Doped Poly Deposition (VerticooMini)

G

M

S

P

A

M

SG

MP


SiC Activation Techniques / Equipment

▪ Activation of Al+ and P+ implants require temperatures between 1600°C and 2000°C

▪ Need for specific annealing equipment

For R&D (and small volume)

- RF heated furnaces

- Rapid thermal annealing (RTA)

- Microwave heating

- Higher heating rates (up to 1000K/min)

- Higher cooling rates

- Poor(er) T uniformities

- More wafer stress

- Only single wafer or small batches

- Freeze in of Vc

- Ar plasma jet heated - Higher heating rates

- Higher cooling rates

- Contamination?

- Surface damages?

- Precise temperature control difficult

- Freeze in of Vc

- Excimer Laser heating - No surface reconstruction w/o capping

- Probably no Vc generation

- No defect annealing / crystalline

recovery

- High stress in surface layer

- Precise temperature control difficult

Annealing type Pros Cons

- Resistive heated furnace

(used at >95% of production

sites)

- Good T uniformities

- High activation grades

- Good crystal recovery & defect

annealing (mobility)

- High thermal budget capability

- Partial Vc annihilation by slow cooling

- Big batch sizes

- Slower heating rates (up to 100K/min)

- Slower cooling rates (up to 30 K/min)


SiC Annealing Aspects

▪ Annealing SiC at temperatures above ~1550°C leads to:

▪ Si evaporation from SiC wafer surfaces

▪ Minimization of relatively high free surface energy of SiC(0001) wafers with few degree off angle (for better home epitaxy) leads to surface reconstruction step bunching

Source: T. Kimoto, “Fundamentals of Silicon Carbide Technology”


SiC Annealing Aspects: Control of Si loss and Surface reconstruction

▪ Cap less annealing with Si background pressure (SiH4, Si effusion, etc):

▪ Si loss can be compensated, but surface reconstruction is difficult to suppress [1]

▪ Process not compatible with C-capping due to formation of SiC particles in capping!

▪ This “cap less” approaches never made it from R&D to mass production

▪ Capping techniques:

▪ Capping layers are the best approach to suppress surface reconstruction

▪ SiO2, Si3N4, AlN and carbon caps were investigated [2, 3]

▪ Carbon caps showed best temperature stability and overall results [3]

▪ Carbon cappings (state of the art, almost 100% of production sites use c-caps):

▪ (~75% of production sites use photoresist cappings, for example: AZ5214

▪ Ex-situ prebake resist at > 350°C is strongly recommended

▪ Carbonization of resist occurs during implant annealing up to high temperatures (>1300°C)

▪ (~25% of production sites use sputtered carbon caps, because they cause less desorption and contamination during annealing

▪ The C-cap is removed by thermal oxidation (~900°C), RIE in O2 or plasma ashing

▪ Depending on process flow and device type (i.e. vertical devices w/o thinning), surface roughening might have to be also prevented by coating on wafer backsides


SiC Annealing Aspects: Surface Roughening vs.Dopant Concentration & Implantation Temperature

▪ With higher implant doses and increasing lattice amorphization the surface roughness increases after annealing

▪ High temperature implantation helps to reduce lattice damage and implantation defects

Source: T. Kimoto, “Fundamentals of Silicon

Carbide Technology”

Source: M. Rambach, “Implantation and

Annealing of Aluminum in 4H Silicon

Carbide” [4]


SiC Annealing Aspects: Activation vs. Temperature

▪ Higher activation temperatures improve activation & annealing of implantation damages [5, 6]

11Activator_Oxidator_2017.07.14.pptx Confidential

▪ Activation increases all the way up to 2050°C but at same time the mobility decreases

▪ Significant Rs reduction was observed up to 1950°C

Activation

Mobility

Sheet resistance after 10min annealing

Al+ box implant at 700°C, total dose 3e15at/cm2


SiC Annealing Aspects: Surface Roughness vs. Temperature

Temperature [°C] Rq [nm] Ra [nm]

1650 2,01 1,65

1850 2,19 1,79

1950 2,82 2,21

2050 3,56 2,84

0

0.5

1

1.5

2

2.5

3

3.5

4

1600 1650 1700 1750 1800 1850 1900 1950 2000 2050 2100

AFM Surface Roughness

Rq [nm] Ra [nm]

▪ Somewhere between 1850°C and 1950°C the surface roughness seems to increase stronger

▪ This is also why typical annealing temperatures are < 1900°C


▪ 2000°C, 10min, free fall cooling (ct standard,cooling rates < 25 K/min)

▪ 2000°C, 10min, free fall cooling + 1500°C 3h (ct)

SiC Annealing Aspects: Carbon Vacancy (Vc) Conventional vs. RF Annealing DLTS(deep level transient spectroscopy) Results from DOE with Univ. Oslo


With courtesy Dr. Hussein Ayedh, University Oslo [7, 8]

RF Furnace with

fast cooling

▪ For low Vc, cooling rates < 15 K/min required


SiC Annealing: Process Window


▪ Typical annealing conditions for production

▪ Temperature: 1600°C - 1950°C, most sites run between 1650°C and 1850°C ▪ Time: 30 min – 5 min▪ Pressure: 20 mbar – atmosphere in Ar


SiC Trench Annealing in H2

▪ Reason for trench annealing:

▪ Trench rounding

▪ Removal of impurity traces from RIE etching

▪ Trench sidewall smoothing

▪ Process window for trench annealing

▪ Pressure: 1 mbar - 30 mbar ▪ Temperature: 1400°C - 1500°C▪ H2 / Ar: 0% - 100%

SiO2

SiC

RIE typical micro trenching

With courtesy Dr. Anton Bauer, IISB FhG Erlangen


c.ACTIVATOR150 SiC Trench Annealing0.8μm Trench Cross Section Before H2 Anneal

cross section tilted cross section

top corner enlargement bottom corner enlargement



cross sectiontop view

c.ACTIVATOR150 SiC Trench Annealing 0.8μm Trench Cross Section After H2 Anneal



Temperature Monitoring of Annealing Tool

▪ Running daily implanted monitor wafers and measure their sheet resistance (Rs) with automated 4 point prober is standard to monitor Si wafer annealing equipment (RTA, Laser..)

▪ On SiC wafers the 4 point prober does not giver reliable results after annealing, since the needles do not penetrate into SiC and make only poor contact [9]

▪ Rs data can be derived from:

▪ TLM (Transfer Line Measurement)

▪ Van-der-Pauw Hall measurement (more complex but delivers carrier concentration & mobilities)

▪ From el. Device data

▪ To calculate temperature uniformities from Rs uniformities, the temperature sensitivity of the implant condition must be known or derived from temperature split run

▪ With relatively little preparation effort and little side effects, the temperature at ~1414°C can be also evaluated by performing gradual Si melt test

▪ All of these methods have some flaws and take too long for daily monitoring, consequently

▪ Annealing tools must run very stable

▪ A more easy and faster monitoring needs to be developed

Titel der Präsentation | Name 18CONFIDENTIAL


Temperature Monitoring by Sheet Resistance (Rs)

▪ WIW, sheet Resistance (Rs) results

▪ The typical tool related WIW uniformity is below 1% (1s).

▪ The guaranteed added WIW uniformity is < 2.5% for 100 mm and 150 mm wafers

19

Slot #

RS,Avg

[Ω/sq]RS,Min [Ω/sq]

RS,Max

[Ω/sq]

Stdev.(1s)

[Ω/sq]

Stdev.(1s)

[%]

Spec. (1s).

(%)

1 1000 989 1007 4,7 < 1% < 2.5%

13 1004 995 1013 5,7 < 1% < 2.5%

25 997 987 1005 5,4 < 1% < 2.5%

38 1001 987 1009 6,1 < 1% < 2.5%

50 1019 1003 1029 6,4 < 1% < 2.5%

Substrate: Monocrystalline SiC

Implantation: Al; >1014cm-2; >400°C

Annealing: >1800°C; 5min; Ar; 20mbar

Activator_Oxidator_2017.07.14.pptx Confidential


Uniformity with Melt Test


Temperature Top, Slot 55 Center, Slot 28 Bottom, Slot 01

1408°C no melting

1410°C partial melting

1412°C full melting

T range WIW & WTW ~4 K


c.ACTIVATOR150



SiC Oxidation and POA Aspects

▪ Dry oxidation + POA (post oxidation anneal)

▪ Most popular approach (~75% use it for MOSFET production)

▪ POA is key for high mobility to drive out C residues and saturate dangling bonds at interface

▪ High N concentrations at the SiC/SiO2 interface are desirable for high channel mobility

▪ Low N tailing into the oxide improves the oxide leakage

▪ POA with NO shows best mobility and oxide reliability results (N2O is little worse)

▪ High temperature oxidations showed improved Dit and channel mobility [10, 11]

▪ Annealing in N2 at high temperature (1400°C) improves interface but degrades the oxide reliability [12, 13]

▪ High temperature annealing in low O2 concentration in Ar removes carbon from interface [14]

▪ Deposited SiO2 + POA

▪ Many looked into this approach (about 25% us it for MOSFET production)

▪ Also for deposited oxides POA is required and crucial

▪ Recent work from Toshiba showed good results with a densification annealing in O2 at 900°C for 1h prior to the actual POA in N2 at 1300°C for 1h [15]

▪ Other approaches (R&D stage):

▪ POCl3 annealing showed good mobilities, but issues with Vth shifts and minor oxide reliability

▪ High-K dielectrics with wide bandgaps, like Al2O3 gained attention and could improve to the dielectric breakdown behavior, but electrical data are so far not state of the art [16]


Benefit of NO Post Oxidation Anneal

▪ High temperature nitric oxide annealing at temperatures > 1100 °C for:

▪ Reduction of the Dit

▪ Removal of carbon from SiO2 / SiC interface

▪ Lower Dit increases the channel mobility


[9] John Rozen; Tailoring Oxide/Silicon Carbide

Interfaces: NO Annealing and Beyond, INTECH open

science / open minds

[9]


SiC Oxidation and POA Process Windows


Requested oxidation and POA conditions for R&D & production:

▪ Dry oxidation: 800°C – 1500°C

▪ NO, N2O anneal: 1150°C – 1350°C

▪ Ar, N2 anneal: 1300°C – 1500°C

▪ Wet oxidation (optional): 800°C – 900°C

▪ In-situ Chlorine cleaning is beneficial to remove surface contamination from process parts

▪ Solid safety concept is mandatory!


ccccccccf

Trench Oxidation of 4H SiCProcess: Oxidation + NO/N2 POA at ~1350°C

top corner bottom corner

trench sidewall backside oxide

57 nm (at Si-face)

11

3 n

m (

at s

idew

all)

114 nm (at C-face)

54 nm (at Si-face)



Face dependency of the SiO2 growth rate

decreases and conformality increases

with temperature

At 1500°C the SiO2 growth rate on Si- &

C-face are almost the same

Increasing

temperature

High Temperature improves Oxide Conformalityfor Trench Gate MOSFET

0

50

100

150

200

250

300

350

0 10 20 30 40 50 60 70

Oxi

de

Thic

knes

s [n

m]

Oxidation Time [min]

4H-SiC (Si-Phase / Frontside)

1500°C

1380°C

1350°C

1300°C

1250°C

1200°C

1100°C

4H-SiC (Si-Face / Frontside)

0

50

100

150

200

250

300

350

0 10 20 30 40 50 60 70

Oxi

de

Thic

knes

s [n

m]


4H-SiC (C-Phase / Backside)1500°C

1380°C

1350°C

1300°C

1250°C

1200°C

1100°C

4H-SiC (C-Face / Backside)



0,00

1,00

2,00

3,00

4,00

5,00

6,00

7,00

0 10 20 30 40 50 60 70

Rat

io T

ox

(C-/

Si-F

ace)


4H-SiC (Si-Face / C-Face)

1100°C

1200°C

1250°C

1300°C

1350°C

1380°C

1500°C

At 1500°C the SiO2 growth rate on Si- & C-faces are almost equal

Incre

asin

g T

em

pe

ratu

re

Si / C Face Growth Ratio vs. Oxidation Temperature

4H-SiC (C-Face / Si-Face)



Activation Energies for Oxidation of Si and C Face

▪ Si-face has higher activation energy Ea compared to C-face

“Thermal Oxidation of Silicon Carbide (SiC) –Experimentally Observed Facts“, Sanjeev Kumar Gupta and Jamil Akhtar Central Electronics Engineering Research Institute (CEERI)/ Council of Scientific and Industrial Research (CSIR)

▪ At ~1600°C the oxidation rates on Si- and C-face are equal.

▪ This is also the case for any other SiC face with Ea ≤ Ea(Si)



Si vs. SiC Uniformity Comparison

Dry oxidation at 1380°C, 30min in 100% O2, 890 mbar

150 mm Si wafer

tox,mean: 236.81 nm

Univ: 0.13 %

Max-Min: 1.56 nm

150 mm SiC wafer

tox,mean: 102.48 nm

Univ: 0.27 %

Max-Min: 1.08 nm

Contour lines: 0.5 %


Tox uniformity on SiC usually worse than on Si because:

▪ Tox smaller unif. % higher

▪ Partly transparent Different heat deposition

▪ Inhomogeneous N doping▪ Higher temperature at areas

with higher doping

▪ Higher oxidation rates at areas with higher doping

▪ Typical specification for SiC:WIW, WTW, RTR < 1.5% (1s)


MOSCAP & MOSFET el. DataProcess: Oxidation + NO POA

▪ State of the art el. data:

▪ Low Dit(in low E12 cm-2)

▪ Mobility > 30 cm2/Vs

▪ Low mobile charges

▪ Ebd > 9.5 MV/cm

Activator_Oxidator_2017.07.14.pptx Confidential

HF C-V (100kHz)：EOT ~50 nm

HI-LO C-V

HF forward-reverse sweep

I-V

30


c.OXIDTOR150



Conclusions

▪ The future for SiC and GaN WBG semiconductors is seen very bright and after many years of R&D and small volume production, the business starts to ramp up driven by new volume applications, like electrical vehicles (EV) and others

▪ For SiC this was enabled by tremendous improvements in:

▪ Wafer / eqi quality

▪ Optimization of implantation and annealing processes

▪ MOS interface annealing

▪ Ohmic contact formation (especially p-contact)

▪ But of course open points remain and offer a large range of opportunities for future R&D in device design and fabrication technology

▪ Centrotherm as market leader for SiC annealing and oxidation furnaces is committed to support your SiC business with production proven equipment and with “Know How” partnership


centrotherm international AG

Württemberger Str. 31

89143 Blaubeuren

Germany

Tel +49 7344 918-0

Fax +49 7344 918-8388

www.centrotherm.de

Thank you for your attention!

For more, visit our booth in hall

A4 booth #669


References

▪ [1] Capano, M.A., Ryu, S., Cooper, J.A. Jr., et al. (1999) Surface roughening in ion implanted 4H-silicon carbide. J. Electron. Mater., 28, 214

▪ [2] Handy, E.M., Rao, M.V., Jones, K.A. et al. (1999) Effectiveness of AlN encapsulant in annealing ion-implanted. SiC. J. Appl. Phys., 86, 746.

▪ [3] Negoro, Y., Katsumoto, K., Kimoto, T. and Matsunami, H. (2004) Electronic behaviors of high-dose phosphorus-ion implanted 4H–SiC (0001). J. Appl. Phys., 96, 224.

▪ [4] M. Rambach, A.j. Bauer and H. Ryssel Electrical and topographical characterization of aluminum implanted layers in 4H silicon carbide. Phys. stat. sol. (b) 245, No. 7, 1315–1326 (2008) / DOI 10.1002/pssb.200743510

▪ [5] R. Hattori1, T. Watanabe1, T. Mitani2, H. Sumitani1 and T. Oomori1. Crystalline Recovery after Activation Annealing of Al Implanted 4H-SiC. Materials Science Forum Vols. 600-603 (2009) pp 585-590.

▪ [6] R. Nipoti et al, Al implanted 4H-SiC: improved electrical activation and ohmic contacts, Science Forum, proceeding of ECSCRM2012 (2012)

▪ [7] H.M. Ayed, R. Nipoti, A. Hallén and B.G. Svensson Isothermal Treatment Effects on the Carbon Vacancy in 4H Silicon Carbide. Materials Science Forum Vols 821-823 (2015) pp 351-354

▪ [8] H.M. Ayed, R. Nipoti, A. Hallén and B.G. Svensson Controlling the Carbon Vacancy Concentration in 4H-SiC Subjected to High Temperature Treatment. Materials Science Forum 1662-9752, Vol. 858, pp 414-417


References

▪ [9] N. Chandra, V. Sharma, G.Y. Chung, D.K. Schroder Four-point probe characterization of 4H silicon carbide. Solid-State Electronics 64 (2011) 73–77

▪ [10] S. M. Thomas, Y. K. Sharma, M. A. Crouch, C. A. Fisher, A. Perez-Toma, M. R. Jennings and P. A. Mawby Enhanced Field Effect Mobility on 4H-SiC by Oxidation at 1500◦C. J. Electron Device Society, Volume 2, NO. 5, September 2014

▪ [11] T. Hosoi, D. Nagai, M. Sometani, T. Shimura, M. Takei and H. Watanabe Ultra high temperature oxidation of 4H SiC(0001) and impact of cooling process on SiO2/SiC interface properties. Materials Science Forum 1661-9760, Vol. 897, pp 323-326

▪ [12] A. Chanthaphan, T. Hosoi, T. Shimura, and H. Watanabe Study of SiO2/4H-SiC interface nitridation by post-oxidation annealing in pure nitrogen gas. AIP Advances 5 (2015) 097134

▪ [13] A. Chanthaphan, Y. Cheng, T. Hosoi, T. Shimura, and H. Watanabe, Materials Science Forum 858 (2016) 627

▪ [14] T. Kobayashi, K. Tachiki, K. Ito, Y. Matsushita, T. Kimoto Reduction of interface state density in SiC (0001) MOS structures by very-low-oxygen-partial-pressure annealing. ECSCRM 2018, TU.01a.05

▪ [15] S. Asaba, T. Ito, S. Fukatsu, Y. Nakabayashi, T. Shimizu, M. Furukawa, T. Suzuki and R. Iijima Interface Reaction in the High-temperature N2 Annealing Process for Gate Insulator on SiC with High-Mobility and High-Reliability. ECSCRM 2018, TU01a.01 invited

▪ [16] S.S. Suvanama, M. Usmana, D. Martinc, M.G. Yazdia, M. Linnarssona, A. Tempezd, M. Götelida, A. Halléna Improved interface and electrical properties of atomic layer deposited Al2O3/4H-SiC. Applied Surface Science 433 (2018) 108–115

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SiC Activation and Oxidation Technology and related Production … · 2018-11-16 · SiC Activation and Oxidation Technology and related Production Tools Patrick Schmid, Senior Manager