At a SEMICON West press conference yes-

terday, SEMI released its Mid-year Forecast.

Worldwide sales of new semicon-

ductor manufacturing equipment

are projected to increase 19.8

percent to total $49.4 billion in

2017, marking the first time that

the semiconductor equipment

market has exceeded the market

high of $47.7 billion set in 2000.

In 2018, 7.7 percent growth is

expected, resulting in another

record-breaking year — totaling

$53.2 billion for the global semi-

conductor equipment market.

“It’s really an exciting time for the industry

in terms of technology, the growth in infor-

mation and data and it’s all going to require

semiconductors to enable that growth,” said

JULY 12, 2017

MOSCONE CENTER | SAN FRANCISCO, CALIFORNIA

WEDNESDAYSHOW DAILYSHOW DAILYSHOW DAILY9:05 am – 9:20 amSpecial Guest: James. C. MorganJim talks about his new book, Applied WisdomYerba Buena Theater

9:35 am – 10:05 amBig Data in Autonomous DrivingKatherine S. Winter, IntelYerba Buena Theater

10:30 am – 12:30 pmEnabling the IoTInnovative Technologies to Advance the Connected WorldMeet the Expert Theater, Moscone West

12:30 am –2:00 pmSmart Automotive 1The Future of Smart & Connected Self-driving CarsMoscone North, TechXPOT North

2:00 pm – 3:00 pmExecutive PanelMeeting the Challenges of the 4th Industrial Revolution along the Microelectronics Supply ChainYerba Buena Theater

2:00 pm – 5:00 pmAdvanced Packaging Technologies Enabling Advanced ApplicationsMoscone West, TechXPOT West

3:00 pm – 4:30 pmSmart ManufacturingMachine learning in design, inspection, process modeling and decision makingMeet the Expert Theater, Moscone West

continued on p. 3

DON’T MISS

Keynote speakers Terry Higashi of Tokyo

Electron Ltd. and Tom Caulfield of Global-

Foundries took the stage at the Yerba Buena

Theater Tuesday morning to predict major

changes in the goals and

operations of the semi-

conductor industry.

In many ways, 2017

has been marked by

intense interest in the capabilities of neural

networks and other forms of artificial intelli-

gence (AI). Higashi, now a corporate director

at TEL, predicted that AI and virtual reality

are among the applications that will propel

demand for semiconductors “almost without

limit.” Neuromorphic processors, the veteran

TEL executive said, “are one of the promising

devices to enhance human creativity. They

will be improved step by step, just as logic and

memory devices were improved.”

Looking toward a future in which AI and

human skills combine to resolve problems,

Higashi predicted that today’s Von Neumann-

continued on p 3

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based architectures and neuromorphic device

will complement each other. “Artificial intel-

ligence solutions will be proposed, and the

challenges and problems will be solved by sci-

entists and engineers. The combination of Von

Neumann and neuromorphic computing gets

us closer to true intelligence,” he said.

AI also will play a role in enhancing the

immersive experiences promised by virtual

reality, experiences which visionaries have

predicted but which thus far mankind “has

never fully experienced.”

Higashi said that by combining VR and AI,

“we can attain a suspension of disbelief, and

simply enjoy the experience. If we can provide

the technologies, consumers will experience

excitement and a form of happiness.”

Caulfield, the general manager of the Malta

fab near Albany, agreed with Higashi’s assess-

ment that that the semiconductor industry is

seeing “new buds” that will bloom into large

semiconductor markets.

However, Caulfield said that to achieve any-

thing like the rate of technological progress

seen over the first half century of the semicon-

ductor industry, companies and customers will

have to take collaboration to new levels. And

he offered the collaboration between Global-

Foundries and AMD as an example.

“Collaboration, potentially, is the biggest

thing we need to do. We need strategic partner-

ships, and not only among semiconductor manu-

facturers but also with equipment suppliers.”

At its Malta fab, GlobalFoundries builds

all of AMD’s leading-edge discrete graphics

engines and CPUs. “The AMD and Global-

Foundries engineering teams are so embedded

with each other, one can hardly tell” which

company an engineer works for, he said.

Noting the resurgence of AMD, Caul-

field said “we are all proud to be part of that

partnership.” And he pointed to another col-

laboration, between Samsung and Global-

Foundries, which allows customers to take

the same 14nm design and choose whether to

manufacture it at Samsung’s Austin fab or at

Dan Tracy, senior director, IR&S at SEMI.

If you average the forecasts of various ana-

lysts, it comes out to about 12% growth for

the year. “It’s a very good growth year for the

industry,” Tracy said. “In January, the consen-

sus was about 5% growth for the year and with

the improvement in the market and the firmer

pricing for memory we see an increase in the

outlook for the market.”

The SEMI Mid-year Forecast predicts wa-

fer processing equipment is anticipated to

increase 21.7 percent in 2017 to total $39.8

billion. The other front-end segment, which

consists of fab facilities equipment, wafer

manufacturing, and mask/reticle equipment,

will increase 25.6 percent to total $2.3 billion.

The assembly and packaging

equipment segment is projected

to grow by 12.8 percent to $3.4

billion in 2017 while semiconduc-

tor test equipment is forecast to

increase by 6.4 percent, to a total

of $3.9 billion this year.

“Based on the May outlook,

we are looking at a

record year in terms

of tracking equipment spending.

This is for new equipment, used

equipment, and spending related

to the facility that installed the

equipment. It will

be about a $49 bil-

lion market this year.

Next year, it’s going

to grow to $54 bil-

lion, so we have two years in a row

of back to back record spending,”

Tracy said.

In 2017, South Korea will be

the largest equipment market for

the first time. After maintaining

the top spot for five years, Taiwan will place

second, while China will come in third. All re-

gions tracked will experience growth, with the

exception of Rest of World (primarily South-

east Asia). South Korea will lead in growth

with 68.7 percent, followed by Europe at 58.6

percent, and North America at 16.3 percent.

SEMI forecasts that in 2018,

equipment sales in China will

climb the most, 61.4 percent, to

a total of $11.0 billion, following

5.9 percent growth in 2017. In

2018, South Korea, Taiwan, and

China are forecast to remain the

top three markets, with South

Korea maintaining the top spot

to total $13.4 billion. China is

forecasted to become the second

largest market at $11.0 billion, while equip-

ment sales to Taiwan are expected to reach

$10.9 billion.

Equipment Forecast continued from p. 1

Copy AI and Collaboration continued from p. 1

continued on p 14

Dan Tracy, senior director, IR&S, SEMI

Show Daily StaffPublished by Solid State Technology,

an Extension Media company.

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MOSCONE CENTER | SF, CA

4

In order to increase device performance, the

semiconductor industry has slowly been imple-

menting many new materials. From the 1960s

through the 1990s, only a handful of materials

were used, most notably silicon, silicon oxide,

silicon nitride and aluminum. Soon, by 2020,

more than 40 different materials will be in

high-volume production, including more “ex-

otic” materials such as hafnium, ruthenium,

zirconium, strontium, complex III-Vs (such as

InGaAs), cobalt and SiC.

These new materials create a variety of

challenges with regard to process integration

(understanding material interface issues, ad-

hesion, stress, cross-contamination, etc.). But

they also create new challenges when it comes

to material handling.

“As we go through technology node advance-

ments, people are looking at the potential of dif-

ferent materials on the wafer,” notes Clint Haris,

Senior Vice President and General Manager of

the Microcontamination Control Division at

Entegris (Billerica, MA). “They’re looking at

different chemicals that are required to clean

those materials to reduce defects and improve

their operational yield, and what we’re increas-

ingly seeing is that fabs are concerned with the

fact that contamination can be introduced in the

fluid stream anywhere in that long process flow.”

Haris said that part of their mission at Ente-

gris is to make sure that the entire supply chain

– from the development of a chemistry at the

supplier to its use on a wafer in a fab – is work-

ing in harmony, particularly with regard to any

materials that might “touch” the chemicals.

“Not only do you want to filter and purify things

throughout the whole fluid flow,” he said, “but

you want to have that last filtration right before

the fluid touches the surface of the wafer.”

The goal of filtration is, of course, to remove

contaminants and particles before they reach

the wafer, but the exact purity required can

be a moving target. “Today we’re seeing a lot

of these materials and liquids, which have a

parts per trillion purity level, but there’s a de-

sire to move to parts per quadrillion,” Haris

said. That’s the equivalent of one drop in all the

water that flows over Niagra Falls in one day.

In addition to the filtration challenge of

achieving that level, there’s the question of do

the analytical tools exist to actually measure

contaminants at that level. The answer – not

yet. “It’s actually a real issue where some of the

metrology tools cannot meet our customers’

needs at those levels, and so one of the things

that we’ve done is we’ve developed some tech-

niques internally to enhance the capability

of metrology,” Haris said. “We also work on

how we prepare our samples so you can detect

contamination at those levels.” Because that

level of detection is so difficult -- in some cases

impossible – Haris said fabs are increasingly

putting additional filters at the process tool

and at the dispense nozzle to “protect against

the unknown.”

Earlier this year, Entegris introduced Pura-

sol™, a first-of-its-kind solvent purifier that

removes a wide variety of metal microcon-

taminants found in organic solvents used in

ultraclean chemical manufacturing processes.

Using tailored membrane technology, the puri-

fier can efficiently remove both dissolved and

colloidal metal contaminants from a wide vari-

ety of ultra-pure, polar and non-polar solvents.

“One of the main things that our customers are

seeing is a concern with metal contamination in

the photo process that can result in particular

defects (see Figure), such as bridge defects,”

Haris explained. Increasingly, fabs are moving

from just filtration (removing particles) to puri-

fication (removing ions and metals), he added.

Entegris also recently acquired W. L. Gore

& Associates’ water and chemical filtration

product line for microelectronics applications.

“This is a Teflon-based product line, which is

used in ultrapure water filtration for semicon-

ductor fabs, but it’s also a product that we’re

selling into some of the fine chemical purifica-

tion markets for some of the chemistries that

are brought into the fabs,” Haris said. “We

are focused on new product development and

M&A to enhance our capability to support our

customers as they overcome these contamina-

tion challenges.”

New Materials, New Challenges

Illustration of metal contamination inducing defects on lithography process.

We are focused on new product

development and M&A to enhance our capability to support

our customers as they overcome

these contamination challenges

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MOSCONE CENTER | SF, CA

6

In the annual reports of every

semiconductor manufacturers

is a section focused on sustain-

ability. “They will all have various

goals and targets associated with

two areas: reducing their carbon

footprint – that’s carbon dioxide

and energy use – and generally

reducing all their utilities con-

sumptions, be that fuel gas, wa-

ter and all those sorts of things,”

said Mike Czerniak, Environmen-

tal Solutions Business Develop-

ment Manager at Edwards. “That

makes great environmental sense,

but great financial sense as well

because you’re not paying such

big water bills and power bills.”

In recent years, energy con-

sumption has decreased due to

several innovations that have

helped to improve the energy ef-

ficiency of process tools and sub-

fab equipment, but an increase in

the number of processes and the

growing complexity of processing

at the current node has resulted

in a spike in energy consumption

in the fab. Approximately 43% of

the energy consumed in the fab is

due to the processing equipment

and, of this, 20% is vacuum and

abatement (8% overall).

Adding to the interest in re-

ducing semiconductor manufac-

turing’s carbon footprint is the

increasing use of electronics in the

automotive sector, where car mak-

ers are also trying to reduce their

overall carbon footprint. “There

are three footprints associated

with a car – there’s the manufac-

turing footprint, the product use

footprint and the end-of-life foot-

print,” Czerniak said. Cars are be-

coming more efficient with semi-

autonomous and autonomous

driving, and there’s increased use

of electric cars. Cars are also light-

er in weight through increased use

of aluminum and composite ma-

terials. “All of those things

add together to reduce the

product use footprint. That

means the manufacturing

footprint gets that much

more of a fraction of the

whole lifecycle footprint, so

it becomes of more interest

to the auto makers,” Czer-

niak said.

Czerniak will be pre-

senting today at 2:30 pm

on “Minimizing CF4 Emis-

sions in ICs and Aluminum

in the Automotive Supply

Chain” as part of the ses-

sion on SMART Manufac-

turing: Virtual reality, sus-

tainability, and 3D-model

control.

At the moment, about

30% of the value of the com-

ponents that go into a car,

are electronics. That’s due

to double within the next

10-15 years, particularly

once cars become fully au-

tonomous and have an all

electric drive train. “That’s

why people are getting so much

more interested in reducing their

overall manufacturing footprint

in semiconductor manufacture.”

Enter a new standard from

SEMI, E175, which defines ener-

gy saving modes. That, combined

with a new EtherCAT signaling

standard, can help fabs save en-

ergy and other gas/utility costs

when the tool is not processing and

with no impact on subsequent wa-

fer processing. “Idle mode or sleep

mode savings are such an easy, low

hanging fruit. Why wouldn’t you

want to do it?” asks Czerniak.

EtherCAT, based on industrial

Ethernet, provides high-speed

control and monitoring. It is

the communication standard of

choice for the latest semiconduc-

tor tool controllers to connect to

sensors and actuators around the

tool, including vacuum and abate-

ment systems.

SEMI E175 defines how pro-

cess tools communicate with sub-

fab equipment, such as vacuum

pumps and gas abatement sys-

tems, to reduce utility consump-

tion at times when wafers are not

being processed by the tool, and

returning to full performance

when the tool is again required to

process wafers. It builds on SEMI

E167, which defines communica-

tion between the fab host/WIP

controller and the process tools

for the purpose of utility saving.

Now that the tools are avail-

able, Czerniak said there’s a lot

of work to do. “Green modes in

general are still quite embryonic.

We’re in the evangelistic stage,”

he said. “There have been one or

two pioneering companies in this

area that have already made strides

in this direction, but it’s far from

being universally accepted. This

is why we’re trying to push this

method so hard at the moment.”

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MOSCONE CENTER | SF, CA

8

Global industry R&D hub IMEC defines the

“IMEC 7nm-Node” (I7N) for finFETs to have

56 nm Contacted Gate Pitch (CGP) with 40

nm Metal Pitch (MP), and such critical mask

layers can be patterned with a single exposure

of 0.33 N.A. EUVL as provided by the ASML

NXE:3400B tool. To reach IMEC 3-nm-Node

(I3N) patterning targets of ~40 CGP and ~24

MP, either double exposure of 0.33 N.A. EUVL

would be needed or else single-exposure of 0.55

N.A. EUVL as promised by the next-generation

ASML tool. All variations of EUVL require novel

photoresists and anti-reflective coatings (ARC)

to be able to achieve the desired patterning.

The Figure shows that IMEC has led tremen-

dous progress on the photoresists, with best

resolution in a single 0.33 N.A. EUVL expo-

sure of 13nm half-pitch (HP) line arrays. The

most important parameter for the photoresist

is the sensitivity target of 20 mJ/cm2, but at

that dosage the best materials seen today have

unacceptably high line-width roughness of >5

nm three-sigma. “If you’re talking about lines

of 16nm width, for 3-sigma you want to be less

than 3 nm line-width-roughness,” ex-

plained Steegan during the 2017 IMEC

Technology Forum. “Smoothing tech-

niques are post-develop technologies

that basically reduce line-width-rough-

ness. We are working with many partners, and

all are making progress in reducing line-width

roughness though post-develop techniques.”

The Figure also

shows that IMEC

has been working

with vacuum depo-

sition companies on

atomic-layer deposi-

tion (ALD) or chemi-

cal-vapor deposition

(CVD) processes to

ideally take off 2 nm

of sidewall rough-

ness. Plasma energy

may be capacitively-

or inductively-cou-

pled to a vacuum chamber to allow for either

PEALD or PECVD processing. Such precise

atomic-scale processing may be composed of

“dep/etch” sequences of one/few atomic layer

depositions followed by light plasma etching

such that the nominal line-width would not

necessarily change. However, this approach

necessitates that the wafer leave the lithogra-

phy track and move to a separate vacuum-tool.

To save on cost and time, LWR smoothing

may be accomplished to some extent today in

the litho track by specialized spin-on materials.

Companies that supply lithography resolution

extension (EXT) materials such as spin-on

hard masks (SOHM) and anti-reflective coat-

ings (ARC) have looked at ways spin-on ma-

terials can improve the LWR of post-devel-

oped resist lines. This can be combined with

“shrink” materials that add controlled thick-

nesses to sidewalls of holes, or with “trim”

materials that subtract controlled thicknesses

from the sidewalls of lines. Generally, some

manner of complex chemical engi-

neering is used to create a film that

either forms or breaks bonds when

thermally driven by a bake step, and

after image transfer to underlying

SOHM layers the shrink/trim mate-

rial is typically stripped in a solvent

such as propylene glycol methyl ether

acetate (PGMEA).

EUVL photoresists may be based

on metal-oxide nano-particles, in-

stead of on extensions to the Chem-

ically-Amplified Resist (CAR) for-

mulations that have been mainstays

of ArF/ArFi lithography for decades.

Inpria Corp.—the 10-year-old-start-

up supported by industry—has ulti-

mately developed a tin-oxide family

of blends that are shown as the Non-

Chemically-Amplified Resist (NCAR)

in the Figure. NCAR metal-oxide

EUV Patterning Materials EvolvingBY ED KORCZYNSKI

Top-down SEM images of the best achieved EUVL resolutions using 0.33 N.A. stepper and Chemically-Amplified Resist (CAR) or metal-oxide Non-Chemically-Amplified Resist (NCAR) formulations, along with post-development “smoothing” technologies to improve the Line-Width Roughness (LWR) to meet target specifications. (Source: IMEC)

continued on p. 18

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MOSCONE CENTER | SF, CA

10

When it comes to defects and con-

tamination in the semiconductor

manufacturing industry, most

people tend to think of small, sub-

nm defects at the transistor level.

As important as those are, there

are plenty of things that can go

wrong and be seen at the macro

level. Scratches, fingerprints, hot

spots, spin defects, edge chips,

poly haze, missing patterns, etc.

are usually visible with the naked

eye, perhaps aided by a green light

or a microscope.

Fabs often do manual visual in-

spections, but it tends to be fairly

random, only sampling a few wa-

fers at a time. “You put some wa-

fers on the screen, and you look

sporadically at five, ten points on

a few of the wafers,” notes Reiner

Fenske, founder, CEO and presi-

dent of Microtronic (Hawthorne,

NY). “If you find something, typi-

cally it’s very difficult to feed that

information forward. You might

take a picture, but then where

does that picture go?” It’s also

difficult to compare defects, such

as scratches, with previously seen

defects. “How many scratches

did you have last week? Does that

scratch look like the one that you

had last night?” Reiner asks.

An automated

macro inspection tool

— such as the newly

released Micro-

tronic EAGLEview

5, which will be run-

ning wafers at North

Hall Booth #5467 at

Semicon West this

week — solves those

problems, without

requiring any recipes

and quickly scanning

every wafer in the cassette, noting

and logging various defects. The

EAGLEview 5 represents a big up-

grade over the company’s previous

offering. “There’s really a dramatic

difference in terms of defect de-

tection, defect resolution, defect

sensitivity, and there’s no hit to

throughput, so we’re still looking at

3,000 wafers a day, which is

incredibly fast,” said Mike

LaTorraca, Microtronic’s

Chief Marketing Officer.

Errol Akomer, Applica-

tions Director at Micro-

tronic, adds that in addition

to the higher resolution,

it’s a much cleaner signal.

“The signal-to- noise ratio

is much better — there’s

a 5X improvement in that

as well,” he said. Inter-

nally developed software

algorithms also results in

less nuisance defects and

increased defect detection.

With these new capa-

bilities, LaTorraca said

they’ve created a bridge

between micro and macro,

and manual and automat-

ed. “We can take manual

microscope images and

put them into the same

software that runs on Ea-

gleView. We can start to

integrate defect informa-

tion and the actual defect

images from the manual micro-

scope world into our tool, and that

gives the fab owners a much more

comprehensive view, to make bet-

ter decisions,” he said.

EAGLEview 5 is equipped with

advanced imaging technology,

analytical software, robotics and

a 4-cassette multi-size (100mm-

300mm) wafer platform. EAG-

LEview ProcessGuard Client Soft-

ware provides defect visualization,

digital guard-banding, wafer ran-

domization/slot positional analy-

sis, together with integration with

manual microscopes for fab-wide

defect tracking and reporting.

Every wafer is automatically

OCR read, imaged, 100% inspect-

ed and stored for any step through-

out the manufacturing process.

EAGLEview 5 acts as a hub

for defect management across the

fab by integrating manual micro-

scope inspection, high resolution

EAGLEview wafer images. EAG-

LEview 5 replaces legacy manual/

micro wafer inspection by auto-

mating and standardizing wafer

inspection processes. Blindly

sampling 5 sites on a wafer is no

longer needed. The newly devel-

oped ProcessGuard microscope

interface software records micro

defect classifications. This cou-

pled with on-board commonality

analysis allows root cause to be

Bridging the Macro and Micro World of DefectsBY PETE SINGER

EAGLEview 5

continued on p. 15

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12

EV Group (EVG), located in Booth #7211 in the

West Hall, unveiled its next-generation laser

debonding solution (Figure 1), which enables

high-throughput, low-cost-of-ownership (CoO)

room-temperature debonding for ultra-thin and

stacked fan-out packages. Designed as a mod-

ule for integration in the company’s benchmark

EVG®850 DB automated debonding system, the

new laser debonding solution incorporates a

solid-state laser and proprietary beam-shaping

optics to enable optimized, force-free debond-

ing. Featuring both low-temperature debonding

and high-temperature- processing

stability, EVG’s new laser debond-

ing solution is ideal not only for

fan-out wafer-level packaging

(FoWLP), but also for processing

compound semiconductors and

power devices. System orders

have already been placed for the

new solution.

“The semiconductor industry

and its touch points grow more

diverse by the day. The Internet

of Things, automotive advance-

ments, communications and vir-

tual needs are now all being driven

by the advancements in this indus-

try,” stated Paul Lindner, executive

technology director at EV Group.

“Many of these devel-

opments are now tak-

ing place at the pack-

aging level, where the

need for greater device functionality and smaller

form factors has led to more complex packages,

stacked packages, systems in package, as well as

high-performance packages. EVG’s temporary

bonding and debonding solutions, including our

latest-generation laser debonding module, play

a crucial role in enabling wafer thinning to ad-

dress the smaller form factors required for these

new packaging architectures and applications.”

FoWLP offers the ability to enable very thin

devices and system integration with increased

performance, functionality and design flexibil-

ity for consumer and mobile handheld devices.

According to market research and strategy con-

sulting firm Yole Développement, FoWLP is

growing at a compound annual growth rate

(CAGR) of 36 percent from 2017 to 2022, reach-

ing more than $3 billion in 2022. The extreme

thinness of device wafers in FoWLP is driving

the need for temporary carrier technologies.

In the case of the “chip last/redistribution lay-

er (RDL) first” FoWLP approach, the entire

package flow occurs on a glass wafer or glass

panel. Since the RDL layer is immediately on

top of the debonding layer, low force is essen-

tial to minimizing risk of yield loss during the

debonding process. Laser debonding is ideally

suited to remove the glass handler after RDL

formation due to its use of minimum force. In

addition, the temperature stability of the laser

debonding process allows it to easily remove

bonding adhesive materials without impacting

other materials in the package. The result is

high process yield and low risk of device wafer

breakage.

EVG’s new laser debonding solution incor-

porates a solid-state UV laser and a proprietary

optical setup (Figure 2) that shapes the Gauss-

ian beam profile of the laser into a “quasi top

hat” beam profile. By employing this optical

setup, EVG achieves a highly reproducible beam

with minimal heat introduced to the device wa-

fer and excellent spatial control. This enables

tighter process control, which coupled with the

high pulse repetition rate of the laser, the ability

to conduct laser treatment and wafer separa-

tion in a single chamber to minimize handling

time, and the ability to scan across the surface

of a fixed wafer, leads to a well-controlled, high-

throughput and low-temperature

debonding process. Figure 3 shows

how the laser set-up compares to

other types of configurations.

Low laser maintenance, high

carrier wafer lifetime, the ability to

support fully automated handling

on film frame, oversized carriers

or free standing/unsupported thin

wafers, and optimized footprint

layout, all round out the system’s

low CoO advantages. In the tra-

dition of EVG’s open platform

approach to wafer bonding, the

laser debonding solution is also

compatible with a wide variety of

commercially available adhesive

materials.

Low-Temperature Laser Debonding for FOWLP

Figure 1. EV Group’s next-generation laser debonding solution combines a solid-state UV laser, proprietary optics, modular plat-form and universal debonding process to create a high- throughput, low cost-of-ownership debonding process optimized for fan-out wafer-level packaging (FOWLP), compound semiconductor and power device applications. Shown here is the EVG®850 DB automated laser debonding system. Figure 2. Close up of EVG’s next-generation

laser debonding module with solid-state UV laser scanning across the surface of a fixed wafer.

Figure 3. Comparison of three laser types (from left to right): advanced UV laser solution from EVG; (2) conventional solid-state laser; and (3) excimer laser. The blue crisscross areas in the beam profile image indicate the radiant exposure used for the laser debond process while the red area indicates energy that cannot be used for debonding. The EVG laser debonding solution combines the best fea-tures of both other laser types.

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14

MOSCONE CENTER | SF, CA

Malta. “Customers can run pho-

tomasks in Austin or in Malta,

New York and have the product

look the same,” he said.

Government RoleIn such a collaboration-rich busi-

ness environment, governments

also have a role to play, Caulfield

said.

“Public-private investments

must imply a return to govern-

ments as well as to companies.

Otherwise, they send the

wrong message.” By invest-

ing several billion dollars in

the Malta fab, GlobalFound-

ries and the state of New

York put to work the well-

educated young people who

otherwise would have left the

state in search of technology

jobs. When Malta began op-

erations, only 20 percent of

the staff were educated in New

York. Now, fully half of the work-

force has benefited from a New

York education.

“We were exporting talent.

Now, the workforce has great

opportunity within the state,” he

said.

Both Higashi and Caulfield

said major challenges face the in-

dustry. Higashi noted that innova-

tion will be required to keep flash

memory costs under control. “As

data is captured by sensors and

is transferred via the appropri-

ate networks and stored in data

centers, demand for NAND will

be high. We must make huge ef-

forts to reduce the overall cost, as

the semiconductor industry is ex-

pected to provide enough volumes

to support the Internet of Things.”

Caulfield said the performance

of logic transistors has struggled

to keep pace, even as density in-

creases have continued. When

the industry moved from 28nm to

14nm technologies, performance

increased by fully 50 percent.

But from 14nm to 10nm, speeds

improved by about 18 percent,

making shrinks primarily a cost

improvement.

With the industry now focused

on brining 7nm logic to the mar-

ket, the question arises whether

5nm CMOS will provide enough

performance to justify that node.

While the jury on technology scal-

ing is still out, Caulfield said the

industry may have to move to gate

all around (GAA) structures, or

to non-silicon channel materials,

in order to gain the kinds of per-

formance improvements that cus-

tomers expect from a new node.

Higashi said systems must get

faster. “Real-time processing is

crucial in the cyber world. And

with robotic hands, there should

be no delays in physical opera-

tions.”

“Memory, logic, and sensing

make it possible for AI systems to

solve problems much faster than

a team of geniuses. We are now

in a new era, one of super inte-

gration. In addition to improved

specialty devices – based on logic,

memory, and sensors – we must

take these separate devices and

put them together into fully inte-

grated systems. It is time to make

a pizza, with some of the best in-

gredients,” he said.

Copy AI and Collaboration continued from p. 3

Tom Caulfield, GlobalFoundries

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James C. Morgan will be a special guest pre-

senter during the Semicon West keynote session

this morning at the Yerba Buena Center. Mor-

gan is a director emeritus and past president of

SEMI, and was one of SEMI’s early support-

ers, back when the organization consisted of

an “executive secretary, two clerks, and eight

board members.”

Jim will be discussing the semiconductor

equipment industry and introducing his autobi-

ography and book of business insights, Applied

Wisdom: Bad News Is Good News and Other

Insights That Can Help Anyone Be a Better

Manager. Dan Hutcheson, CEO of VLSI Re-

search, says that he would “definitely put this

book on the shelf next to Andy Grove’s Only the

Paranoid Survive.”

Complimentary copies of the ebook will

be made available to all attendees of this

year’s Semicon West

conference.

Jim Morgan will

also be signing pa-

perback books at

booth 5630 in the North Hall at Moscone

Center on June 11 and 12.

James C. Morgan ran Applied Materials for

nearly three decades—one of the longest ten-

ures of any Fortune 500 CEO. The company

was near-bankrupt when he joined; when he

retired as CEO in 2003, Applied was a multi-

billion dollar global leader with more than

15,000 employees.

More recently he and his wife Becky found-

ed the Northern Sierra Partnership, which fos-

ters collaboration among conservation orga-

nizations in order to preserve and restore one

of the world’s great mountain ranges.

James C. Morgan Unveils Applied Wisdom

determined for micro defects and breathes

new life into existing microscope inspec-

tion strategies. EAGLEview was original-

ly designed to be comparable to naked eye

1x green light inspection. EAGLEview 5

shifts the line between a macro green light

inspection and microscope inspection.

“You can put all the micro defects into

our database in the same ways you did the

macro, so you classify your macro defects

and you classify all your micro defects,”

Fenske explained. “Now you have a record

of what, where, how many, and because

we collect all the history of where the lot

went to, which tools it went through, we

can then use that information to do com-

monality studies to figure out which tool

caused the problem. With the microscope,

there hasn’t been that type of integration,

so we can now take all of those legacy

things everyone needs to use and actu-

ally give them a new life.”

Macro and Micro continued from p. 10

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With the 7nm technology node in the devel-

opment phase and the 5nm node moving into

development, transistor scaling gets ever more

complex. On top of that, the performance ben-

efits gained at the front-end-of-line (i.e., the

transistors) can easily be undone if the back-

end-of-line can’t come along. BEOL process-

ing involves the creation of stacked layers of

Cu wires that electrically interconnect the

transistors in the chip. Today, high-end logic

chips easily have 12 to 15 levels of Cu wires.

With each technology node, this Cu wiring

scheme becomes more complex, mainly be-

cause there are more transistors to connect

with an ever tighter pitch. Shrinking dimen-

sions also means the wires have a reduced

cross-sectional area, which drives up

the resistance-capacitance product

(RC) of the interconnect system. And

this results in strongly increasing sig-

nal delay. The RC delay issues started

a few nodes ago, and the problems are

becoming worse. For example, a delay

of more than 30% is expected when

moving from the 10nm to the 7nm node.

The current BEOL flowCu-based dual damascene has been the work-

horse process flow for interconnects since its

introduction in the mid 1990s. A simple dual

damascene flow starts with the deposition of a

low-k dielectric material on a structure. These

low-k films are designed to reduce the capaci-

tance and the delay in the ICs. In a next step,

this dielectric layer is covered with an oxide

and a resist, and vias and trenches are formed

using lithography and etch steps. These vias

connect one metal layer with the layer above or

below. Then, a metallic barrier layer is added to

prevent Cu atoms from migrating into the low-k

materials. The barrier layers are deposited with

physical vapor deposition, using materials such

as tantalum and tantalum nitride, and subse-

quently coated by a Cu seed barrier. In a final

step, this structure is electroplated by Cu in a

chemical mechanical polishing (CMP) step.

A 5nm technology full dual damascene moduleThe semiconductor industry is hugely in fa-

vor of extending the current dual damascene

technology as long as possible before moving

to a new process. And this starts with incre-

mental changes to the current technology,

which should suffice for further scaling to at

least the 5nm technology node. Researchers at

imec have demonstrated a full dual damascene

module for the 5nm technology node. At this

node, the BEOL process becomes extremely

complex, and interconnects are designed at

very tight pitches. For example, a 50% area

scaling in logic and 60% scaling of an SRAM

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cell from 7nm to 5nm results in a gate pitch at

around 42nm and an intermediate first rout-

ing metal at 32nm pitch (or 16nm half pitch,

which is half the distance between identical

features). In these BEOL layers, trenches are

created which are then filled with metal in a

final metallization step. In order to create elec-

trically functional lines, perpendicular block

layers to the trenches

are added, where

metal traces are not

formed. One of the

many challenges to

scaling the intercon-

nects relates to the

patterning options.

Patterning these

tight pitch layers is

no longer possible

by using single im-

mersion lithography

and direct etch steps.

Only multi-pattern-

ing – which is known to be very costly and

complex – is possible either by immersion or

by EUV or by a combination of immersion and

EUV exposures to form a single metal layer. At

IITC, imec showed a full integration flow using

multi-patterning, which enables the patterning

of tight-pitch metal-cut (the blocks), and ef-

fectively scaling the trench critical dimension

to 12nm at 16nm half pitch. The researchers

also looked at the reliability, for example at

electromigration issues caused by the move-

ment of atoms in the interconnect wires. They

demonstrated the ability of imec’s Cu metalli-

zation scheme at 16nm critical dimension with

extendibility to 12nm width, and investigated

full ruthenium (Ru) metallization as copper

replacement.

Scaling the BEOL beyond the 5nm node...For the technology nodes below the 5nm, the

team of imec is investigating a plethora of op-

tions and comparing their merits. Options

include new materials for conductors and di-

electrics, barrier layers, vias, and new ways to

deposit them; innovative BEOL architectures

for making 2.5D/3D structures; new pattern-

ing schemes; co-optimization of system and

technology, etc.

For example, to achieve manufacturable

Figure 1. Tight pitch copper lines embedded into a low-k material. The metal cuts (or blocks) were enabled by a tone-inversion flow.

continued on p 18

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processes and at the same time control the RC

delay, scaling boosters, such as fully self-aligned

vias, are increasingly being used. Via alignment

is a critical step in the BEOL process, as it de-

fines the contact area between subsequent inter-

connect levels. Any misalignment impacts both

resistance and reliability. Imec’s team has shown

the necessity of using a fully self-aligned via to

achieve overlay specifications, and proposed a

process flow for 12nm half pitch structures.

Also, self-assembled monolayers (SAMs)

open routes to new dielectric and conductor

schemes. SAMs composed of sub-1nm organic

chains and terminated with desired functional

groups can help engineering thin-film dielec-

tric and metal interfaces, and can strongly

inhibit interfacial diffusion. The use of SAMs

has been a topic of research for the past ten

years. Imec has now moved this promising

concept from lab to fab, and combined SAMs

with a barrier/liner/metallization scheme on

a full wafer. The researchers investigated the

implications on the performance and scaling

ability of this process flow, and demonstrated

a ~18% reduction in the RC of 22nm half-pitch

dual damascene interconnects, due to a better

interface and thinner barrier.

For conventional BEOL metallization, a bar-

rier layer is coated by a Cu seed barrier, and this

structure is electroplated with low-resistive Cu,

which acts as the conductor. But when moving

to sub-10nm interconnects, the resistivity of Cu

continues to increase. At the same time, the dif-

fusion barrier – which is highly resistive and dif-

ficult to scale – is taking up more space, thereby

increasing the overall resistance of the barrier/

Cu structure. Therefore, alternative metals are

being investigated that could possibly serve as

a replacement for Cu and do not require a dif-

fusion barrier. Among the potential candidates,

such as Co, Ni, Mo, etc., platinum-group metals,

especially ruthenium

(Ru), have shown

great promise due to

their low bulk resis-

tivity and resistance

to oxidation. They

also have a high melt-

ing point which can

result in better elec-

tromigration behav-

ior. Imec has realized

Ru nanowires with

58nm2 cross section

area. The nanowires

exhibit low resistiv-

ity and robust wafer-

level reliability. For

example, a very high

current carrying ca-

pacity with fusing currents as high as 720MA/

cm2 was demonstrated.

At the 2017 IITC conference, this author was

invited to take part in a panel discussion, orga-

nized by Applied Materials, to discuss the latest

developments in metallization at single-digit

nodes, the challenges and bottlenecks arising

at these very small dimensions, and new ap-

plication-driven requirements. Distinguished

speakers from the technical field reviewed vi-

able solutions for extending the current tech-

nology and alternative options were discussed.

From the discussion it is clear that the biggest

immediate benefit can be found in the area of

conductors – both from the material side as well

as design. Indeed, it is driving the replacement

of copper at specific metallization levels. Other

avenues – such as dielectric innovations, func-

tionality in the BEOL or 2D materials – remain

interesting options for the R&D pipeline.

As an option that is further out, spin wave

propagation in conductors is an alternative sig-

naling to traditional electron based propagation.

Adding additional functionality in the BEOLIn the future, more and more technology op-

tions may get dictated by the requirements

of systems or even applications. This could

result in a separate technology for e.g. high-

performance computing, low-power mobile

communication, chips for use in medical ap-

plications, or dedicated chips for IoT sensors.

Along the same lines, imec is investigating the

benefits of introducing additional functionality

in the BEOL.

More specifically, imec is evaluating the

possibility of integrating thin-film organic

transistors – with typically low-leakage level

– into the BEOL interconnect circuitry of Si

FinFETs. The potential advantages of fabri-

cating them together are mainly a reduced

power consumption and improved area sav-

ing. A variety of circuits can fully utilize the

benefits of this hybrid processing, including

portable applications, eDRAM, displays and

FPGA applications. As a concrete example,

imec researchers are currently merging imec’s

expertise in BEOL technologies and in thin-

film-based flat panel displays, thereby opening

opportunities for new applications.

RC Delay continued from p. 17

Figure 2. Time dependent behavior of Ru nanowires under thermoelec-tric stress.

resists show similar LWR at similar exposure

doses to CARs. However, the metal-oxides in

the NCAR can often replace SOHM materials,

saving cost and complexity in the resist stack.

IMEC’s work on EUVL with ASML step-

pers leads to the belief that the source power

will increase to allow throughput to rise from

today’s ~100 wph to ~120 wph by the end of

this year. However, those throughputs assume

20mJ/cm2 resist-speed, and masks may re-

quire 30 mJ/cm2 target exposures even with

post-develop smoothing steps.

[DISCLOSURE: Ed Korczynski is also Sr.

Technology Analyst with TECHCET Group, and

author of the “Critical Materials Report: Photo-

resists and Extensions and Ancillaries 2017”.]

EUV Patterning continued from p. 8

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