IEEE TRANSACTIONS ON COMPUTERS, NOVEMBER 1970

REFERENCES

[1] E. F. Moore, "Gedanken-experiments of sequential machines," inAutomata Studies. Princeton, N. J.: Princeton University Press,1956, pp. 129-153.

[2] S. Seshu and D. N. Freeman, "The diagnosis of asynchronous sequen-tial switching systems," IRE Trans. Electronic Computers, vol. EC-1 1,pp. 459-465, August 1962.

[3] A. Gill, Introduction to the Theory of Finite-State Machines. NewYork: McGraw-Hill, 1962.

[4] K. Kinoshita, "Some considerations on the fault diagnosis of sequen-tial circuits,"' Electron. Comm. Jap., vol. 46, pp. 20-28, September1963.

[5] F. C. Hennie, "Fault detecting experiments for sequential circuit,"

Proc. 5th Ann. Symp. on Switching Circuit Theory and Logical Design(Princeton, N. J.), October 1964.

[6] T. Fukui and Y. Nakanishi, "Determination of input sequence forfault detection in finite state system," Electron. Comm. Jap., vol. 50,pp. 174-182, October 1967.

[7] S. Murakami, K. Kinoshita, and H. Ozaki, "Computer experimentsfor finding fault detecting sequences of sequential circuits," Electron.Comm. Jap., vol. 50, pp. 191-201, October 1967.

[8] Z. Kohavi and P. Lavallee, "Design of sequential machines withfault-detection capabilities," IEEE Trans. Electronic Computers, vol.EC-16, pp. 473-484, August 1967.

[9] S. Murakami, K. Kinoshita, and H. Ozaki, "Synthesis of sequentialmachines with systematic fault detection sequences," J. Inst. Electron.Comm., Eng. Jap., October 1968.

Short Notes.

Use of a Macro Processor in Logical Design

B. J. AUSTIN

Abstract-This note describes a technique of logical design usinga standard machine-language assembler as the basic tool. An analogyis drawn between the assembly of logic modules by an engineer andthe compiling of instructions by a programmer. This analogy can beused to enable an assembler to generate directly, a wiring list, as wellas computing such design parameters as the cost, and the power andspace requirements of the design. The designer works in a macro

language, where a macro may stand for a logic module or a self-con-tained logic circuit within a module. This language contains the essen-

tial logical design information divorced from irrelevant trivia such as

the allocation of logical functions to modules and the arrangement ofmodules in a mounting panel. Thus, optimization of the wiring layoutcan be conveniently carried out after the logical design is complete.The expression of the design in macro form also allows checkout ofthe logic by simulation.

Index Terms-Analogy between program assembly and logic mod-ule interconnection, analogy between signal names used in logicaldesign and symbolic location names used in programming, computer-assisted logic design, derivation of wiring lists and other logical de-sign information by a machine language assembler, interconnectionof logic modules using program assembly techniques.

I. INTRODUCTIONThis note describes a logical design technique used in

the development of an interface between a Control Data3600 and a Digital Equipment PDP-8. The Division ofComputing Research ofthe C.S.I.R.O. has, since June 1966,been operating a 3600 under a locally developed time-shar-ing monitor DAD (Drums and Displays) [1], [2]. Thename DAD is intended to highlight the essential features ofthe system, viz., a large-drum backing store and a multi-access subsystem, based on CRT character displays. The

Manuscript received August 22, 1968. The work described here was

carried out at the Division of Computing Research, C.S.I.R.O, CanberraCity, A.C.T., Australia.

The author is with the Information Sciences Laboratory, Research andDevelopment Center, General Electric Company, Schenectady, N. Y.

displays allow a number of users to access the computer inparallel with normal batch processing, but do not providetruly remote computer use because the particular modelsused (Control Data DD210) must be situated withinabout 200 feet of the computer. This virtually restricts thedisplays to being in the same building as the 3600. There-fore, it was decided to add teleprinter terminals to the sys-tem, both as a means of providing truly remote access, andas an experiment in operating teleprinter and CRT displayterminals in the same time-sharing system. It was furtherdecided to connect the teleprinters to the 3600 via a smallcomputer, viz., a Digital Equipment PDP-8. This smallcomputer takes the place of a normal peripheral controller,but performs in addition the function of making the tele-printers appear to the 3600 as nearly as possible identicalto the displays, so that the existing 3600 software could beused. The PDP-8, by means ofa resident program, simulatesthe properties of a peripheral controller that are normallyprovided as fixed electronics. Thus, the PDP-8 can be viewedas a general-purpose 3600-compatible controller thathappens to be specialized for the particular job of multi-plexing teleprinter stations. This approach gives greatflexibility, but was adopted principally because the authorwas more a programmer than an engineer.

Similarly, the design of the 3600 to PDP-8 interface wastackled from a programmer's point ofview rather than froman engineer's. It is the basic thesis of this note that a reason-able and fruitful analogy exists between the wiring togetherof logical modules by an engineer and the assembling ofmachine instructions by a programmer. This similarity hasbeen pointed out before [3], but with the emphasis re-versed. Many systems of automated logical design havebeen developed [4]-[6], but it has proved possible to carryout a design task using a standard machine language as-sembler as the main tool, with very little additional pro-gramming. The assembler used was the Control Data

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IEEE TRANSACTIONS ON COMPUTERS, NOVEMBER 1970

COMPASS system, and it appears to possess many of theattributes necessary for logical design work.

II. USING AN ASSEMBLER TO CONSTRUCT A WIRING LIST

The design technique to be described assumes that logicmodules are available and provide the usual AND, OR, etc.,functions. These modules plug into a mounting panel,and connections to the modules are made by means ofa ma-trix of pins (e.g., wire-wrap or taper). One of the tasks ofthe design engineer is to produce a list of all connections tobe made within this matrix of pins. In itself, this is no diffi-cult task, but the complexity and apparent lack of order ofthe wiring list make the intrusion of errors easy, and auto-mation of the process attractive.We must first set up a correspondence between a two-

dimensional matrix of pins and a one dimensional array.

This correspondence will depend on the geometry of theproblem in hand. In the present case, there were 32 columnsof 36 pins, each column being one double height moduleor two single height modules. We now consider pinp of thecolumn c to be equivalent to element (p+ 36c) of a one-

dimensional array. This array will, in fact, turn out to be a

program assembled into core in the normal manner.

We must next establish the concept of a "signal name."Every pin is considered to be carrying some electrical signal,and this signal is referred to by a name. Signal names are

unique, so that all pins carrying a signal with the same namemust be joined together by wires, and pins joined by wiresmust carry signals of the same name. For the moment, we

will assume that one pin of all those carrying the same nameis the "source" of the signal, and all other pins are "destina-tions." (See Section IV for a discussion of this restriction.)Symbolic names allowed by the COMPASS assembler are

limited to eight characters. The names of signals were

chosen with as much mnemonic significance and ease ofpronunciation as possible [6], and also with a conventionthat indicated the assertion value of the signal.

In programming terms, a signal name is equated to a

symbolic location name. In fact, the design process involvesassembly of a program in which locations that definesymbolic names are equated with pins that are signalsources, and in which locations that contain references to a

symbolic name are destinations of that signal. The list ofsymbolic names and all their references is identical to thewiring list giving interconnections within the matrix ofpins.The setting-up of such a program is facilitated by the

macro processor to be found in a standard assembler suchas COMPASS. It is necessary to write one macro for eachmodule type. (See below for a generalization in which a

macro is defined for each logic circuit in a module consistingof several self-contained submodules.) The formal param-eters are the pin numbers. They appear within the bodyof the macro in order, and in such a way that exactly one

word of code is assembled for each pin, thus maintainingthe previously established correspondence between core

locations and pins. Where the pin is a signal source, itscorresponding formal parameter appears in the locationfield, and thus defines an address to be used wherever a

reference to the same name occurs. Where the pin uses asignal produced elsewhere, the formal parameter appearsin an address field, thereby constituting a reference to asignal name defined elsewhere.The logical design now becomes a matter ofwriting down

a sequence of macro calls using signal names as actualparameters. The macro calls are, in fact, a sort of algebraand form a convenient vehicle for thought, i.e., the designeris working fairly closely to Boolean algebra. The order ofthe cards containing the macro calls is in direct corre-spondence to the final layout of modules, but may be al-tered to affect optimization of the wiring without affectingthe logic of the design (see Section III). The macros are as-sembled by coMPAss into an array that corresponds to thematrix of pins, and the symbol cross-reference table pro-duced by the assembler is the wiring list. Thus a standardassembler can be used to perform logical design.The macro defining each module can also allow for the

situation in which modules contain unused pins or wheredifferent module sizes exist. In relation to the particulargeometry of the case in point, it was necessary to cater forsingle modules (18 pins) and double modules (36 pins).This was accomplished by making the macro correspondingto a single module "pad" its starting location to a multipleof 18, and by making a double module pad to a multiple of36. Hence, unused pins at the end of the preceding moduledid not need to be counted by the designer.Modules frequently contain a number ofidentical circuits

(submodules), e.g., one module may consist of a number ofidentical inverters. The macro system can be extended toallow the designer to assign a particular logical function toone of these circuits, without irrevocably restricting it to aspecific module or to a specific circuit within the module.Thus, at a later stage of the design, convenience or wiringoptimization may indicate a preferable distribution of cir-cuits within modules of the same type. This is achieved bydefining a macro for one of the circuits making up themodule. Generally, the pins are arranged within eachidentical submodule in the same way, and therefore thesame macro can be used for each. Hence, the designer candefine the logic structure in terms of submodules, and atonly the final stage of setting up ofthe wiring list need he fixthe arrangement to particular modules.The production of the actual wiring list was achieved as

follows. The coMPAss assembler outputs at the end of theprogram listing a symbol reference table, which gives a listof all symbolic location names used, the actual location towhich they correspond, and the location at which referencesto them appear. This constitutes the network of pins thatmust be interconnected. It is not, however, a list ofthe actualwires required for the interconnections, nor is it in a formthat is convenient for the person doing the wiring. A simpleFORTRAN program was therefore written to process the refer-ence table further and to output the wiring information ineasy to read form. It was also possible to produce an inde-pendent (graphical) representation of the same data forcheckout purposes. Note that it is unnecessary at this stageto retain the distinction between a signal's source and its

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SHORT NOTES

Geometrical information, cost, powerrequirements

Power connections.

End of definition.

D= -XOR(E,F)ZZZXOR1 is simulation routine.

Input 1

Input 2

TABLE IIPARrrY TMm DESIGN

XORXOR1 TREEO1,BITO1,BIT11XOR1 TREE23,B1T21,BIT31 TREE is the parity output.XOR1 TREE45,BIT41,BIT51

XORXORI TREE67,BIT61,BIT7 1| BITOI,BITII,... BITIOI,XOR1 TREE89,BIT81,BIT91 BIT 111 are the 12 input bits.XOR1 TREE1O,BIT1I1,BIT111XOR1 TREE,TREE1,TREE4510

XORXOR1 TREE0167,TREEO1,TREE67XOR1 TREE2389,TREE23,TREE89XOR1 TREE4510,TREE45,TREE1OXOR1 TREE1,TREE0167,TREE2389

destinations. Thus, the source address should be sorted intothe list of destinations before the wiring determination isperformed. At this point, the exact geometry of the matrixof pins and the technique used for joining them will decidehow the list of connections to be made can best be set out.It is also possible to generate information in a form suitablefor operating an automatic wiring machine.

In order to clarify the technique as described so far, a sim-ple example is given here. The example is a parity generationtree constructed from exclusive OR modules. Such a paritytree is in fact, a part of the 3600 to PDP-8 interface, but theexample has been simplified to remove some irrelevancieswhile retaining the essence of the method. Imagine that thematrix ofpins is 16 deep, and that all modules have 16 pins,lettered from A to P. (This means that an address expressedin octal can be decoded into module position and pin num-ber without difficulty.) The exclusive OR module consists offour identical submodules (see Table I). Thus, each physicalmodule is represented by one use of the macro XOR, whichdefines in particular the power supply pins, followed by upto four uses ofthe macro XOR1, which defines the inputs andoutput for one exclusive OR circuit. The parity tree design isgiven in Table II, and the resulting symbol reference tablein Table III. The networks corresponding to each signal arepresented in a more easily read form in Table IV.

TABLE IIISYmBoL REFERNCE TABLE

... GROUND 00002 00022 00042 The power supply busses

... MINUS15 00001 00021 00041 have sources outside the

... PLUSIO 00000 00020 00040 example. The input bitsP00034 TREE are not shown.P00003 TREEO1 00044P00043 TREE0167 00055P00031 TREEIO 00053P00054 TREEI 00035P00006 TREE23 00047P00046 TREE2389 00056P00011 TREE45 00052P00051 TREE4510 00036P00023 TREE67 00045P00026 TREE89 00050

TABLE IVTRANSLATED REERENCE TABLE

GROUND OC IC 2C ...

MINUS15 OB lB 2B ...

PLUSIO OA IA 2A ...

TREE iMTREEO1 OD 2ETREE0167 2D 2NTREEIO 1J 2LTREEI IN 2MTREE23 OG 2HTREE2389 2G 20TREE45 OJ 2KTREE4510 10 2JTREE67 ID 2FTREE89 IG 21

III. FuRTHiER DESIGN CONSIDERPATIoNs TREATEDBY AN ASSEMBLER

So far, the discussion has centered around the productionof a wiring list. There are other important factors, not theleast being the logical validity of the design. Unfortunately,it is not possible to say that a machine-language assemblerwill check this, but it is possible to include in the macro-

structure references to subroutines that define the logicalproperties of modules, i.e., the logical connection betweenits inputs and outputs. Hence, the program assembled toobtain the wiring list can also be used in a simulation check-out of the design.

In the present application, a particularly simple-mindedsimulation sufficed. Since the electronics could be assumedto be far faster than the changes to its inputs and since therewere only a very small number ofmonostables, a time-inde-pendent simulation was satisfactory, viz., after a change tothe inputs to the system, all signals were recomputed re-

peatedly until stability was achieved. The simulation pro-

gram used a CRT character display to allow inputs to be setup and the resulting outputs observed.

It is possible to derive other design benefits from theassembly process. The COMPASS assembler allows elementaryarithmetic operations to be performed on symbolic quan-

tities at compile time. It is therefore simple to compute thetotal cost of the modules used in a trial design by includingin the macro defining each module a statement that incre-

TABLE IMACRO DEFINMONS

XOR MACROPAD

+ 00+ 00+ 00

ENDM

XOR1 MACROD 22

+ 02+ 02

ENDM

35,1,36

PLUSIOMINUS15GROUND

D,E,FZZ7XOR1

EF

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IEEE TRANSACTIONS ON COMPUTERS, NOVEMBER 1970

ments a cost symbol appropriately. Hence, every use of themodule will be counted in the total cost. By a similar tech-nique, other design factors can be computed by the as-sembler, and are available to the designer at all stages of hiswork. It was possible to keep a check on the space require-ments of the design, the current drawn from two supplies,and the number of modules and submodules of every typeused, as well as the cost. The designer can also check thatno signal is overloaded (though again it requires more thanjust the assembler). The macro defining each module cancontain the fan-in/fan-out information, and a simple pro-gram can examine the compiled code (i.e., the wiring array)to check the current drain on every signal source. Referenceto Table I will show how information regarding all theseproperties is included in the macro specifications.A logical design expressed in macro form is an ideal basis

for wiring optimization, since it contains the logical in-formation in a manner divorced from geometrical or me-chanical details. That is, the set of macros contains a mini-mum of final decisions regarding the disposition of logicalfunctions among modules of the same type and the layoutof modules, but allows ready production of wiring lists oftrial module arrangements. Just what optimization of wir-ing may mean will depend on the particular problem, espe-cially on the exact geometry of the matrix of pins and thetechnique used in connecting them, but it will usually in-volve shortening total wire length, or particular wire lengths.Generally, the optimum is not sought after or is not defined,and the designer is content with one of many nearly opti-mum solutions. The design technique described in this paperfacilitates finding such a solution in two ways. Firstly, thelogical design is performed without regard to the considera-tions ofoptimization, and can be checked out by simulation.Secondly, optimization of the finalized design can beachieved without disturbing the logical properties of thedesign, since optimizing only alters the order of the macrostatements and not their content. Put in another way, theset of macros defines a logical design which is invariantunder rearrangement of the order of the macro calls, and itis very easy to rearrange the macros and test the optimiza-tion of the resulting layout.

In the present case, it was decided to regard reduction inthe length of connections between columns of pins as bene-ficial, and set up a matrix showing the number of wires con-necting each pair of columns. Optimization then involvedmaking this matrix as nearly as possible diagonal. This wasachieved by altering the order of the macro calls manually,but there seems to be no reason why a computer programshould not be able to do nearly as well. The use of anassembler as a design vehicle seems to be an aid to optimiza-tion of wiring whether the process is fully automated or in-volves an "engineer-in-the-loop."

IV. DISCUSSIONIt is not to be denied that the problem to which the tech-

nique described in this note was applied was a small one,though not so small as to be trivial. The question of ex-

tendability to larger applications therefore needs discussion.An assembly of the design took a few minutes of 3600 time.Hence, a problem an order of magnitude larger might take30 minutes, and might be regarded as the largest practicable.One should note, however, that the techniques of programsegmentation could apply equally well to logical design.Thus, a programmer divides his problem into units heavilyconnected within themselves, but with comparatively fewinterconnections between units. The task of compiling unitsis given to an assembler, and the task of putting units to-gether is that of a linking loader. Similarly, an engineercould divide his logical design problem into suitable units,where each unit is of a tractable size and performs a singlefunction or a set of related functions, and could treat eachunit separately for the purposes of design and wiringoptimization. The units could then be joined by a linkingloader and tested by simulation. It seems, therefore, that thetechnique of logical design using an assembler is not limitedby size. Indeed, it would be fair to say that the logicalstructures built by software teams are, at the least, com-parable in size with those constructed by their hardwarecolleagues, and therefore it would seem feasible to adopt anassembler technique for hardware development.The technique, as described so far, has a stringent restric-

tion, viz., a signal must have only one source. This prohibitssuch methods as oRing by connecting collectors together,since this would be deemed by the assembler as a doublydefined signal. In the present application, this turned out tobe not very serious, and it was preferred to gain the con-comitant advantages, viz., automatic notification ofa signalname used inadvertently more than once with differentmeanings and of signal names used but never given a source,and use of the reference table directly as a wiring list. It ispossible to consider a system that uses an assembly tech-nique, but allows more than one source of the same name.Instead of using the assembler to deal with references to thesignal name, it could be made to assemble the actual namesinto core. A simple program could then process the as-sembled code, check for signal names for which no sourceis defined, and generate a wiring list. Indeed, this approachis not much different in difficulty of implementation or easeof use to the system already set out, and it would allow asignal to be the OR of several sources. The remarks of Sec-tion III would still hold, since the logical design would becontained in a set ofmacro calls. Design parameters such ascost could be computed in the same way, and optimizationof the wiring could still be carried out by reordering themacro calls. Hence, the assembler technique is not restrictedto the case of one source per signal name.

ACKNOWLEDGMENTThe author would like to acknowledge the assistance of

C. D. Gilbert throughout the project.

REFERENCES[1] B. J. Austin, T. S. Holden, and R. H. Hudson, "DAD, the C.S.I.R.O.

operating system," Comm. ACM, vol. 10, pp. 575-583, September1967.

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SHORT NOTES

[2] B. J. Austin and T. S. Holden, "Recent developments in the DAD Sys-tem," Aust. Computer J., vol. 1, pp. 201-207, May 1969.

[3] W. L. Gordon, "Data processing techniques in design automation,"1960 Eastern Joint Computer Conf., pp. 205-209.

[4] C. W. Peck, "Wire list package," Decuscope, vol. 6, no. 5, p. 11, 1967.[5] R. J. Plano, "Wire," Decuscope, vol. 6, no. 5, p. 39-E, 1967.[6] A. H. Leiner, A. Weinberger, C. Coleman, and H. Loberman, "Using

digital computers in the design and maintenance of new computers,"IRE Trans. Electronic Computers, vol. EC-10, pp. 680-690, December1961.

The Synthesis of Multivalued Cellular Cascades

MICHAEL YOELI

Abstract-This note discusses multivalued cellular cascades, i.e.,one-dimensional arrays of multivalued two-input, one-output com-

binational cells. It is shown that a large class of multivalued combina-tional switching functions can be realized by such a cascade.

Index Terms-Cascaded switching networks, cellular logic, com-binational logic, multivalued logic, switching network synthesis.

I. STATEMENT OF MAIN RESULTSFollowing [1], we define a multivalued cellular cascade or

generalized Maitra cascade of length n as a one-dimensionalarray of n two-input, one-output combinational cells, as

shown in Fig. 1. We assume all the vertical cell inputs to beM-valued, M >2, and all the horizontal leads to be N-valued, N> 2. In general, we assume such an M x Ncascade to be redundant [2], i.e., the same external inputmay be connected to the (vertical) input leads of severalcells. In particular, we denote the external inputs byx1,

- -

, Xm, m< n, and assume that xl(i), 1 < A(i)< m, is con-

nected to the vertical input of cell Hi.Now let X= {O, 1, ,M-1}, Y= {0, 1, N-1}. The

ith cell (i= 1, .., n) of the cascade of Fig. 1 produces a

function Hi: YxXX- Y These n cell functions Hl, , H,together with the boundary condition yo, completely de-termine the output function F:Xm-+ Y of the cascade.Namely, for every (x1, , xm)eXm we have

y= HR(yi-1, xA(i)) 1 < i < n

and

F(x Xm) = Yn- (1)

Setting M =N= 2, we obtain the extensively studiedbinary redundant Maitra cascade. It is well known [2] thatthere exist Boolean functions not realizable by such a

cascade. On the other hand, it is shown in [3] that forM=2, N=4, every function F: Xm-+ Y, m> 1, is realizableas the output function of a redundant M x N cascade. Theresult of [3] was extended by Elspas and Stone [4] to thecase M=2, N=2r, r> 1 (which corresponds, in an evident

Manuscript received February 6, 1968; revised February 13, 1970.This research has been sponsored in part by the Air Force Office of Scien-tific Research through the European Office of Aerospace Research, OAR,U. S. Air Force, under Grant AF EOAR 67-21.

The author is with the Department of Computer Science, Technion-Israel Institute of Technology, Haifa, Israel.

Inputs

Baw,dory~ ~ ~~l Ynn.Condition Yo Hi H2.H H'' Xwoutput

Cell Cell 2 Cell n

Fig. 1. The Maitra cascade.

way, to binary r-rail cascades). The synthesis of ternarycascades (M=N = 3) is covered in [5]. Whereas in [3] and[5] simple group-theoretic arguments are used, an impor-tant feature of [4] is the introduction of methods from thetheory of linear sequential switching networks.The results of [4] are easily extended to the case whereM= 2s(s.1), and M= 2r(r> 1), since a 2S x 2r cascade canevidently be obtained from a 2 x 2' cascade by lumpingtogether appropriate cells.

In this note we use the techniques of [4] and [5] to obtainTheorem 1. For M= 2s(s2 1), N= 2r(r> 1) these resultscoincide with the above mentioned extension of [4] and,for M =N = 3, Theorem 1 coincides with Theorem 1 of [5 ].

Theorem 1: Let M>2, and N=2r q, where N>2, r#1,and q is odd. Then every function F: Xm--+ Y, m> 1, isrealizable as the output function of a redundant MxNcascade of length km, where k1=1 and km=M(km + 1),m>1.

II. GENERALIZED OUTPUT FUNCTIONSThe derivation of Theorem 1 makes use of the concept of

generalized output functions [1]. In Section I we havedefined the output function F:Xm Y of the cascade shownin Fig. 1 for some fixed boundary condition yo. Alterna-tively, we may consider yo as an additional externalinput. The corresponding generalized output functionF:YxXm-*Y is then defined by (1) and F(yo, xl, Xm)=Yn, for all yo0 Y and all (x1, *., xm)EXm.We shall first consider the case M. 2 and N= pr, where p

is a prime number, r> 1, and N>2. Following [4] werepresent Y by the linear space V of all r-dimensional rowvectors over the Galois field GF(p). This representation ofY corresponds to the replacement of the single pr-valuedrails yi of Fig. 1 by r p-ary rails. We denote the resultingcascade as (M; p, r) cascade.We call a function F: V x Xm-+ V additive, if always

F(y0xi,.. IXm) = yo + F(O, x, ,xm)where yo E V and 0 is the zero vector of VWe then have the following lemma.Lemma 1: For X={O, 1, , M-1}, M>2, and V as

previously defined, every additive function F: V x Xm-+ V,m> 1, is realizable as the generalized output function of aredundant (M; p, r) cascade of length km, where km is definedas in Theorem 1.

Proof: The case m= 1 is trivial. Proceeding by induc-tion on m, we wish to show for m> 1, that F can be realizedas shown in Fig. 2, where F(yo, x1, , xm)=y with yoeV,ye V, and the Ci are (M; p, r) subcascades with additive

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