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A Cascade Multilevel Inverter Usinga Single DC Source

Zhong Du1, Leon M. Tolbert2,3, John N. Chiasson2, and Burak zpineci3

1Semiconductor Power Electronics CenterElectrical and Computer Engineering

North Carolina State UniversityRaleigh, NC 27606

zdu@ncsu.edu

2ECE DepartmentThe University of TennesseeKnoxville, TN 37996-2100

tolbert@utk.edu, chiasson@utk.edu

3Power Electronics and Electric Machinery Research Center

Oak Ridge National Laboratory, NTRC2360 Cherahala Boulevard

Knoxville, TN 37932tolbertlm@ornl.gov, ozpinecib@ornl.gov

Abstract A method is presented showing that a cascademultilevel inverter can be implemented using only a single DCpower source and capacitors. A standard cascade multilevelinverter requires n DC sources for 2n + 1 levels. Withoutrequiring transformers, the scheme proposed here allows the useof a single DC power source (e.g., a battery or a fuel cell stack)with the remaining n1 DC sources being capacitors. It is shown

that one can simultaneously maintain the DC voltage level of thecapacitors and choose a fundamental frequency switching patternto produce a nearly sinusoidal output.

Index Terms Multilevel Inverter, Fuel Cell

I. INT RODUCT ION

A cascade multilevel inverter is a power electronic devicebuilt to synthesize a desired AC voltage from several levels ofDC voltages. Such inverters have been the subject of researchin the last several years [1][2][3][4][5], where the DC levelswere considered to be identical in that all of them were either

batteries, solar cells, etc. In [6], a multilevel converter was

presented in which the two separate DC sources were thesecondaries of two transformers coupled to the utility ACpower. In contrast, in this paper, only one source is usedwithout the use of transformers. The interest here is interfacinga single DC power source with a cascade multilevel inverterwhere the other DC sources are capacitors. Currently, each

phase of a cascade multilevel inverter requires n DC sourcesfor2n+1 levels in applications that involve real power transfer.In this work, a scheme is proposed that allows the use of asingle DC power source (e.g., battery or fuel cell stack) with

the remaining n 1 DC sources being capacitors. It is shownthat one can simultaneously maintain the DC voltage level ofthe capacitors and choose a fundamental frequency switching

pattern to produce a nearly sinusoidal output.

II. MULTILEVEL INVERTE R ARCHITECTURE

To operate a cascade multilevel inverter using a single DCsource, it is proposed to use capacitors as the DC sources forall but the first source. Consider a simple cascade multilevelinverter with two H-bridges as shown in Fig. 1.

+

-

dccVv

21

=C+

-

1S

2S

3S

4S

1S 2S

3S

4S

1H

2H

2v

dcV1

v

v

n

i

DC

Power

Source

Fig. 1. Single-phase structure of a multilevel cascaded H-bridges inverter.

The DC source for the first H-bridge (H1) is a DC powersource with an output voltage of Vdc, while the DC source

4260-7803-9547-6/06/$20.00 2006 IEEE.

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for the second H-bridge (H2) is a capacitor voltage to beheld at Vdc/2. The output voltage of the first H-bridge isdenoted by v1 and the output of the second H-bridge isdenoted by v2 so that the output of this two DC sourcecascade multilevel inverter is v(t) = v1(t)+ v2(t). By openingand closing the switches of H1 appropriately, the outputvoltage v1 can be made equal to Vdc, 0, or Vdc whilethe output voltage of H2 can be made equal to Vdc/2, 0,

or Vdc/2 by opening and closing its switches appropriately.Therefore, the output voltage of the inverter can have thevalues 3Vdc/2,Vdc,Vdc/2, 0, Vdc/2, Vdc, 3Vdc/2, whichis seven levels and is illustrated in Fig. 2(a). Table I showshow a waveform can be generated using the topology of Fig.1.

1 2 3

dcV

23

2

dcV

dcV

21

dcV

21

dcV

dcV

23

1

2

3

1

2

3

dcV

dcV

2/dc

V

2/dc

V

2

1v

2v

1

(a)

(b)

2

2 3

1

2

dcV

dcV

2/dc

V

2/dc

V

2

1v

2v

1

(c)

2

1

2/

2/

32/

2/

2

Fig. 2. (a) Output waveform of an 7-level cascade multilevel inverter. (b)and (c) H-bridge voltages v1 and v2 which achieve the same output voltagewaveform v = v1 + v2.

TABLE I. OUTPUT VOLTAGES FOR A 7-LEVEL INVE RTER

v1 v2 v = v1 + v20 1 0 0 0

1 2 0 Vdc/2 Vdc/21 2 Vdc Vdc/2 Vdc/22 3 Vdc 0 Vdc

3 /2 Vdc Vdc/2 3Vdc/2

Fig. 2(b) shows how the waveform of Fig. 2(a) is generatedif, for 1 2, v1 = Vdc and v2 = Vdc/2 is chosen.Similarly, Fig. 2(c) shows how the waveform of Fig. 2(a) isgenerated if, for 1 2, v1 = 0 and v2 = Vdc/2is chosen. The fact that the output voltage level Vdc/2 can

be achieved in two different ways is exploited to keep thecapacitor voltage regulated. Specifically, one measures thecapacitor voltage vc and the inverter current i. Then, if vc 0, one sets v1 = Vdc and v2 = Vdc/2 andthe capacitor is being charged. Table II summarizes this casealong with the discharge case vc > Vdc/2.

TABLE II. CONTROLLER FORCAPACITOR VOLTAGE LEVELSystem State v1 v2 v = v1 + v2

vc < Vdc/2, i > 0 Vdc Vdc/2 Vdc/2vc < Vdc/2, i < 0 0 Vdc/2 Vdc/2vc > Vdc/2, i > 0 0 Vdc/2 Vdc/2vc > Vdc/2, i < 0 Vdc Vdc/2 Vdc/2

By choosing the nominal value of the capacitor voltage to beone half that of the DC power source, the nominal values of thelevels are equally spaced. However, this is not required. The

criteria required for this capacitor regulating scheme is that (1)the desired capacitor voltage is less than the DC power sourcevoltage, (2) the capacitance value is chosen large enough sothat the variation of its voltage around its nominal value issmall, and (3) the capacitor charging cycle is greater than thecapacitor discharge cycle.

III. SWITCHING ANGL ES

If the nominal capacitor voltage is chosen as Vdc/2, thenone can compute the switching angles 1, 2, and 3 as in [7].Following the development in [7] (see also [8]), the Fourierseries expansion of the (staircase) output voltage waveform ofthe multilevel inverter as shown in Fig. 2(a) is

V(t) =4

Vdc2 (1)

Xn=1,3,5,...

1

n

cos(n1) + cos(n2) + cos(n3)

sin(nt).

Ideally, given a desired fundamental voltage V1, one wantsto determine the switching angles 1, 2, and 3 so that (1)

becomes V(t) = V1 sin(t). In practice, one is left withtrying to do this approximately. For three-phase systems, thetriplen harmonics in each phase need not be canceled as theyautomatically cancel in the line-to-line voltages. In this casewhere there are 3 DC sources, the desire is to cancel the5th and 7th order harmonics as they tend to dominate thetotal harmonic distortion. The mathematical statement of these

conditions is then4

Vdc2

cos(1) + cos(2) + cos(3)

= V1

cos(51) + cos(52) + cos(53) = 0 (2)

cos(71) + cos(72) + cos(73) = 0.

This is a system of three transcendental equations in the threeunknowns 1, 2, and 3. There are many ways one can solvefor the angles (see, for example, [9], [10], and [11]). Here theapproach in [7] and [12] is used.

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IV. EXPERIMENTAL RESULTS

A three-phase wye-connected cascaded multilevel inverterusing 100 V, 70 A MOSFETs as the switching devices [13]was used to carry out the experiments. A power supply wasused as the DC power source with Vdc = 25 V and a 8mF capacitor was used as the second DC source. The real-time controller was implemented on an FPGA chip with an

8 sec time step where the switching angles as a functionof the modulation index were stored in a lookup table. Themultilevel converter was connected to a three phase inductionmotor whose nameplate data is 1/3 hp, 1.5 A, 1725 rpm and208 V (RMS line-to-line at 60 Hz).

With m , V1/

4

Vdc2

[see equation (2)], Fig. 3 shows

the inverter voltage waveforms of the three phases for m =1.32 and f = 60 Hz. (Note that the modulation index is m/swhere s is the number of DC sources, which in this experimentis s = 2).

0 0.005 0.01 0.015 0.02 0.025 0.03 0.03540

30

20

10

0

10

20

30

40Voltage v. time with m=1.32 and f = 60 Hz

Time in seconds

Phasevoltage

Fig. 3. Three-phase output waveforms of the seven-level multilevel inverter.

Note that the second level in Fig. 3 is constant at 25 Vbecause this level is due to only the power supply source withthe capacitor voltage not being used. However, the first leveland the third level both require using the capacitor voltage, andnote that they are not constant. In particular, note that the firstlevel varies considerably, but the capacitor voltage controller

pushes back in the right direction. The fact that the capacitorvoltage varies so much is due to the low value of capacitance

used (8 mF).Also, voltage spikes are seen in Fig. 3. These occur at thosetimes when both of the sources (power supply and capacitor)are being switched in or out simultaneously. This is due to thedifferences in dead time of the H-bridge switches as well asthe timing of turning the switches on and off not being exactlythe same between the two H-bridges.

The FFT plot of a line-line voltage waveform is shown inFig. 4. The 5th and 7th harmonics are not quite zero due tothe varying capacitor voltage.

0 500 1000 1500 2000 2500 30000

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1FFT of the normalized lineline voltage with m=1.32 and f=60

Frequency (Hz)

ak

/amax

5th 7th

Fig. 4. FFT of the line-line voltage form = 1.32 and f = 60 Hz.

Fig. 5 is the current in one of the phases of the inductionmachine, and its corresponding FFT is shown in Fig. 6.

0 0.005 0.01 0.015 0.02 0.025 0.03 0.035

0.8

0.6

0.4

0.2

0

0.2

0.4

0.6

0.8

Current

Time in seconds)

Current vs. time with m=1.32 and f = 60 Hz

Fig. 5. Phase current waveform with m = 1.32 and f = 60 Hz.

0 500 1000 1500 2000 2500 30000

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1Normalized Magnitude of Phase Current vs Frequency (m=1.32)

Frequency (Hz)

ak/a

max

5th 7th

Fig. 6. FFT of the phase current form = 1.32 and f = 60 Hz.

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V. 15-LEVEL INVE RTER

Consider now a 15-level inverter with three H-bridges asshown in Fig. 7. The corresponding waveform is shown inFig. 8.

DC

Power

Source

+

-

+

-

1S 2S

3S

4S

1S 2S

3S 4S

1H

2H

+

-

1S 2S

3S

4S

3H

dccVv

21

1=C2v

dcV

dccVv

41

2=C

1v

n

i

3vv

Fig. 7. Hardware architecture for a 15-level (3 DC sources) inverter.

1 2 3

23 /dc

V

dcV

2/dc

V

4/dc

V

4/3dc

V

4/7dc

V

4/5dc

V

4 5 6 7

2

23 /dc

V

dcV

2/dc

V

4/dcV

4/3dc

V

4/7dc

V

4/5dc

V

v

Fig. 8. Hardware architecture and output voltage waveform for a 15-levelinverter.

The DC source for the first H-bridge (H1) is a DC powersource with an output voltage of Vdc, the DC source for thesecond H-bridge (H2) is a capacitor voltage to be held at

Vdc/2, and the DC source for the third H-bridge (H3) isa second capacitor voltage held at Vdc/4. As in the 7-levelinverter, the capacitor voltages are chosen in this way so thatthe difference between levels is the same. However, this is notessential. The output voltages of each of the H-bridges aredenoted v1, v2, and v3, respectively, so the output voltage ofthe 15-level inverter is given by v(t) = v1(t) + v2(t) + v3(t).The possible ways in which the voltage waveform of Fig. 8(b)

can be achieved are given in Table III.TABLE III. OUTPUT VOLTAGES FOR A 15-LEVEL IN-

VERTER

v1 v2 v3 v1 + v2 + v30 1 0 0 0 0

1 2 0 Vdc/4 Vdc/41 2 0 Vdc/2 Vdc/4 Vdc/41 2 Vdc Vdc/2 Vdc/4 Vdc/42 3 0 Vdc/2 0 Vdc/22 3 Vdc Vdc/2 0 Vdc/23 4 0 Vdc/2 Vdc/4 3Vdc/43 4 Vdc 0 Vdc/4 3Vdc/43 4 Vdc Vdc/2 Vdc/4 3Vdc/44 5 Vdc 0 0 Vdc5 6 Vdc 0 Vdc/4 5Vdc/45 6 Vdc Vdc/2 Vdc/4 5Vdc/46 7 Vdc Vdc/2 0 6Vdc/4

7 /2 Vdc Vdc/2 Vdc/4 7Vdc/4

VI. CONCLUSIONS

A cascade multilevel inverter topology has been proposedthat requires only a single DC power source. Subject tospecified constraints, it was shown that the voltage level of thecapacitors can be controlled while at the same time choosingthe switching angles to achieve a specified modulation indexand eliminate harmonics in the output waveform.

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