SHIFT REGISTERS

Sarawut S. Janpong 2-14

1 BASIC SHIFT REGISTER FUNCTIONS

รูปท่ี 10.1 The flip-flop as a storage element

รูปท่ี 10.2 Basic data movement in shift registers (4-bits are used for illustration)

SHIFT REGISTERS

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2 SERIAL IN/SERIAL OUT SHIFT REGISTERS

รูปท่ี 10.3 Serial in/serial out shift register with an 4-bit capacity.

ตัวอยางShow the states of the 5-bit register in Figure 10-4(a) for the specified data input and clock

waveforms. Assume that the register is initially cleared (all 0s).

รูปท่ี 10.4

SHIFT REGISTERS

Sarawut S. Janpong 4-14

รูปท่ี 10.5 Logic symbol for an 8-bit serial in/serial out shift register

3 SERIAL IN/PARALLEL OUT SHIFT REGISTERS3.1 Operation

รูปท่ี 10.6 A serial in/parallel out shift register.

ตัวอยางShow the states of the 4-bit register for the data input and clock waveform in Figure 10-7(a).

The register initially contains all 1s.

รูปท่ี 10.7

SHIFT REGISTERS

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3.2 THE 74LS164 8-BIT SERIAL IN/PARALLEL OUT SHIFT REGISTER

รูปท่ี 10.8 The 74LS164 8-bit serial in/parallel out shift register.

รูปท่ี 10.9 Sample timing diagram for a 74LS164 shift register.

SHIFT REGISTERS

Sarawut S. Janpong 6-14

4 PARALLEL IN/ SERIAL OUT SHIFT REGISTERS4.1 Operation

รูปท่ี 10.10 A 4-bit parallel in/serial out shift register.ตัวอยาง

Show the data output waveform for a 4-bis register with the parallel input data and the clockand LOADSHIFT / waveforms given in Figure 10-11(a).

รูปท่ี 10.11

SHIFT REGISTERS

Sarawut S. Janpong 7-14

4.2 THE 74LS165 8-BIT PARALLEL LOAD SHIFT REGISTER

รูปท่ี 10.12 The 74LS165 8-bit parallel load shift register.

SHIFT REGISTERS

Sarawut S. Janpong 8-14

รูปท่ี 10.12 Sample timing diagram for a 74LS163 shift register.

5 PARALLEL IN/ PARALLEL OUT SHIFT REGISTERS5.1 Operation

รูปท่ี 10.13 A parallel in/parallel out register.

SHIFT REGISTERS

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5.2 THE 74LS195A 4-BIT PARALLEL ACCESS SHIFT REGISTER

รูปท่ี 10.14 The 74LS195A 4-bit parallel access shift register.

รูปท่ี 10.15 Sample timing diagram for a 74LS195A shift register.

SHIFT REGISTERS

Sarawut S. Janpong 10-14

6 BIDIRECTIONAL SHIFT REGISTERS6.1 Operation

รูปท่ี 10.16 4-bit bidirectional shift register.

ตัวอยางDetermine the state of the shift register of Figure 10-16 after each clock pulse for the given

LEFTRIGHT / control input waveform in Figure 10-17(a). Assume that 0,1,1 210 === QQQ

and 13 =Q and that the serial data-input line is LOW.

รูปท่ี 10.17

SHIFT REGISTERS

Sarawut S. Janpong 11-14

6.2 THE 74LS194A 4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER

รูปท่ี 10.18 The 74LS194A 4-bit bidirectional universal shift register.

รูปท่ี 10.19 Sample timing diagram for a 74LS194A shift register.

SHIFT REGISTERS

Sarawut S. Janpong 12-14

7 SHIFT REGISTER COUNTERS7.1 THE JOHNSON COUNTER

(a) 4-bit Johnson sequence (b) 5-bit Johnson sequenceตารางท่ี 10.1 4-bit and 5-bit Johnson sequence

(a) 4-bit John counter

(b) 5-bit John counter

รูปท่ี 10.20 4-bit and 5-bit Johnson counters.

SHIFT REGISTERS

Sarawut S. Janpong 13-14

รูปท่ี 10.21 Timing sequence for a 4-bit Johnson counter.

รูปท่ี 10.22 Timing sequence for a 5-bit Johnson counter.

7.2 THE RING COUNTER

ตารางท่ี 10.2 10-bit ring counter sequence.

SHIFT REGISTERS

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รูปท่ี 10.23 A 10-bit ring counter.

ตัวอยางIf a 10-bit ring counter similar to Figure 10-23 has the initial state 1010000000, determine

the waveform for each of the Q output.

รูปท่ี 10.24