Shaping Solutions in Advanced Semiconductor Assembly and TestPranab Sarma, Product Engineering Manager

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STATS ChipPAC Overview

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What we do – total turnkey solutions

Outsourced Semiconductor Assembly and Test Services (“OSAT”)

Wafer fabrication

Package design & simulation

Multipleapplications

Package assemblyBonding die on a substrate

Wire bonding to form electrical connection

Encapsulation of integrated circuits into packages

QA and final chip testing

Die singulation/wafer singulation

Wafer probe & bump

(Bump) (Sort)

Wafer design

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Semiconductor growth by market segment 2006–2011

Storage ($13.3)

(US$B)

CAGR (2006 – 2011) %4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0

$25

$0

$50

$75

$100

$125

$150

8.5 9.0 9.5

Mar

ket

Size

by

2011

Consumer ($60.4)

Computing/Data storage ($140.1)

Automotive ($27.3)

Communications($107.8)

Mil/Civil Areo ($4.8)

By 2011,total semi market $373.5Btotal OSAT market $30.4B

Industrial ($33.1)

Growth and scale in 3C’s Growth and scale in 3C’s

STATS ChipPAC market mix in 2006

STATS ChipPAC market mix in 2006

We are well aligned to high growth market segments

Consumer 24.6%

Communications 56.7%

Computing 18.7%

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Our positioning and strategyExcellence in

backend turnkey SATS solutions

Global strategic footprint that best

serves our customers

Technology differentiation in

integration

Invest in technology and

focus on long term growth products

Maintain capital discipline

(3D, SiP, FC, WLCSP, RF & mixed signal testing)

(Singapore, China, Korea, Malaysia, Taiwan, US)

(Bump, Sort, Assembly, Final Test)

(Strong balance sheet & cash flow) Positioning

and Strategy

(3D wafer level interconnect, CSMP and etc)

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Established presence in the world’s most strategic semiconductor markets

Milpitas and San Diego, CA: 34,000 ft2 and 20,000 ft2 respectively, pre-production test houses, provide complete semiconductor test services. Offers new product integration support, final test and other high volume preparatory services

Shanghai, China: 422,000 ft2 facility provides wafer sort, packaging and test services. Second 500,000 ft2 facility expected to be completed in 2Q 2007.

15,000 ft2 operation in Song Jiang District will be focused on 200mm gold bumping and wafer sort services for LCD driver ICs.

Singapore: Corporate Headquarters594,000 ft2 facility with state-of-the-art equipment, class 10K clean room. Provides full turnkey services including wafer probe, packaging, final testing and drop shipment

Hsin-Chu Hsien, Taiwan: Winstek, subsidiary with 220,000 ft2 facility, provides wafer probe services and final test.

Icheon, Korea: 587,000 ft2 high-end facility specializes in advanced array packaging such as Flip-Chip, Stacked Die, Chip Scale Packaging and BGA. Second 199,000 ft2 facility expected to be ready in second half 2007.

Hsin-Chu Hsien,Taiwan: 7,000 ft2 facility specializes in 300mm wafer electroplated solder bump

Global scale, unrivalled positioning

R&DManufacturing

Sales

Kuala Lumpur, Malaysia: 488,000 ft2 facility provides high volume packaging and test services for a full range of Mixed-Signal / RF test and Power Discrete devices

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• Feature rich end products required more silicon in less space

• 3D packaging takes advantage of the vertical axis to dramatically increase silicon density

• 3D packaging is enabling the digital revolution in communication and consumer products

6 die stackcapability

STATS ChipPAC is the leader in 3D packaging

AudioPU

FLASH FM Radio

DigitalBaseband

AnalogBasebandFLASH

SRAM

PowerMgmt

RF TX PA FEM

Handset layout block diagram

Trend towards customized packaging continues as integration of silicon becomes more complex

BT

Package-on-Package (PoP)

MEMSMIC

Image Sensor

Slim profile handset in the market

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STATS ChipPAC’s flip chip, gold bump and wafer sort complementing the turnkey services

• 300mm solder bumping and gold bump lines co-located with TSMC foundries

– 12” Solder bump – TSMC Fab 7 Hsin-chu

– 8” Gold bump – TSMC Songjiang

• Broad technology offering– Wafer processes (bumping, RDL, IPD, WLCSP)

– fcCSP (single die and stacked dies)

– fcBGA (bare die, lidded, multi-die, SiP)

• Well engaged with leading customers– GPU graphics & ASIC IDM/fabless companies

– LCD Driver IC fabless companies

• Leveraging 3D technology for emerging portable and consumer product applications

– Game consoles, portable PC, LCD HDTV

Resistor

Capacitor Inductor

Integrated passive devices

Gold (Au) bump

RDL Solder bumpWLCSP

fcLFBGA-SD2

fcBGA

fcBGA-MP

fcQFN

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Deliver the broadest and most comprehensive test capability

PoP PiPm PiPs

3-D memory testing in traction to support next generation 3-D packages

Type of Test Mixed signal High-end digital Radio frequency 3D/MemoryPosition test solution to enable turnkey strategy Yes Yes Yes Yes

Leverage expertise and scale SCS & SCM SCK & SCS SCS & SCM SCK & SCC

Utilize test R&D as key differentiator for turnkey Yes Yes Yes Yes

Breadth of application typesMCU, Mixer, CODEC, Tunner & Switches

CPU, GPU, DSP, PHY, MAC, ASIC & ASSP

Transceiver, Receiver, Transmitter, RF FEM & RFIC

Memory Card, NOR & NAND Flash

Breadth of package types QFN, QFP, BGA & CSP

FCBGA, FBGA, FBGA-SD, BGA, CSP & WLCSP

QFN, CSMP, SiP & WLCSP

FCBGA, FBGA-SD, PoP, PiP & MCC

Lowest cost of test Multi-site setup Multi-site setup Multi-site setup High parallel>320

Alignment with high growth market segment PC, Communication & Consumer

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Technology differentiation in integration

*United States Patent and Trademark Office

•Wafer process, wafer thinning, die attach, molding, packaging technique

Process

3D Stack Package

Leadframe Package

Flip Chip, SIP Packages

Laminate Package

Others •3D Leadership

•Flip chip enabling technologies

3-D wafer interconnect

● IP Alignment to Market

PoP PiPS

Energy saving, small form factor

Smaller footprint, high integrationHigh performance, high density

Flip-chip LFBGAm

● USPTO* IP Filing

20052006

117 filed37 issued

235 filed43 issued

Patents PublishedPatents Published

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Our leadership in shaping solutions to achieve product customization for our customers

Leading enabling technologies

VFBGA-T LFBGA-SD LFLGA

LFBGA-SiPTBGATFLGA

QFN/BCC PoP/PiP

Advanced packaging Broad test offering

+ +Seamless

integration

Customized solutions for our customers

FCBGA for GPULFBGA for CPU

TBGA for MPU

PoP/PiP for BB/MAC + Flash

Memory card packaging

QFN/BCC for TXVR

ADVANTEST

VERIGY

LTX FUSION FLEX

ROOS CATALYSTSubstrate Solder bump Gold bump

IPDStacked diesWire bond

Shielding RDLUFLEX HP93K/PS800

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Our market focusHigh growth marketsHigh growth markets

Wireless – 31% CAGR

Consumer -22% CAGR

PC/Storage – 18% CAGR

Automotive – 15% CAGR

Wireline – 14% CAGR

Note: CAGR period is five years (2006-2011)Source: Gartner DQ Dec’06

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Pb Free Conversion Status

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Pb Free Roadmap

• 70% of laminate volume is Pb – free.- All new products are Pb free.

• Of the remaining non Pb free products 80% are PBGA.- The BOM is Pb free except the solder ball that is Sn-Pb.-These are legacy products and will be supported based on demand.- New designs will generally move to Pb free.

• Requirement for being ROHS compliant and customer demand driving the push for higher conversion rate to Pb free.

- STATS ChipPAC’s product focus is more focused towards high growth markets that isdriving the conversion to Pb free and green solutions.

- Current business demands encourage investments in infrastructure for Pb free solution and discourages long term investments for supporting leaded solutions.

• STATS ChipPAC has done extensive studies comparing eutectic and Pb freesolution indicating that Pb free solutions are at par or better than eutectic.

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Pb Free ProgramBetter For Business – Better For Environment

Reliability Overview

• Qualified major package families internally and at customers.

• Completed and passed the following tests:- MRT L2a @ 260C, L3 @ 260C and specific customer conditions.- PCT (336 Hrs)- TC Condition “C” (1000 cycles)- HTS (1000 Hrs)- 85C/85% RH without Bias

• Passed BLR Tests with different Pb-free alloys.

• Passed Aging (Intermetallic) and Bend Tests.

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Overview: Package Level Reliability

• Reliability Target

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Board Level Reliability

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Board Level Reliability

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Board Level Reliability

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Board Level Reliability

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Board Level Reliability

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Pb Free Reliability Study Conclusion

• Lead-free Solder Joint Reliability is Superior.

• No Difference in the Reliability Among the Various Lead-free Solder JointsTested So Far.

• In General, Area Array Packages and Leadframe Packages Exhibit Acceptable Thermal Fatigue Resistance.

• Based on Internal Study, Customer Feedbacks, and Market Conditions,Conversion to Lead-free Offers Better Advantages Compared to Sn-Pb.

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The Road Ahead

• STATS ChipPAC is Committed to Continuous Conversion to Lead-freeSolutions.

- Existing customers will be supported during the life of the legacy products, however new designs will be continuously converted to Lead-free solutions.

• STATS ChipPAC is Ready for ROHS Implementation.

• Lead-free Solution is Better for Business and Better for Environment.

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Thank You