User's M

anual

SH7710, SH7712, SH7713 Group

User’s Manual: Hardware32

Rev.3.00 Mar 2012

Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

SH7710 HD6417710SH7712 HD6417712SH7713 HD6417713

www.renesas.com

The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text.

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Page iii of xxiv

Notice1. All information included in this document is current as of the date this document is issued. Such information, however, is

subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please

confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to

additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website.

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Page iv of xxiv

General Precautions on Handling of Product

1. Treatment of NC Pins

Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed.

2. Treatment of Unused Input Pins

Note: Fix all unused input pins to high or low level. Generally, the input pins of CMOS products are high-impedance input pins. If unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a pass-through current flows internally, and a malfunction may occur.

3. Processing before Initialization

Note: When power is first supplied, the product's state is undefined. The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin. During the period where the states are undefined, the register settings and the output state of each pin are also undefined. Design your system so that it does not malfunction because of processing while it is in this undefined state. For those products which have a reset function, reset the LSI immediately after the power supply has been turned on.

4. Prohibition of Access to Undefined or Reserved Addresses

Note: Access to undefined or reserved addresses is prohibited. The undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these addresses. Do not access these registers; the system's operation is not guaranteed if they are accessed.

Page v of xxiv

Configuration of This Manual

This manual comprises the following items:

1. General Precautions on Handling of Product

2. Configuration of This Manual

3. Preface

4. Contents

5. Overview

6. Description of Functional Modules

• CPU and System-Control Modules • On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module. However, the generic style includes the following items:

i) Feature

ii) Input/Output Pin

iii) Register Description

iv) Operation

v) Usage Note When designing an application system that includes this LSI, take notes into account. Each section includes notes in relation to the descriptions given, and usage notes are given, as required, as the final part of each section.

7. List of Registers

8. Electrical Characteristics

9. Appendix

10. Main Revisions and Additions in this Edition (only for revised versions) The list of revisions is a summary of points that have been revised or added to earlier versions. This does not include all of the revised contents. For details, see the actual locations in this manual.

11. Index

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Preface

This LSI is a RISC (Reduced Instruction Set Computer) microcomputer which includes a Renesas original RISC CPU as its core, and the peripheral functions required to configure a system.

Target Users: This manual was written for users who will be using this LSI in the design of application systems. Users of this manual are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers.

Objective: This manual was written to explain the hardware functions and electrical characteristics of this LSI to the above users. Refer to the SH-3/SH-3E/SH3-DSP Software Manual for a detailed description of the instruction set.

Notes on reading this manual:

• Product names The following products are covered in this manual.

Product Classifications and Abbreviations

Basic Classification Product Code

SH7710 HD6417710

SH7712 HD6417712

SH7713 HD6417713

• In order to understand the overall functions of the chip

Read the manual according to the contents. This manual can be roughly categorized into parts on the CPU, system control functions, peripheral functions and electrical characteristics.

• In order to understand the details of the CPU's functions

Read the SH-3/SH-3E/SH3-DSP Software Manual.

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Rules: Register name: The following notation is used for cases when the same or a similar function, e.g. serial communication interface, is implemented on more than one channel: XXX_N (XXX is the register name and N is the channel number)

Bit order: The MSB (most significant bit) is on the left and the LSB (least significant bit) is on the right.

Number notation: Binary is B'xxxx, hexadecimal is H'xxxx, decimal is xxxx.

Signal notation: An overbar is added to a low-active signal: xxxx

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Abbreviations

ACIA Asynchronous communication interface adapter

AUD Advanced user debugger

BSC Bus state controller

CPG Clock pulse generator

DMA Direct memory access

DMAC Direct memory access controller

etu Elementary time unit

FIFO First-in first-out

H-UDI User debugging interface

INTC Interrupt controller

IPSEC Security architecture accelerator for internet protocol

JTAG Joint test action group

LSB Least significant bit

MMU Memory management unit

MSB Most significant bit

PFC Pin function controller

RISC Reduced instruction set computer

RTC Realtime clock

SCIF Serial communication interface with FIFO

SIOF Serial I/O with FIFO

TLB Translation lookaside buffer

TMU Timer unit

UART Universal asynchronous receiver/transmitter

UBC User break controller

WDT Watchdog timer

All trademarks and registered trademarks are the property of their respective owners.

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Contents

Section 1 Overview and Pin Function ...................................................................1 1.1 Features.................................................................................................................................. 1 1.2 Block Diagram....................................................................................................................... 8 1.3 Pin Description..................................................................................................................... 11

1.3.1 Pin Assignment ....................................................................................................... 11 1.3.2 Pin Functions .......................................................................................................... 27

Section 2 CPU......................................................................................................37 2.1 Processing States and Processing Modes............................................................................. 37

2.1.1 Processing States..................................................................................................... 37 2.1.2 Processing Modes ................................................................................................... 38

2.2 Memory Map ....................................................................................................................... 39 2.2.1 Logical Address Space............................................................................................ 39 2.2.2 External Memory Space.......................................................................................... 40

2.3 Register Descriptions ........................................................................................................... 42 2.3.1 General Registers.................................................................................................... 45 2.3.2 System Registers..................................................................................................... 46 2.3.3 Program Counter..................................................................................................... 47 2.3.4 Control Registers .................................................................................................... 48

2.4 Data Formats........................................................................................................................ 52 2.4.1 Register Data Format .............................................................................................. 52 2.4.2 Memory Data Formats ............................................................................................ 52

2.5 Features of CPU Core Instructions ...................................................................................... 54 2.5.1 Instruction Execution Method................................................................................. 54 2.5.2 CPU Instruction Addressing Modes ....................................................................... 55 2.5.3 CPU Instruction Formats ........................................................................................ 58

2.6 Instruction Set ...................................................................................................................... 62 2.6.1 CPU Instruction Set Based on Functions ................................................................ 62 2.6.2 Operation Code Map............................................................................................... 76

Section 3 DSP Operating Unit .............................................................................81 3.1 DSP Extended Functions ..................................................................................................... 81 3.2 DSP Mode Resources .......................................................................................................... 83

3.2.1 Processing Modes ................................................................................................... 83 3.2.2 DSP Mode Memory Map........................................................................................ 83 3.2.3 CPU Register Sets................................................................................................... 84

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3.2.4 DSP Registers ......................................................................................................... 87 3.3 CPU Extended Instructions.................................................................................................. 88

3.3.1 Repeat Control Instructions .................................................................................... 88 3.3.2 Extended Repeat Control Instructions .................................................................... 98

3.4 DSP Data Transfer Instructions ......................................................................................... 103 3.4.1 General Registers.................................................................................................. 107 3.4.2 DSP Data Addressing ........................................................................................... 109 3.4.3 Modulo Addressing .............................................................................................. 110 3.4.4 Memory Data Formats .......................................................................................... 113 3.4.5 Instruction Formats of Double and Single Transfer Instructions .......................... 113

3.5 DSP Data Operation Instructions....................................................................................... 116 3.5.1 DSP Registers ....................................................................................................... 116 3.5.2 DSP Operation Instruction Set.............................................................................. 121 3.5.3 DSP-Type Data Formats....................................................................................... 126 3.5.4 ALU Fixed-Point Operations................................................................................ 128 3.5.5 ALU Integer Operations ....................................................................................... 133 3.5.6 ALU Logical Operations ...................................................................................... 135 3.5.7 Fixed-Point Multiply Operation............................................................................ 136 3.5.8 Shift Operations .................................................................................................... 138 3.5.9 Most Significant Bit Detection Operation ............................................................ 142 3.5.10 Rounding Operation.............................................................................................. 145 3.5.11 Overflow Protection.............................................................................................. 147 3.5.12 Local Data Move Instruction ................................................................................ 148 3.5.13 Operand Conflict .................................................................................................. 149

3.6 DSP Extended Function Instruction Set............................................................................. 150 3.6.1 CPU Extended Instructions................................................................................... 150 3.6.2 Double-Data Transfer Instructions ....................................................................... 152 3.6.3 Single-Data Transfer Instructions ......................................................................... 153 3.6.4 DSP Operation Instructions .................................................................................. 155 3.6.5 Operation Code Map in DSP Mode ...................................................................... 161

Section 4 Exception Handling ...........................................................................165 4.1 Register Descriptions......................................................................................................... 165

4.1.1 TRAPA Exception Register (TRA) ...................................................................... 166 4.1.2 Exception Event Register (EXPEVT)................................................................... 167 4.1.3 Interrupt Event Register (INTEVT)...................................................................... 167 4.1.4 Interrupt Event Register 2 (INTEVT2)................................................................. 168 4.1.5 Exception Address Register (TEA) ...................................................................... 168

4.2 Exception Handling Function ............................................................................................ 169 4.2.1 Exception Handling Flow ..................................................................................... 169

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4.2.2 Exception Vector Addresses ................................................................................. 170 4.2.3 Exception Codes ................................................................................................... 170 4.2.4 Exception Request and BL Bit (Multiple Exception Prevention) ......................... 170 4.2.5 Exception Source Acceptance Timing and Priority .............................................. 171

4.3 Individual Exception Operations........................................................................................ 175 4.3.1 Resets.................................................................................................................... 175 4.3.2 General Exceptions ............................................................................................... 176 4.3.3 General Exceptions (MMU Exceptions)............................................................... 179

4.4 Exception Processing while DSP Extension Function is Valid.......................................... 182 4.4.1 Illegal Instruction Exception and Slot Illegal Instruction Exception .................... 182 4.4.2 CPU Address Error ............................................................................................... 182 4.4.3 Exception in Repeat Control Period...................................................................... 182

4.5 Usage Notes ....................................................................................................................... 189

Section 5 Memory Management Unit (MMU) ..................................................191 5.1 Role of MMU..................................................................................................................... 191

5.1.1 MMU of This LSI ................................................................................................. 193 5.2 Register Descriptions ......................................................................................................... 199

5.2.1 Page Table Entry Register High (PTEH).............................................................. 200 5.2.2 Page Table Entry Register Low (PTEL) ............................................................... 201 5.2.3 Translation Table Base Register (TTB) ................................................................ 201 5.2.4 MMU Control Register (MMUCR) ...................................................................... 201

5.3 TLB Functions ................................................................................................................... 203 5.3.1 Configuration of the TLB ..................................................................................... 203 5.3.2 TLB Indexing........................................................................................................ 205 5.3.3 TLB Address Comparison .................................................................................... 206 5.3.4 Page Management Information............................................................................. 208

5.4 MMU Functions................................................................................................................. 210 5.4.1 MMU Hardware Management .............................................................................. 210 5.4.2 MMU Software Management ............................................................................... 210 5.4.3 MMU Instruction (LDTLB).................................................................................. 211 5.4.4 Avoiding Synonym Problems ............................................................................... 212

5.5 MMU Exceptions............................................................................................................... 215 5.5.1 TLB Miss Exception............................................................................................. 215 5.5.2 TLB Protection Violation Exception .................................................................... 216 5.5.3 TLB Invalid Exception ......................................................................................... 217 5.5.4 Initial Page Write Exception................................................................................. 218 5.5.5 MMU Exception in Repeat Loop.......................................................................... 219

5.6 Memory-Mapped TLB....................................................................................................... 221 5.6.1 Address Array ....................................................................................................... 221

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5.6.2 Data Array ............................................................................................................ 221 5.6.3 Usage Examples.................................................................................................... 223

5.7 Usage Note......................................................................................................................... 223

Section 6 Cache .................................................................................................225 6.1 Features.............................................................................................................................. 225

6.1.1 Cache Structure..................................................................................................... 225 6.2 Register Descriptions......................................................................................................... 227

6.2.1 Cache Control Register 1 (CCR1) ........................................................................ 227 6.2.2 Cache Control Register 2 (CCR2) ........................................................................ 228 6.2.3 Cache Control Register 3 (CCR3) ........................................................................ 231

6.3 Operation ........................................................................................................................... 232 6.3.1 Searching the Cache.............................................................................................. 232 6.3.2 Read Access.......................................................................................................... 233 6.3.3 Prefetch Operation ................................................................................................ 234 6.3.4 Write Access......................................................................................................... 234 6.3.5 Write-Back Buffer ................................................................................................ 234 6.3.6 Coherency of Cache and External Memory.......................................................... 235

6.4 Memory-Mapped Cache .................................................................................................... 236 6.4.1 Address Array....................................................................................................... 236 6.4.2 Data Array ............................................................................................................ 237 6.4.3 Usage Examples.................................................................................................... 240

Section 7 X/Y Memory .....................................................................................241 7.1 Features.............................................................................................................................. 241 7.2 Operation ........................................................................................................................... 242

7.2.1 Access from CPU ................................................................................................. 242 7.2.2 Access from DSP.................................................................................................. 242 7.2.3 Access from DMAC, E-DMAC, and IPSEC ........................................................ 243

7.3 Usage Notes ....................................................................................................................... 243 7.3.1 Page Conflict ........................................................................................................ 243 7.3.2 Bus Conflict .......................................................................................................... 243 7.3.3 MMU and Cache Settings..................................................................................... 244 7.3.4 Sleep Mode ........................................................................................................... 244 7.3.5 Address Error........................................................................................................ 245

Section 8 Interrupt Controller (INTC)...............................................................247 8.1 Features.............................................................................................................................. 247

8.1.1 Block Diagram...................................................................................................... 247 8.2 Input/Output Pins............................................................................................................... 249

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8.3 Interrupt Sources................................................................................................................ 249 8.3.1 NMI Interrupt........................................................................................................ 249 8.3.2 IRQ Interrupts ....................................................................................................... 250 8.3.3 IRL Interrupts ....................................................................................................... 250 8.3.4 On-Chip Peripheral Module Interrupts ................................................................. 251 8.3.5 Interrupt Exception Handling and Priority............................................................ 252

8.4 Register Descriptions ......................................................................................................... 258 8.4.1 Interrupt Priority Registers A to I (IPRA to IPRI) ................................................ 259 8.4.2 Interrupt Control Register 0 (ICR0)...................................................................... 261 8.4.3 Interrupt Control Register 1 (ICR1)...................................................................... 262 8.4.4 Interrupt Request Register 0 (IRR0) ..................................................................... 264 8.4.5 Interrupt Request Register 1 (IRR1) ..................................................................... 264 8.4.6 Interrupt Request Register 2 (IRR2) ..................................................................... 266 8.4.7 Interrupt Request Register 3 (IRR3) ..................................................................... 267 8.4.8 Interrupt Request Register 4 (IRR4) ..................................................................... 268 8.4.9 Interrupt Request Register 5 (IRR5) ..................................................................... 269 8.4.10 Interrupt Request Register 7 (IRR7) ..................................................................... 271 8.4.11 Interrupt Request Register 8 (IRR8) ..................................................................... 272

8.5 Operation ........................................................................................................................... 273 8.5.1 Interrupt Sequence ................................................................................................ 273 8.5.2 Multiple Interrupts ................................................................................................ 275

Section 9 User Break Controller ........................................................................277 9.1 Features.............................................................................................................................. 277 9.2 Register Descriptions ......................................................................................................... 280

9.2.1 Break Address Register A (BARA) ...................................................................... 280 9.2.2 Break Address Mask Register A (BAMRA)......................................................... 281 9.2.3 Break Bus Cycle Register A (BBRA)................................................................... 281 9.2.4 Break Address Register B (BARB) ...................................................................... 283 9.2.5 Break Address Mask Register B (BAMRB) ......................................................... 284 9.2.6 Break Data Register B (BDRB)............................................................................ 284 9.2.7 Break Data Mask Register B (BDMRB)............................................................... 285 9.2.8 Break Bus Cycle Register B (BBRB) ................................................................... 286 9.2.9 Break Control Register (BRCR) ........................................................................... 288 9.2.10 Execution Times Break Register (BETR)............................................................. 292 9.2.11 Branch Source Register (BRSR)........................................................................... 293 9.2.12 Branch Destination Register (BRDR)................................................................... 294 9.2.13 Break ASID Register A (BASRA)........................................................................ 294 9.2.14 Break ASID Register B (BASRB) ........................................................................ 295

9.3 Operation ........................................................................................................................... 295

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9.3.1 Flow of the User Break Operation ........................................................................ 295 9.3.2 Break on Instruction Fetch Cycle ......................................................................... 297 9.3.3 Break on Data Access Cycle................................................................................. 297 9.3.4 Break on X/Y-Memory Bus Cycle ....................................................................... 299 9.3.5 Sequential Break................................................................................................... 299 9.3.6 Value of Saved Program Counter ......................................................................... 300 9.3.7 PC Trace ............................................................................................................... 301 9.3.8 Usage Examples.................................................................................................... 301

9.4 Usage Notes ....................................................................................................................... 306

Section 10 Power-Down Modes........................................................................309 10.1 Overview............................................................................................................................ 309

10.1.1 Power-Down Modes ............................................................................................. 309 10.1.2 Reset ..................................................................................................................... 310 10.1.3 Input/Output Pins.................................................................................................. 312

10.2 Register Descriptions......................................................................................................... 312 10.2.1 Standby Control Register (STBCR)...................................................................... 312 10.2.2 Standby Control Register 2 (STBCR2)................................................................. 314 10.2.3 Standby Control Register 3 (STBCR3)................................................................. 315

10.3 Operation ........................................................................................................................... 316 10.3.1 Sleep Mode ........................................................................................................... 316 10.3.2 Software Standby Mode........................................................................................ 317 10.3.3 Module Standby Function..................................................................................... 319 10.3.4 STATUS Pin Change Timings.............................................................................. 320

Section 11 On-Chip Oscillation Circuits...........................................................325 11.1 Overview............................................................................................................................ 325

11.1.1 Features................................................................................................................. 325 11.2 Overview of CPG............................................................................................................... 327

11.2.1 CPG Block Diagram ............................................................................................. 327 11.2.2 Input/Output Pins.................................................................................................. 329

11.3 Clock Operating Modes ..................................................................................................... 329 11.4 Register Description .......................................................................................................... 334

11.4.1 Frequency Control Register (FRQCR) ................................................................. 334 11.5 Changing Frequency .......................................................................................................... 336

11.5.1 Changing Multiplication Rate............................................................................... 336 11.5.2 Changing Division Ratio ...................................................................................... 336

11.6 Overview of WDT ............................................................................................................. 337 11.6.1 Block Diagram of WDT ....................................................................................... 337

11.7 Register Descriptions of WDT........................................................................................... 338

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11.7.1 Watchdog Timer Counter (WTCNT).................................................................... 338 11.7.2 Watchdog Timer Control/Status Register (WTCSR)............................................ 338 11.7.3 Notes on Register Access...................................................................................... 340

11.8 Using WDT........................................................................................................................ 341 11.8.1 Canceling Standbys............................................................................................... 341 11.8.2 Changing Frequency ............................................................................................. 342 11.8.3 Using Watchdog Timer Mode .............................................................................. 342 11.8.4 Using Interval Timer Mode .................................................................................. 342

11.9 Notes on Board Design ...................................................................................................... 343

Section 12 Bus State Controller (BSC)..............................................................347 12.1 Features.............................................................................................................................. 347 12.2 Input/Output Pins ............................................................................................................... 350 12.3 Area Overview................................................................................................................... 352

12.3.1 Area Division........................................................................................................ 352 12.3.2 Shadow Area......................................................................................................... 352 12.3.3 Address Map......................................................................................................... 354 12.3.4 Area 0 Memory Type and Memory Bus Width .................................................... 356 12.3.5 Data Alignment..................................................................................................... 356

12.4 Register Descriptions ......................................................................................................... 357 12.4.1 Common Control Register (CMNCR) .................................................................. 358 12.4.2 CSn Space Bus Control Register (CSnBCR)

(n = 0, 2, 3, 4, 5A, 5B, 6A, 6B)............................................................................. 361 12.4.3 CSn Space Wait Control Register (CSnWCR)

(n = 0, 2, 3, 4, 5A, 5B, 6A, 6B)............................................................................. 366 12.4.4 SDRAM Control Register (SDCR)....................................................................... 393 12.4.5 Refresh Timer Control/Status Register (RTCSR)................................................. 396 12.4.6 Refresh Timer Counter (RTCNT)......................................................................... 397 12.4.7 Refresh Time Constant Register (RTCOR) .......................................................... 398

12.5 Operation ........................................................................................................................... 399 12.5.1 Endian/Access Size and Data Alignment.............................................................. 399 12.5.2 Normal Space Interface......................................................................................... 405 12.5.3 Access Wait Control ............................................................................................. 411 12.5.4 CSn Assert Period Expansion ............................................................................... 413 12.5.5 SDRAM Interface ................................................................................................. 414 12.5.6 Burst ROM (Clock Asynchronous) Interface ....................................................... 456 12.5.7 Byte-Selection SRAM Interface ........................................................................... 458 12.5.8 PCMCIA Interface................................................................................................ 463 12.5.9 Burst ROM (Clock Synchronous) Interface.......................................................... 469 12.5.10 Wait between Access Cycles ................................................................................ 470

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12.5.11 Bus Arbitration ..................................................................................................... 470 12.5.12 Others.................................................................................................................... 474

Section 13 Direct Memory Access Controller (DMAC)...................................477 13.1 Features.............................................................................................................................. 477 13.2 Input/Output Pins............................................................................................................... 479 13.3 Register Descriptions......................................................................................................... 480

13.3.1 DMA Source Address Register (SAR) ................................................................. 481 13.3.2 DMA Destination Address Register (DAR) ......................................................... 481 13.3.3 DMA Transfer Count Register (DMATCR)......................................................... 482 13.3.4 DMA Channel Control Register (CHCR)............................................................. 482 13.3.5 DMA Operation Register (DMAOR) ................................................................... 487 13.3.6 DMA Extension Resource Selector 0 to 2 (DMARS0 to DMARS2) ................... 490

13.4 Operation ........................................................................................................................... 493 13.4.1 DMA Transfer Flow ............................................................................................. 493 13.4.2 DMA Transfer Requests ....................................................................................... 496 13.4.3 Channel Priority.................................................................................................... 498 13.4.4 DMA Transfer Types............................................................................................ 501 13.4.5 Number of Bus Cycle States and DREQ Pin Sampling Timing ........................... 508

13.5 Usage Note......................................................................................................................... 512 13.5.1 Note on Using TEND Pin ..................................................................................... 512 13.5.2 Notes On DREQ Sampling When DACK is Divided in External Access ............ 513

Section 14 Timer Unit (TMU)...........................................................................517 14.1 Features.............................................................................................................................. 517

14.1.1 Block Diagram...................................................................................................... 517 14.2 Register Descriptions......................................................................................................... 519

14.2.1 Timer Start Register (TSTR) ................................................................................ 519 14.2.2 Timer Control Registers (TCR) ............................................................................ 520 14.2.3 Timer Constant Registers (TCOR) ....................................................................... 521 14.2.4 Timer Counters (TCNT) ....................................................................................... 521

14.3 TMU Operation.................................................................................................................. 522 14.3.1 Counter Operation ................................................................................................ 522

14.4 Interrupts............................................................................................................................ 525 14.4.1 Status Flag Set Timing.......................................................................................... 525 14.4.2 Status Flag Clear Timing ...................................................................................... 525 14.4.3 Interrupt Sources and Priorities ............................................................................ 526

14.5 Usage Notes ....................................................................................................................... 526 14.5.1 Writing to Registers .............................................................................................. 526 14.5.2 Reading Registers ................................................................................................. 526

Page xvii of xxiv

Section 15 Realtime Clock (RTC) .....................................................................527 15.1 Feature ............................................................................................................................... 527 15.2 Input/Output Pins ............................................................................................................... 529 15.3 Register Descriptions ......................................................................................................... 529

15.3.1 64-Hz Counter (R64CNT) .................................................................................... 530 15.3.2 Second Counter (RSECCNT) ............................................................................... 530 15.3.3 Minute Counter (RMINCNT) ............................................................................... 531 15.3.4 Hour Counter (RHRCNT)..................................................................................... 531 15.3.5 Day of Week Counter (RWKCNT) ...................................................................... 532 15.3.6 Date Counter (RDAYCNT) .................................................................................. 534 15.3.7 Month Counter (RMONCNT) .............................................................................. 534 15.3.8 Year Counter (RYRCNT) ..................................................................................... 535 15.3.9 Second Alarm Register (RSECAR) ...................................................................... 536 15.3.10 Minute Alarm Register (RMINAR)...................................................................... 536 15.3.11 Hour Alarm Register (RHRAR) ........................................................................... 537 15.3.12 Day of Week Alarm Register (RWKAR) ............................................................. 538 15.3.13 Date Alarm Register (RDAYAR)......................................................................... 539 15.3.14 Month Alarm Register (RMONAR) ..................................................................... 540 15.3.15 Year Alarm Register (RYRAR)............................................................................ 541 15.3.16 RTC Control Register 1 (RCR1)........................................................................... 542 15.3.17 RTC Control Register 2 (RCR2)........................................................................... 544 15.3.18 RTC Control Register 3 (RCR3)........................................................................... 546

15.4 Operation ........................................................................................................................... 547 15.4.1 Initial Settings of Registers after Power-On ......................................................... 547 15.4.2 Setting Time.......................................................................................................... 547 15.4.3 Reading Time........................................................................................................ 547 15.4.4 Alarm Function ..................................................................................................... 549 15.4.5 Crystal Oscillator Circuit ...................................................................................... 550

15.5 Usage Notes ....................................................................................................................... 551 15.5.1 Register Writing during RTC Count..................................................................... 551 15.5.2 Use of Realtime Clock (RTC) Periodic Interrupts ................................................ 551 15.5.3 Transition to Standby Mode after Setting Register............................................... 551 15.5.4 Usage Note about RTC Power Supply (1) ............................................................ 552 15.5.5 Usage Note about RTC Power Supply (2) ............................................................ 552

Section 16 Serial Communication Interface with FIFO (SCIF) ........................553 16.1 Features.............................................................................................................................. 553 16.2 Input/Output Pins ............................................................................................................... 556 16.3 Register Descriptions ......................................................................................................... 557

16.3.1 Receive Shift Register (SCRSR)........................................................................... 558

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16.3.2 Receive FIFO Data Register (SCFRDR) .............................................................. 558 16.3.3 Transmit Shift Register (SCTSR) ......................................................................... 559 16.3.4 Transmit FIFO Data Register (SCFTDR)............................................................. 559 16.3.5 Serial Mode Register (SCSMR)............................................................................ 559 16.3.6 Serial Control Register (SCSCR).......................................................................... 563 16.3.7 Serial Status Register (SCFSR) ............................................................................ 567 16.3.8 Bit Rate Register (SCBRR) .................................................................................. 575 16.3.9 FIFO Control Register (SCFCR) .......................................................................... 576 16.3.10 FIFO Data Count Register (SCFDR).................................................................... 578 16.3.11 Line Status Register (SCLSR) .............................................................................. 580

16.4 Operation ........................................................................................................................... 581 16.4.1 Overview .............................................................................................................. 581 16.4.2 Serial Operation in Asynchronous Mode.............................................................. 583 16.4.3 Serial Operation in Clock Synchronous Mode ..................................................... 594

16.5 SCIF Interrupt Sources and DMAC................................................................................... 604 16.6 Usage Notes ....................................................................................................................... 605

Section 17 Serial I/O with FIFO (SIOF) ...........................................................609 17.1 Features.............................................................................................................................. 609

17.1.1 Block Diagram...................................................................................................... 610 17.2 Input/Output Pins............................................................................................................... 611 17.3 Register Descriptions......................................................................................................... 612

17.3.1 SIOF Mode Register (SIMDR)............................................................................. 613 17.3.2 Serial Clock Select Register (SISCR)................................................................... 615 17.3.3 Serial Transmit Data Assign Register (SITDAR)................................................. 616 17.3.4 Serial Receive Data Assign Register (SIRDAR) .................................................. 617 17.3.5 Serial Control Data Assign Register (SICDAR)................................................... 618 17.3.6 SIOF Control Register (SICTR) ........................................................................... 620 17.3.7 SIOF FIFO Control Register (SIFCTR)................................................................ 623 17.3.8 SIOF Status Register (SISTR) .............................................................................. 625 17.3.9 SIOF Interrupt Enable Register (SIIER)............................................................... 629 17.3.10 Serial Transmit Data Register (SITDR)................................................................ 631 17.3.11 Serial Receive Data Register (SIRDR) ................................................................. 632 17.3.12 Serial Transmit Control Data Register (SITCR)................................................... 633 17.3.13 Serial Receive Control Data Register (SIRCR) .................................................... 634

17.4 Operation ........................................................................................................................... 635 17.4.1 Serial Clocks......................................................................................................... 635 17.4.2 Serial Timing ........................................................................................................ 636 17.4.3 Transfer Data Format............................................................................................ 638 17.4.4 Register Allocation of Transfer Data .................................................................... 639

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17.4.5 Control Data Interface .......................................................................................... 642 17.4.6 FIFO...................................................................................................................... 643 17.4.7 Transmission and Reception Procedures .............................................................. 645 17.4.8 Interrupts............................................................................................................... 650 17.4.9 Transmission and Reception Timing .................................................................... 652

17.5 Usage Notes ....................................................................................................................... 657

Section 18 Ethernet Controller (EtherC)............................................................659 18.1 Features.............................................................................................................................. 659 18.2 Input/Output Pins ............................................................................................................... 662 18.3 Register Descriptions ......................................................................................................... 664

18.3.1 Software Reset Register (ARSTR) ....................................................................... 666 18.3.2 EtherC Mode Register (ECMR)............................................................................ 667 18.3.3 EtherC Status Register (ECSR) ............................................................................ 670 18.3.4 EtherC Interrupt Permission Register (ECSIPR) .................................................. 671 18.3.5 PHY Interface Register (PIR) ............................................................................... 672 18.3.6 MAC Address High Register (MAHR) ................................................................ 673 18.3.7 MAC Address Low Register (MALR).................................................................. 673 18.3.8 Receive Frame Length Register (RFLR) .............................................................. 674 18.3.9 PHY Status Register (PSR)................................................................................... 675 18.3.10 Transmit Retry Over Counter Register (TROCR) ................................................ 675 18.3.11 Delayed Collision Detect Counter Register (CDCR)............................................ 676 18.3.12 Lost Carrier Counter Register (LCCR)................................................................. 676 18.3.13 Carrier Not Detect Counter Register (CNDCR) ................................................... 676 18.3.14 CRC Error Frame Receive Counter Register (CEFCR)........................................ 677 18.3.15 Frame Receive Error Counter Register (FRECR)................................................. 677 18.3.16 Too-Short Frame Receive Counter Register (TSFRCR)....................................... 677 18.3.17 Too-Long Frame Receive Counter Register (TLFRCR)....................................... 678 18.3.18 Residual-Bit Frame Receive Counter Register (RFCR) ....................................... 678 18.3.19 Multicast Address Frame Receive Counter Register (MAFCR)........................... 679 18.3.20 IPG Register (IPGR)............................................................................................. 679 18.3.21 TSU Counter Reset Register (TSU_CTRST) ....................................................... 680 18.3.22 Relay Enable Register (Port 0 to 1) (TSU_FWEN0) (SH7710, SH7712) ............ 681 18.3.23 Relay Enable Register (Port 1 to 0) (TSU_FWEN1) (SH7710, SH7712) ............ 681 18.3.24 Relay FIFO Size Select Register (TSU_FCM) (SH7710, SH7712)...................... 682 18.3.25 Relay FIFO Overflow Alert Set Register (Port 0) (TSU_BSYSL0)

(SH7710, SH7712)................................................................................................ 683 18.3.26 Relay FIFO Overflow Alert Set Register (Port 1) (TSU_BSYSL1)

(SH7710, SH7712)................................................................................................ 684

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18.3.27 Transmit/Relay Priority Control Mode Register (Port 0) (TSU_PRISL0) (SH7710, SH7712) ............................................................................................... 685

18.3.28 Transmit/Relay Priority Control Mode Register (Port 1) (TSU_PRISL1) (SH7710, SH7712) ............................................................................................... 686

18.3.29 Receive/Relay Function Set Register (Port 0 to 1) (TSU_FWSL0) (SH7710, SH7712) ............................................................................................... 688

18.3.30 Receive/Relay Function Set Register (Port 1 to 0) (TSU_FWSL1) (SH7710, SH7712) ............................................................................................... 689

18.3.31 Relay Function Set Register (Common) (TSU_FWSLC) (SH7710, SH7712) ..... 691 18.3.32 Qtag Addition/Deletion Set Register (Port 0 to 1) (TSU_QTAGM0)

(SH7710, SH7712) ............................................................................................... 693 18.3.33 Qtag Addition/Deletion Set Register (Port 1 to 0) (TSU_QTAGM1)

(SH7710, SH7712) ............................................................................................... 694 18.3.34 Relay Status Register (TSU_FWSR) (SH7710, SH7712) .................................... 695 18.3.35 Relay Status Interrupt Mask Register (TSU_FWINMK) (SH7710, SH7712) ...... 697 18.3.36 Added Qtag Value Set Register (Port 0 to 1) (TSU_ADQT0)

(SH7710, SH7712) ............................................................................................... 701 18.3.37 Added Qtag Value Set Register (Port 1 to 0) (TSU_ADQT1)

(SH7710, SH7712) ............................................................................................... 702 18.3.38 CAM Entry Table Busy Register (TSU_ADSBSY) (SH7710, SH7712) ............. 703 18.3.39 CAM Entry Table Enable Register (TSU_TEN) (SH7710, SH7712)................... 704 18.3.40 CAM Entry Table POST1 Register (TSU_POST1) (SH7710, SH7712).............. 708 18.3.41 CAM Entry Table POST2 Register (TSU_POST2) (SH7710, SH7712).............. 711 18.3.42 CAM Entry Table POST3 Register (TSU_POST3) (SH7710, SH7712).............. 714 18.3.43 CAM Entry Table POST4 Register (TSU_POST4) (SH7710, SH7712).............. 717 18.3.44 CAM Entry Table 0 to 31 H Registers (TSU_ADRH0 to TSU_ADRH31)

(SH7710, SH7712) ............................................................................................... 720 18.3.45 CAM Entry Table 0 to 31 L Registers (TSU_ADRL0 to TSU_ADRL31)

(SH7710, SH7712) ............................................................................................... 721 18.3.46 Transmit Frame Counter Register (Normal Transmission Only) (Port 0)

(TXNLCR0) (SH7710, SH7712) / (TXNLCR) (SH7713).................................... 721 18.3.47 Transmit Frame Counter Register (Normal and Error Transmission) (Port 0)

(TXALCR0) (SH7710, SH7712) / (TXALCR) (SH7713).................................... 722 18.3.48 Receive Frame Counter Register (Normal Reception Only) (Port 0)

(RXNLCR0) (SH7710, SH7712) / (RXNLCR) (SH7713) ................................... 722 18.3.49 Receive Frame Counter Register (Normal and Error Reception) (Port 0)

(RXALCR0) (SH7710, SH7712) / (RXALCR) (SH7713) ................................... 723 18.3.50 Relay Frame Counter Register (Normal Relay Only) (Port 1 to 0)

(FWNLCR0) (SH7710, SH7712) ......................................................................... 723

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18.3.51 Relay Frame Counter Register (Normal and Error Relay) (Port 1 to 0) (FWALCR0) (SH7710, SH7712) ......................................................................... 724

18.3.52 Transmit Frame Counter Register (Normal Transmission Only) (Port 1) (TXNLCR1) (SH7710, SH7712) .......................................................................... 724

18.3.53 Transmit Frame Counter Register (Normal and Error Transmission) (Port 1) (TXALCR1) (SH7710, SH7712) ......................................................................... 725

18.3.54 Receive Frame Counter Register (Normal Reception Only) (Port 1) (RXNLCR1) (SH7710, SH7712).......................................................................... 725

18.3.55 Receive Frame Counter Register (Normal and Error Reception) (Port 1) (RXALCR1) (SH7710, SH7712).......................................................................... 726

18.3.56 Relay Frame Counter Register (Normal Relay Only) (Port 0 to 1) (FWNLCR1) (SH7710, SH7712) ......................................................................... 726

18.3.57 Relay Frame Counter Register (Normal and Error Relay) (Port 0 to 1) (FWALCR1) (SH7710, SH7712) ......................................................................... 727

18.4 Operation ........................................................................................................................... 728 18.4.1 Transmission (Applied to All of the SH7710, SH7712, and SH7713) ................. 729 18.4.2 Reception (Applied to All of the SH7710, SH7712, and SH7713)....................... 731 18.4.3 Relay (Applied Only to the SH7710 and SH7712) ............................................... 733 18.4.4 CAM Function (Applied Only to the SH7710 and SH7712) ................................ 733 18.4.5 MII Frame Timing (Applied to All of the SH7710, SH7712, and SH7713)......... 739 18.4.6 Accessing MII Registers

(Applied to All of the SH7710, SH7712, and SH7713)........................................ 741 18.4.7 Magic Packet Detection

(Applied to All of the SH7710, SH7712, and SH7713)........................................ 744 18.4.8 Operation by IPG Setting

(Applied to All of the SH7710, SH7712, and SH7713)........................................ 745 18.4.9 Direction for IEEE802.1Q Qtag (Applied Only to the SH7710 and SH7712)...... 745

18.5 Connection to PHY-LSI (Applied to All of the SH7710, SH7712, and SH7713) ............. 747 18.6 Usage Notes (Applied Only to the SH7713)...................................................................... 748

18.6.1 Initial Setting ........................................................................................................ 748

Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC) .......................................................................................749

19.1 Features.............................................................................................................................. 749 19.2 Register Descriptions ......................................................................................................... 751

19.2.1 E-DMAC Mode Register (EDMR) ....................................................................... 752 19.2.2 E-DMAC Transmit Request Register (EDTRR)................................................... 753 19.2.3 E-DMAC Receive Request Register (EDRRR).................................................... 754 19.2.4 Transmit Descriptor List Address Register (TDLAR).......................................... 755 19.2.5 Receive Descriptor List Address Register (RDLAR) ........................................... 756

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19.2.6 EtherC/E-DMAC Status Register (EESR)............................................................ 756 19.2.7 EtherC/E-DMAC Status Interrupt Permission Register (EESIPR)....................... 762 19.2.8 Transmit/Receive Status Copy Enable Register (TRSCER)................................. 765 19.2.9 Receive Missed-Frame Counter Register (RMFCR) ............................................ 766 19.2.10 Transmit FIFO Threshold Register (TFTR).......................................................... 767 19.2.11 FIFO Depth Register (FDR) ................................................................................. 769 19.2.12 Receiving Method Control Register (RMCR) ...................................................... 770 19.2.13 E-DMAC Operation Control Register (EDOCR) ................................................. 771 19.2.14 Receive Buffer Write Address Register (RBWAR).............................................. 772 19.2.15 Receive Descriptor Fetch Address Register (RDFAR)......................................... 772 19.2.16 Transmit Buffer Read Address Register (TBRAR) .............................................. 772 19.2.17 Transmit Descriptor Fetch Address Register (TDFAR) ....................................... 773 19.2.18 Overflow Alert FIFO Threshold Register (FCFTR) ............................................. 773 19.2.19 Transmit Interrupt Register (TRIMD) .................................................................. 775

19.3 Operation ........................................................................................................................... 775 19.3.1 Descriptors and Descriptor List ............................................................................ 776 19.3.2 Transmission......................................................................................................... 789 19.3.3 Reception .............................................................................................................. 791 19.3.4 Transmit/Receive Processing of Multi-Buffer Frame

(Single-Frame/ Multi-Descriptor)......................................................................... 793 19.3.5 Receive FIFO Overflow Alert Signal (ARBUSY)................................................ 795

19.4 Usage Notes ....................................................................................................................... 799 19.4.1 Using of EDTRR and EDRRR ............................................................................. 799 19.4.2 Endian Support in E-DMAC................................................................................. 800 19.4.3 Prohibition for Padding Insertion Function of Internal Ethernet DMAC ............. 800 19.4.4 Usage Notes on SH-Ether EtherC/E-DMAC Status Register (EESR).................. 801 19.4.5 Usage Notes on SH-Ether Transmit-FIFO Underflow.......................................... 810

Section 20 IP Security Accelerator (IPSEC) (SH7710 Only) ...........................819

Section 21 Pin Function Controller (PFC) ........................................................821 21.1 Overview............................................................................................................................ 821 21.2 Register Configuration....................................................................................................... 822 21.3 Register Descriptions......................................................................................................... 823

21.3.1 Port A Control Register (PACR) .......................................................................... 823 21.3.2 Port B Control Register (PBCR)........................................................................... 824 21.3.3 Port C Control Register (PCCR)........................................................................... 825 21.3.4 Ethernet Controller Pin Control Register (PETCR).............................................. 826

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Section 22 I/O Ports ...........................................................................................829 22.1 Overview............................................................................................................................ 829 22.2 Register Descriptions ......................................................................................................... 829

22.2.1 Port A Data Register (PADR)............................................................................... 829 22.2.2 Port B Data Register (PBDR) ............................................................................... 830 22.2.3 Port C Data Register (PCDR) ............................................................................... 832

Section 23 User Debugging Interface (H-UDI) .................................................833 23.1 Features.............................................................................................................................. 833 23.2 Input/Output Pins ............................................................................................................... 834 23.3 Register Descriptions ......................................................................................................... 835

23.3.1 Bypass Register (SDBPR) .................................................................................... 835 23.3.2 Instruction Register (SDIR) .................................................................................. 835 23.3.3 Boundary Scan Register (SDBSR) ....................................................................... 836 23.3.4 ID Register (SDID)............................................................................................... 843

23.4 Operation ........................................................................................................................... 844 23.4.1 TAP Controller ..................................................................................................... 844 23.4.2 Reset Configuration .............................................................................................. 845 23.4.3 TDO Output Timing ............................................................................................. 845 23.4.4 H-UDI Reset ......................................................................................................... 846 23.4.5 H-UDI Interrupt .................................................................................................... 846

23.5 Boundary Scan................................................................................................................... 847 23.5.1 Supported Instructions .......................................................................................... 847 23.5.2 Points for Attention............................................................................................... 848

23.6 Usage Notes ....................................................................................................................... 848 23.7 Advanced User Debugger (AUD)...................................................................................... 848

Section 24 List of Registers ...............................................................................849 24.1 Register Addresses

(by functional module, in order of the corresponding section numbers)............................ 850 24.2 Register Bits....................................................................................................................... 865 24.3 Register States in Each Operating Mode ........................................................................... 889

Section 25 Electrical Characteristics .................................................................903 25.1 Absolute Maximum Ratings .............................................................................................. 903 25.2 DC Characteristics ............................................................................................................. 905 25.3 AC Characteristics ............................................................................................................. 907

25.3.1 Clock Timing ........................................................................................................ 908 25.3.2 Control Signal Timing .......................................................................................... 913

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25.3.3 AC Bus Timing..................................................................................................... 916 25.3.4 Basic Timing......................................................................................................... 918 25.3.5 Burst ROM Timing............................................................................................... 922 25.3.6 Synchronous DRAM Timing................................................................................ 923 25.3.7 DMAC Signal Timing .......................................................................................... 949 25.3.8 RTC Signal Timing............................................................................................... 950 25.3.9 SCIF Module Signal Timing................................................................................. 951 25.3.10 SIOF Module Signal Timing ................................................................................ 952 25.3.11 Ethernet Controller Timing................................................................................... 956 25.3.12 Port Input/Output Timing ..................................................................................... 960 25.3.13 H-UDI Related Pin Timing................................................................................... 961 25.3.14 AC Characteristics Measurement Conditions ....................................................... 963

25.4 Delay Time Variation Due to Load Capacitance ............................................................... 964

Appendix .........................................................................................................965 A. Pin States and States of Unused Pins ................................................................................. 965 B. Package Dimensions .......................................................................................................... 974 C. Note on Reset Processing Program Description ................................................................ 977

Main Revisions and Additions in this Edition.....................................................979

Index .......................................................................................................1003

Section 1 Overview and Pin Function

R01UH0338EJ0300 Rev. 3.00 Page 1 of 1006 Mar 23, 2012

SH7710, SH7712, SH7713 Group

Section 1 Overview and Pin Function

This LSI is a 32-bit reduced instruction set computer (RISC) microprocessor that is built on the SuperH architecture.

Its core is a RISC-type CPU with a Digital Signal Processor (DSP) as a functional extension. A single chip microprocessor integrates peripheral functions required for building an Ethernet system.

The LSI comprises two channels (SH7710, SH7712) or one channel (SH7713) of Ethernet controllers. They include a media access controller (MAC) and a media independent interface (MII) standard unit that conforms to the IEE802.3u standard and provide 10/100 Mbps LAN connection. The on-chip IP security accelerator enables efficient security management of network data*.

The LSI has a large capacity (32-kbyte) cache memory, 16-kbyte on-chip X/Y memory, and an interrupt controller for system configuration to enable flexible system design. It supports high-speed data transfer using an on-chip direct memory access controller (DMAC). Its external memory access support provides direct connection to various types of memory.

The strong on-chip power saving function reduces power consumption even during high-speed operation.

Note: * The IP security accelerator is incorporated only in the SH7710.

1.1 Features

The features of this LSI are shown below.

CPU:

• Original Renesas SuperH architecture • Compatible with SH-1, SH-2, and SH-3 at object code level • 32-bit internal data bus • Various groups of built-in registers

General registers: Sixteen 32-bit registers (including eight 32-bit bank registers)

Control registers: Five 32-bit registers

System registers: Four 32-bit registers

Section 1 Overview and Pin Function

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SH7710, SH7712, SH7713 Group

• Supports RISC-type instruction set Instruction length: 16-bit fixed length for improved code efficiency

Load/store architecture

Delayed branch instructions

Instruction set based on C language

• Instruction execution time: one instruction/cycle for basic instructions • Logical address space: 4 Gbytes • Space identifier ASID: 8 bits, 256 logical address spaces • Supports five-stage pipeline DSP:

• Mixture of 16-bit and 32-bit instructions • 32-/40-bit internal data bus • Multiplier, ALU, and barrel shifter • 16-bit × 16-bit → 32-bit one cycle multiplier • Large-capacity DSP data registers

Six 32-bit data registers

Two 40-bit data registers

• Supports extended harvard architecture for DSP data bus Two data buses

One instruction bus

• Maximum four parallel operations ALU, multiply, and two load/store

• Two addressing units to generate addresses for two memory access • Supports DSP data addressing modes

Increment and indexing (with or without modulo addressing)

• Zero-overhead repeat loop control • Conditional execution instructions • Supports user DSP mode and privileged DSP mode

Section 1 Overview and Pin Function

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SH7710, SH7712, SH7713 Group

Memory management unit (MMU):

• 4 Gbytes of address space, 256 address spaces (8-bit ASID) • Page unit sharing • Supports multiple page sizes

1 kbyte or 4 kbytes

• Supports 128-entry, 4-way set associative TLB • Supports software selection of replacement way and random-replacement algorithms • Contents of TLB are directly accessible by address mapping Cache memory:

• 32-kbyte cache, mixture of instructions and data • 512-entry, 4-way set associative, 16-byte block length • Write-back, write-through, LRU replacement algorithm • 1-stage write-back buffer X/Y memory:

• Three independent read/write ports 8-/16-/32-bit access from the CPU

Maximum two 16-bit accesses from the DSP

SH7710, SH7712:

8-/16-/32-bit access from the DMAC or E-DMAC

SH7713:

8-/16-/32-bit access from the DMAC

32-bit access from the DMAC or E-DMAC*4

• A total of 16 kbytes memory (8-kbyte RAM each for X- and Y-memory) Interrupt controller (INTC):

• Supports seven external interrupt pins (NMI, IRQ5 to IRQ0) • Supports fifteen level interrupt pins (IRL3 to IRL0) • Supports one interrupt request output pin (IRQOUT) • On-chip peripheral interrupt: Priority level is independently selected for each module • Supports software vector mode • Selection of falling/rising/high/low

Section 1 Overview and Pin Function

Page 4 of 1006 R01UH0338EJ0300 Rev. 3.00 Mar 23, 2012

SH7710, SH7712, SH7713 Group

User break controller (UBC):

• Address, data value, access type, and data size are available for setting as break conditions • Supports the sequential break function • Two break channels On-Chip Oscillation Circuits:

• Clock source selectable between an external supply (EXTAL or CKIO) and crystal resonator The internal clock and peripheral clock can be adjusted by setting the PLL circuit and division ratio.

• Three types of clocks generated: CPU clock (I clock): 200 MHz (max)

Bus clock (B clock): 66 MHz (max)

Peripheral clock (P clock): 33 MHz (max)

• Supports power-down modes: Sleep mo