Serial Audio Interface ( SAI )

Serial Audio Interface ( SAI )

02/07/2015 STM32L476 Technical Training

SAI Introduction The SAI interface (Serial Audio Interface) is a peripheral supporting a wide set of audio protocols thanks to its flexible architecture:

• I2S Philips standards, (Inter-IC Sound),

• I2S LSB or MSB-justified, (Variant of Inter-IC Sound),

• SPDIF Output, (Sony/Philips Digital InterFace)

• PCM, (Pulse Code Modulation)

• TDM, (Time Division Multiplexing)

• AC’97, (Audio Codec ’97 from Intel)

02/07/2015 STM32L476 Technical Training 43

SAI Features(1/2)• A SAI embeds two independent audio sub-blocks which can be:

• Transmitter and/or receiver

• Master or slave

• Synchronous or asynchronous mode between the audio sub-blocks

• Clock generator for each audio sub-block to target independent audio frequency sampling

• 8-word integrated FIFOs for each audio sub-block.

• Up to 16 slots available

• Mute mode

• Stereo/Mono audio frame capability.

• Companding mode supporting µ-Law and A-Law.


SAI Features(2/2)• Flexible serial interface:

– Configurable data justification (LSB or MSB first),

– Configurable data and slot size,

– Configurable sampling edge for the Communication clock,

– Configurable number of bits per frame,

– Configurable data position within a slot,

– Configurable frame synchronization active level,

– Configurable frame shape

• 2 DMA interfaces : one for each audio sub-block

• 2 Interrupt lines: one for each audio sub-block


SAI Block Diagram


SAIx

SAI_CK_A FS_A

SD_A

SCK_A

MCLK_A

FS_B

SD_B

SCK_B

MCLK_B

APB bus

Sync Out

Sub-Block A

FIFO

8 x 32b

Serial

Interface

Clock generator

Sub-Block A

APB Interface

IO L

ine M

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SY

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IN

DMA

Request

Interrupt

Request

SAI_CK_B

APB bus

Sub-Block B

FIFO

8 x 32b

Serial

Interface

Clock generator

Sub-Block B

APB Interface

DMA

Request

Interrupt

Request

Sync In

PLL_P

PLLSAI1_P

PLLSAI2_P

SAIxEXTCLK

STM32L476/486

Signal Dir Description

FS_A, FS_B I/O Frame synchronization

SCK_A, SCK_B I/O Bit clock sampling the serial data

SD_A, SD_B I/O Serial Data

MCLK_A, MCLK_B O Master Clock: can be requested to provide a clock to external codecs

SAI In The System


IO L

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IN

IO L

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Ma

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CM

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SAI: Internal Synchronization examples (1/3)

48

• Synchronization of 2 sub-blocks

• SLAVE full-duplex or dual lane

• MASTER full-duplex or dual lane

STM32L476/486

SAIx

SAI_CK_A FS_A (O)

SD_A (I/O)

SCK_A (O)

MCLK_A (O)

FS_B

SD_B (I/O)

SCK_B

MCLK_B

Sync Out

Sub-Block A

FIFO

8 x 32b

Serial

Interface

Clock generator

Sub-Block A

APB Interface

DMA

Request

Interrupt

Request

SAI_CK_B

Sub-Block B

FIFO

8 x 32b

Serial

Interface

Clock generator

Sub-Block B

APB Interface

DMA

Request

Interrupt

Request

Sync In

TX or RX - MASTER

TX or RX - SLAVE

Those IOs can be

used by another

function

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SAI: External Synchronization examples (2/3)

49

• Synchronization of 2 SAIs

• Up to four data lanes can work simultaneously

• Minimum IO impact thanks to internal “IO Line manager”

SAI2

SAI_CK_A FS2_A

SD2_A (IO)

SCK2_A

MCLK2_A

FS2_B

SD2_B (IO)

SCK2_B

MCLK2_B

Sync Out

Sub-Block A

FIFO

8 x 32b

Serial

Interface

Clock generator

Sub-Block A

APB Interface

DMA

Request

Interrupt

Request

SAI_CK_B

Sub-Block B

FIFO

8 x 32b

Serial

Interface

Clock generator

Sub-Block B

APB Interface

DMA

Request

Interrupt

Request

TX or RX - SLAVE

TX or RX - SLAVE

Those IOs, can be

used by another

function

STM32L476/486

SAI1

SAI_CK_A FS1_A (O)

SD1_A (IO)SCK1_A (O)

MCLK1_A (O)

FS1_B

SD1_B (IO)

SCK1_B

MCLK1_B

Sub-Block A

FIFO

8 x 32b

Serial

Interface

Clock generator

Sub-Block A

APB Interface

DMA

Request

Interrupt

Request

SAI_CK_B

Sub-Block B

FIFO

8 x 32b

Serial

Interface

Clock generator

Sub-Block B

APB Interface

DMA

Request

Interrupt

Request

Sync In

TX or RX - MASTER

TX or RX - SLAVE

Those IOs, can be

used by another

function

Synchro !!!

SAI: Synchronous mode examples (3/3)


• Several other configurations are supported:• If the internal and external synchronization is not used, each sub-block is

independent. Some examples:

• SAI_A in I2S Philips Master, SAI_B in SPDIF• SAI_A in TDM SLAVE, SAI_B in AC97• …

• If the internal or external synchronization is used, the following limitations must be respected:

• It is not possible to synchronize 2 SAI Sub-Blocks using different protocols characteristics.• It is not possible to synchronize 2 SAIs using different protocols characteristics.

FIFO Feature• Each audio block in the SAI has its own FIFO

• FIFO depth is 8 words

• CPU or DMA access to the FIFOs

• Data is right-aligned into the FIFO.

• FIFO FLUSH bit to reinitialized the FIFO pointers

• Each access in read from the FIFO will return a word (32-bit) equivalent to one data

• Each write into the DR will correspond to the FIFO to one data.

• Programmable FIFO threshold to manage data transfert: – FIFO FULL, ¾ FIFO, ½ FIFO, ¼ FIFO, FIFO EMPTY


Free Protocol Description

The Free protocol (PRTCFG = 0) must be

selected to configure the SAI in:

• I2S Philips Standard mode

• I2S MSB/LSB justified

• TDM mode

• PCM mode


Audio Clock configuration• The clock generators are used only in MASTER mode.


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When MCLK is generated (NODIV = 0) When MCLK is not generated (NODIV = 1)

(1) When MCKDIV = 0FMCLK = FSAI_CK

(1)

FRL+1 = 8, 16, 32, 64 128 or 256

FRL+1 = any values between 8 and 256

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Frame synchronization (1/2)

– The Frame length (FRL)

– The Frame active length (FSALL)

– The Frame polarity (FSPOL)


• The Channel side identification (FSDEF)

• The Frame offset (FSOFF)

Adjustable parameters

Frame synchronization (2/2)• The FS signal shape is completely configurable in order to

target the different audio protocols with their own specificities.

• The Frame Synchronization signal (FS) role depends on audio protocol:– Start of frame, like for instance the PCM/DSP, TDM, AC’97, audio

protocols,

– Start of frame and a channel side identification within the audio frame like for the I2S, the MSB or LSB-justified protocols

• The Frame synchronization active length can be set from 1 to 128 bit clock.

• The FS active length is usually:– Half of the frame length in I2S, LSB or MSB-justified modes

– one-bit wide for PCM/DSP or TDM mode

– 16-bit length in AC’97


Frame length• Master mode:

– The audio frame length can be configured up to 256 bit clock,

– If the frame length is greater than the number of declared slots for the frame, the remaining bits to be transmitted will be extended to 0 or the SD line will be released to HI-z depending the state of bit TRIS in the SAI_xCR2 register. In reception mode, the remaining bits are ignored.

• Slave mode: – The audio frame length must be used in order to specify to the slave

the number of bit clocks per audio frame sent by the external master. This feature can be used to detect signal quality errors.

• FS transitions are automatically monitored in order to detect a wrong placement of the start of frame by generating either an anticipated or late frame synchronization detection.


Audio Slot configuration(1/2)• The maximum number of slots per audio frame is fixed to 16

– Configured through bits “NBSLOT[3:0] in the SAI_xSLOTR register +1”.

• Each slot can be defined as an active slot, or not– By setting bit SLOTEN[15:0] in the SAI_xSLOTR register.

• The size of the slots is selected by setting bit SLOTSZ in the SAI_xSLOTR register.

• It is possible to define the data position into the slot (FBOFF)


Audio Slot configuration(2/2)• During the transfer of a inactive slot, 0 value will be forced on the

SD line or the SD line will be released to HI-z depending on TRIS bit setting in the SAI_xCR2 register�No request to read or write the FIFO linked to this inactive slot


Specific Feature: Mute Mode• SAI Transmitter:

– Mute mode can be selected at anytime during an on-going frame

– Mute mode starts by setting the MUTE bit in SAI_xCR2 register:

– The mute mode bit is strobed only at the end of the frame to determine if the next frame will be a mute frame or not.

– During Mute mode:• The FIFO pointers are still incremented.

• SAI still sending bit value 0 or Last values depend of MUTEVAL bit setting in SAI_xCR2

• SAI Receiver: Mute mode starts by setting the MUTE bit.– A frame is detected as MUTE when all the active slots have been

strobed with only 0 on SD line in input.

– FLAG MUTEDET is set and an interrupt generated (if enabled), when the number of consecutive Mute frame is equal to number set into MUTECNT bits In SAI_xCR2 .


Specific Feature: Companding Mode • Two companding modes are supported: μ-Law and the A-Law log

which are a part of the CCITT G.711 recommendation

• The companding standard employed in the United States and Japan is the μ-Law and allows 14 bits bits of dynamic range

• The European companding standard is A-Law and allows 13 bits of dynamic range.

• The μ-Law and A-Law formats encode data into 8-bit code elements with MSB alignment. �Companded data is always 8 bits wide

• Companding standard (μ-Law or A-Law) can be computed based on 1’s complement or 2’s complement representation depending on the CPL bit setting in the SAI_xCR2 register.


Specific Protocol Description• SPDIF Protocol

• AC’97 Protocol


SPDIF Protocol (1/5)The SAI can provide audio samples using SPDIF protocol.

• To select the SPDIF protocol, set PRTCFG[1:0] in the SAI_xCR1 register to 01.

– On SPDIF mode, only SD_x IO is used, other IOs are free.

– The data size is forced to 24 bits.

– The data are Manchester encoded (or biphase-mark)

– The SAI generates automatically the preambles

– The SAI generates automatically the parity

– The application has to handle the CS, U and V bit


SPDIF Protocol (2/5)• Symbol Rate:

– The audio sample rate (FS) can be adjusted using the following formula:


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FSAI_CK Audio sample rate

2.8224 MHz 44.1 kHz

3.072 MHz 48 kHz

6.144 MHz 96 kHz

• Data format:

• The data register must contain CS,U and V bits, plus the data

SPDIF Protocol (3/5)• The block structure is used to organize the Channel Status, and User

information.

– Each block contains 192 frames

– Each frame contains 2 sub-frames

– Each sub-frame contains 32 bits

– A preamble allows the detection of the block and sub-frame boundaries

• Preamble B detects the start of new block, and the start of a Channel A

• Preamble M detects the start of a Channel A (when it is not a block boundary)

• Preamble W detects the start of a Channel B

02/07/2015 STM32F7xx Technical Training 64

M Ch A W Ch B B Ch A W Ch B M Ch A W Ch B M Ch A W Ch B B Ch A W Ch B

X Y Z Y X Y X Y Z Y

Sub-frame Sub-frame

Frame 0 Frame 1Frame 191 Frame 0Frame 191

Start of block Start of block

SPDIF Protocol (4/5)• Each sub-frame contains

– The preamble

– Up to 24-bit data

– 4 Status bits

• V is the validity bit, it means that the current sample can be directly converted into an analog signal.

• P is the parity bit of the received sub-frame, it is used to check the received sub-frame

• U: Is the User data channel, each message is composed of 192 bits

• CS: Is the Channel Status, each message is composed of 192 bits (i.e. sampling rate, sample length….)


SPDIF Protocol (5/5)


• Preambles• The preambles are ‘violating’ the biphase-mark code rules

1 2 30

Previous half-bit = 0






Preamble “B”

Preamble “M”

Preamble “W”

1 UI 2 UI 3 UI 4 UI 5 UI 6 UI 7 UI 8 UI

Missing Transitions !!!

• Biphase-mark data encoding

AC’97 protocol(1/2)• The SAI is able to work as an AC’97 link controller.

– To select the AC 97 protocol, set bit PRTCFG[1:0] in the SAI_xCR1 register to 10.

• The number of slot is fixed to 13 slots:– Tag slot :slot 0 (16-bit),

– Data slots: slot 1 to slot 12 (20-bit)

�Bit FBOFF[5:0] in the SAI_xSLOTR register is ignored

• The frame length is fixed to 256-bit

� The SAI_xFRCR register is ignored


AC’97 protocol(2/2)


FS (SYNC)

DATA_Out TAGCMD ADDR

PCML.Front

CMDDATA

LINE 1DAC

PCM L.SUPR

PCMCenter

PCMLFE

HSETDAC

LINE2DAC

IOCTRL

PCM R.Front

PCM R.SUPR

Slot # 0 121 2 3 4 5 6 7 8 9 10 11

TAGStatusADDR

PCMLEFT

StatusDATA

LINE 1DAC RSRVD

PCMMIC

HSETDAC

LINE2DAC

IOStatus

PCM RIGHT RSRVD RSRVDDATA_In

Codec ID: to select target codec

Slot Request bits to request data from Outgoing Slots from 3 to 12

TAGPHASE DAT PHASE

0

TAG

TAG

Anticipated/Late Frame Error• In SLAVE mode, the FRL must be programmed according to the

frame length provided by the MASTER.

• FRL value is also used to check if the FS active edge occurs at the expected moment. Anticipated or Late FS error can be detected.

• To resynchronize with the master after Anticipated or Late frame detection error, four steps should be respected:1. Disable the SAI (SAIxEN = 0)

2. Flush the FIFO

3. Re-enable the SAI

SAI block will wait for the assertion of FS to restart the synchronization with master


�This detection and flag assertion can detect glitches on the SCK Clock/FS due to a noisy environment

Overrun/Underrun handling• The FIFO overrun or underrun errors occupy the same bit:

OVRUDR

• The SAI guarantees the data alignment even if underrun overrun occurs

• Example : FIFO Overrun on Slot 1


SAI Interrupt Sources

Interrupt

source

Interrupt

groupDescription

How to clear interrupt

FREQ FREQ FIFO request (FIFO threshold reached) SAI_xDR read or write (2)

OVRRUDR

ERROR

Overrun/Underrun error COVRUDR = 1

AFSDET Anticipated frame sync. detected CAFSDET = 1

LFSDET Late frame sync. detected CLFSDET = 1

CNRDY Codec Not Ready (only in AC’97 mode) CCNRDY = 1

WCKCFG Wrong frame length configuration (1) CWCKCFG = 1

MUTEDET MISC Mute detection CMUTEDET = 1


(1) When WCKCFG is set to 1, the SAI is automatically disabled (SAIxEN=0)(2) More precisely, when the FIFO level is below the threshold

I2S Philips Standard at 48 kHz, MASTER

• FSAI_CK = 12.288 MHz

72

Field name Values Comments

MCKDIV

NODIV

CKSTR

DS

SYNCEN

LSBFIRST

MODE

PRTCFG

0

0

1

5

0

0

0

0

No division

Generation of the MCLK

Signal changed on falling edge

20-bit data size

No need to sync the two SAI sub-blocks

MSb first

Master transmitter

Free protocol for I2S

FRL

FSALL

FSOFF

FSPOL

FSDEF

63d

31d

1

0

1

64 bits per frame (must be a power of 2 !!)

32 bits on each channel

First bit starts 1 bit after FS transition

FS is active LOW

Side channel identification activated for right channel

FBOFF

SLOTSZ

NBSLOT

SLOTEN

0

2

1

3

No data offset inside the slot

Slot size = 32 bits

2 slots structure (Left + right)

Slot 0 and Slot 1 are used and enabled

MS

b

LS

b

MS

b

LS

b

MS

b

Documents

Serial Audio Interface ( SAI )