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Lesson 10: Moore Machine

Computer Aided Digital DesignComputer Aided Digital DesignEE 3109Gopi K. ManneFall 2007

Sequential vs Concurrent Statements

� VHDL is inherently a concurrent language– All VHDL processes execute concurrently– Concurrent signal assignment statements are actually one-

line processesline processes

� VHDL statements execute sequentially within a process

� Concurrent processes with sequential execution within a process offers maximum flexibility

– Supports various levels of abstraction

– Supports modeling of concurrent and sequential events as observed in real systems

Sequential Statements

� Statements inside a process execute sequentially

ARCHITECTURE sequential OF test_mux ISBEGINBEGIN

select_proc : PROCESS (x,y)BEGINIF (select_sig = '0') THEN

z <= x;ELSIF (select_sig = '1') THEN

z <= y;ELSE

z <= "XXXX";END IF;END PROCESS select_proc;

END sequential;

Attributes

� Attributes provide information about certain items in VHDL

– E.g. types, subtypes, procedures, functions, signals, variables, constants, entities, architectures, configurations, variables, constants, entities, architectures, configurations, packages, components

– General form of attribute use :

� VHDL has several predefined, e.g :– X'EVENT -- TRUE when there is an event on signal X– X'LAST_VALUE -- returns the previous value of signal X– Y'HIGH -- returns the highest value in the range of Y– X'STABLE(t) -- TRUE when no event has occurred on signal

X in the past ‘t’ time

name'attribute_identifier -- read as "tick"

Sequential Circuits

� Process Statement� process(clk)

� process (sensitivity list)� Begin� If (clk=‘1’)

– Sequential statements

� end process;

D Flip-Flop

� process (CLK)– begin

if clr=‘1’– if clr=‘1’� Q<=0;

– else if CLK’event and CLK = ‘1’ � then Q<=D;

– end if;

� end Process;

2

How to find the rising edge of clock?

if RST='1' then

‘event – returns a true value of the signal if the value changes in the current simulation cycle

if RST='1' then ----elsif CLK'event and CLK = '1' then case current is ....end case; end if;

if CLK'event and CLK = '1' then

Types of State Machines

� Moore State Machines– Inputs and current state determine next state– Only current state determines output– Only current state determines output– For counters, current state is output - thus Moore

� Mealy State Machines– Inputs and current state determine next state– Inputs and current state determine output– Design is generally smaller than Moore– Input glitches can translate directly to outputs

Moore State Machines

X outputsY inputs

N bit register

combinationaloutput logic

combinationalnext statelogic

Up to 2n states (bubbles) with n state bits

N next state bits

N statebits

Mealy State Machines

X outputsY inputs

N bit register

combinationaloutput logic

combinationalnext statelogic

N statebits

N next state bits

Up to 2n states (bubbles) with n state bits

Moore State Machine Example

D A

A’

X Y

A’

D B

B’clk

State Graph and Table for Moore

next state next state

AB X=0 X=1 Z AB X=0 X=1 Z

00 10 01 0 s0 s3 s1 0

01 00 11 1 s1 s0 s2 1

s0001 00 11 1 s1 s0 s2 1

11 01 11 0 s2 s1 s2 0

01 11 01 1 s3 s2 s1 1

s1

s2

s3

0

1

0

1

Output value is tied to current state and is therefore included in bubble.Inputs determine next state.

3

Simple Mealy example – serial adder

shift register FAA

B

S

Cout

shift register

D B

B’

shift register B

CinCout

Mealy State Machine

Shift register will contain sum after completion of serialadditionShift registers

contain numbersto be added at time = 0

State Graph for Mealy example

xi yisi

s0 s1

000

011

101

010

111

100

110

001

s0 is the statewhere there is NO pending carry.

s1 is the statewhere there is a pending carry.

General Example of State Tables for Mealy

Next State Present Output (z1z2)

Present State

x1x2 = 00

x1x2 = 01

x1x2 = 10

x1x2 = 11

x1x2 = 00

x1x2 = 01

x1x2 = 10

x1x2 = 11

s0 s3 s2 s1 s0 00 10 11 01

s1 s0 s1 s2 s3 10 10 11 11s1 s0 s1 s2 s3 10 10 11 11

s2 s3 s0 s1 s1 00 10 11 01

d3 s2 s2 s1 s0 00 00 01 01

Difference between Moore and Mealy is thatpresent output only depends on current statefor Moore, while Mealy also relies on inputs.

Sequence Detector Example

� Very common interview question for design jobs� One input and one output

– input represents sequential list of 1’s and 0’s– input represents sequential list of 1’s and 0’s– output asserts if specific sequence is detected

� In this example, the prescribed sequence is 101

X = 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0 Z = 0 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0

State graph for Moore detector

s00 0

s10

1 1

X = 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0 Z = 0 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0

s20

0

1s31

01

0

State Table for Moore sequence detector

Present State

Next State

x = 0 x = 1 Output

s0 s0 s1 0s0 s0 s1 0

S1 s2 s1 0

S2 s0 s1 0

S3 s2 s1 1s0

0 0s10

1

s20

0

1s31

1

01

0

4

Transition Table for Moore detector

Present State

Next State

x = 0 x = 1 Output

0 0 0 0 0 1 00 0 0 0 0 1 0

0 1 1 1 0 1 0

1 1 0 0 1 0 0

1 0 1 1 0 1 1s0

0 0s10

1

s20

0

1s31

1

01

0A B A+ B+

Final Design of Moore Sequence Detector

00

xab

01

0 1

x

A+=

01

1110 00

xab

01

1110

0 1

0

ab

1

0 1

B+=

Z+=

Lab 8 – Sequence Detector

� Input Ports – Clk, input (X), Reset� Output Ports – output (Z), Statearchitecture behave of SEQDET is type STATES is (S1, S2, S3, S4);signal current: STATES;begin process (CLK, rst)

Process (sensitivity list) – executes when a signal in sensitivity list changesBeginEnd process – after finishing execution goes back and waits for a signal in

sensitivity list changes

Lab 9

� 2 – waveforms– Sequence example

– With reset HIGH in the middle

For Example: X = 0 0 0 1 0 1 0 0 0 1 1 1 0 1 0 0Z = 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 0

VHDL

architecture --------- of --------- is

type STATES is (S0, S1, S2, S3);

signal state: STATES;

case state iswhen S0 =>

------If (x = ‘0’) then state <= ….signal state: STATES;

begin

process(clk,reset)

if reset = ‘1’

-------

elseif (clk’event and clk=1)

If (x = ‘0’) then state <= ….else ……endif…………

when others => null;end case;end if;end process;end ….