Title: Introduction to HDL Modeling, Verification and Implementation of Sequential Digital Circuits.

Abstract: The objective of this experiment is the following:

1. Understanding the design & operation of D type flip-flops and registers.

2. The effects of synchronous load signals and SCLR signals on device.

3. Effects the global asynchronous set/reset signals PRLD and GSR on device.

4. To understand the interaction between combinational segment (Next-Q) and sequential segment

(Present State) of D flip-flops.

5. Simulate the design in Active-HDL simulator and synthesize it using Precision RTL synthesizer and

see its behavior in Xilinx8x CoolRunnerII XC2C256-TQ144 CPLD silicon through ISE WebPack place

and route tool.

6. Observe & compare the result and timing diagram of Functional & Post Fit Simulation.

Introduction: Sequential logic circuits are sensitive to active edges of the system clock. They read data just before

active clock edges and perform their operation just after active clock edges. At all other times it holds the

previous unless there is no active asynchronous reset. So, sequential logic circuits have memory [1]. The

delay through sequential logic is called Clock to Q (C2Q) delay. To reflect the true nature of sequential

logic hardware, Verilog HDL and SystemVerilog HDL always blocks for sequential logic are sensitive to

only clock signals, unless there is an asynchronous reset available.

Theory & Methodology:

Positive Edge Triggered D-Flip Flop: The D type flip-flop has only one input (D=Data) apart from the clock. The INDETERMINATE state is

avoided with this flip-flop.

When the clock goes high, D (0 or 1) is transferred to Q. When the clock goes low, Q remains unchanged

(Hold). Q stores the data until the clock goes high again. Will if there will be a SCLR or ACLR then the

output will goes to zero [2].

Internal Structure of Sequential Device:

Most sequential logic except perhaps the simplest ones such as a D register without any control signals

(Clr, Load etc.) must contain a combinational segmentNext_Q logicin addition to D flip-flops inside

its registerswhich are sequential logic. The Next_Q logic calculates the possible future values of Q by

looking at control inputs (i.e. Clr, Load), data inputs (D) and current output (Q).

Positive edge triggered, Clearable, Loadable D-Register with SCLR and ACLR, where

priority of SCLR is higher than Load:

CLOCK SCLR LOAD Qt + REMARK

RISING EDGE 0 0 Qt - HOLD

RISING EDGE 0 1 D LOAD

RISING EDGE 1 0 0 SYNCH. RESET

RISING EDGE 1 1 0 SYNCH. RESET

LEVEL -1 X X Qt - HOLD

FALLING EDGE X X Qt - HOLD

LEVEL 0 X X Qt - HOLD

Xilinx CPLDs and FPGAs have a Global Asynchronous Set-Reset signal- PRLD for Xilinx CPLDs and

GSR for Xilinx FPGAs that sets or resets all flip-flops in a configured design at the start of operation.

This ensures that that the device is not trapped in an unknown state initially. Xilinx FPLDs trigger this

PRLD/GSR at power up for 100 ns, during which time all the flip-flops are either set or reset and it is

never high again. The default setting for PRLD/GSR is reset; so unless the designer changes this setting,

all flip-flops would be reset at the start. For safe timing or Post-fit simulation, the post-fit simulation

should include Xilinxs global Asynchronous Set-Reset signal PRLD/GSR [3].

Pre-Lab Homework: The difference between combinational and sequential logic are as follows:

Combinational logic Sequential logic

Output is function of input. Output is function of input and previous output.

Whenever one of the input changes the value

output may be updated.

Whenever one of the inputs change just prior to

active edge of the clock output may be updated.

There cant be any output feedback. There must output feedback

Dont have memory. Has memory.

Basic building blocks are basic feed forward logic

gates.

Basic building block are flip-flop in most

sequential logic.

Level sensitive. Edge sensitive.

Apparatus: 1. Design Entry Tool - Active HDL 9.3 Expert Addition (Aldec)

2. Synthesizer Tool - Precision RTL 2011A.10 (Mentor Graphics)

3. Place and Route Tool - Xilinx ISE Webpack 8.2 (Xilinx)

4. Target Technology - Xilinx8x CoolRunnerII CPLD

Design & Simulation Data:

HDL Source Code:

Functional Simulation:

Synthesis Result:

Post Fit Simulation:

Adding .glbl & .tb file:

Adding components to waveform:

Timing Diagram:

Area Report:

Appendices: HDL Source Code:

`timescale 1 ns / 1 ps

module DREG_3BIT_SCLR

(input wire CLOCK,

input wire SCLR,

input wire LOAD,

input wire [2:0] D,

output reg [2:0] Q

);

always @ (posedge CLOCK)

begin

if (SCLR) Q

end

end

initial

begin SCLR = 0; LOAD = 1;

fork

forever begin

#800 LOAD = ~ LOAD;

end forever

begin

#1600 SCLR = ~ SCLR; end

join

end

initial

begin

D = 2;

forever begin

#70 D = D + 1;

end end

time RUN_TIME= 4200;

initial

begin #RUN_TIME;

$finish;

End

endmodule

Area Report: ***************************************

Device Utilization for 2c256tq144

***************************************************************

Resource Used Avail Utilization

--------------------------------------------------------------- IOs 9 118 7.63%

Gates 5 6400 0.08%

---------------------------------------------------------------

******************************************************

**

Library: work Cell: DREG_3BIT_SCLR View: INTERFACE

******************************************************

**

Cell Library References Total Area

AND2 xcr2 3 x 1 3 gates

FDCPE xcr2 3 x 1 3 Flip Flops GND xcr2 1 x

IBUF xcr2 6 x

INV xcr2 1 x 1 1 gates OBUF xcr2 3 x

OR2 xcr2 1 x 1 1 gates

Number of ports : 9

Number of nets : 24

Number of instances : 18 Number of references to this view : 0

Total accumulated area : Number of Flip Flops : 3

Number of gates : 5 Number of accumulated instances : 18

Result: The Clock-to-Q Delay including the output buffer delay seems to be 6136 ps for the CoolRunner2 CPLD.

From the plot for functional simulation (FS) shown above it has been seen that when the positive

edge of the clock arises, the output Q becomes updated if the LOAD signal is high just after the rising

pulse of the clock and gets reset when SCLR signal is high just after the rising edge of the clock. The

timing simulation (PFS) shown above it has been seen that the output gets updated every positive clock

edge but there is clock-to-Q delay which is about 6136 ps.

The PRLD signal shown the global reset delay defined each FPGA boards. During the period when its

high the output Q will be 0 no matter what clock pulse it is. This is done to make sure that the FPGA

doesnt get stuck at uninitialized parameter of input and output.

Reference: [1] [3] Introduction to HDL Modeling and Silicon Realization with CPLDs or FPGAs using EDA

tools(Active-HDL (Aldec), Precision RTL (Mentor Graphics) and ISE WebPack (Xilinx))- AIUB Lab

Manual by Shahriyar M. Rizvi, Assistant Professor, Faculty of Engineering, AIUB.

[2] Electronic Tutorials [http://www.electronics-tutorials.ws/sequential/seq_1.html] [Accessed: 16.03.15]