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OPERATIONAL AMPLIFIERS (OP-AMPS)
SECTION I
Aim: To Study Operational Amplifiers.
Theory:
Introduction to the Operational Amplifiers:
An operational amplifier is a direct coupled high gain amplifier usually consisting of one or more
differential amplifiers followed by a level shifter stage and output stage. The output stage is
generally a push-pull complementary symmetry pair. An operational amplifier is available as a
single integrated circuit package.
The operational amplifier is a versatile device that can be used to amplify DC as well as AC
input signals and was originally designed to perform mathematical operations such as addition,
subtraction, multiplication and integration. Thus the name operational amplifier stems from its
original use for these mathematical operations and is abbreviated to Op-amp. With the addition
of suitable external feedback components, the modern day op-amp can be used for a variety of
operation such as ac and dc signal amplification, active filters, oscillators, comparators,
regulators and others.
Block Diagram of a Typical OP-AMP:
Commercial IC op-amps usually consist of four cascaded blocks as shown in fig.(a). Since an op-
amp is a multistage amplifier, it can be represented by a block diagram as shown in figure:
Input Stage:
The input stage is the dual Input, balanced output differential amplifier. This stage provides most
of the voltage gain of the amplifier and also establishes the input resistance of the op-amp.
Intermediate Stage:
The Intermediate stage is usually another differential amplifier, which is driven by the output of
the first stage. In most amplifiers the intermediate stage is dual input unbalanced output.
Level Shifter: As direct coupling is used, the DC level at the output of the intermediate stage is well above
ground potential. Therefore, generally, the level translator (shifter) circuit is used after the
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intermediate stage to shift the DC level at the output of the intermediate stage downward to zero
volts with respect to ground.
Output Stage: The final stage is usually a push-pull complementary amplifier output stage. The output stage
increases the output voltage swing and raises the current supplying capacity of the op-amp. A
well designed output stage also provides low output resistance.
Schematic Symbol of Op-amp:
The most widely used symbols for the circuit with two inputs and one output. Since the input
differential amplifier stage of op-amp is designed to be operated in the differential mode, the
differential inputs are designated by the (+) and (-) notations. The (+) input is the non inverting
input. An AC (or DC voltage) applied to this input produces an in-phase (or same polarity) signal
at the output. On the other hand the (-) input is the inverting input because an ac signal (or dc
voltage) applied to this input produces an 180˚out of phase (or opposite polarity) signal at the
output. All the input and output voltages to op-amp are measured with respect to ground. Op-
amp amplifies the signal with gain ‘A’ which is a large signal voltage gain specified on the data
sheet for op-amp. Hybrid ICs are further classified as thin film or thick film, depending on the
method used to form the resistors, capacitors and related interconnections on the substrate. When
suitable material is evaporated on a substrate in forming resistors, capacitors and connections, a
thin film hybrid IC is obtained. On the other hand, in a thick film hybrid IC the resistors,
capacitors and interconnections are etched on the substrate by silk screening.
Manufacturing Designation for ICs:
Each uses a specific code and assigns specific type number to the ICs it produces. That is, each
manufacture uses its own identifying initials followed by its own type number. For e.g. the 741
type of internally compensated op-amp was originally manufactured by Fairchild and is sold as
the μA741, where “μA “represents the identifying initials used by Fairchild. Initials used by
some of the well known manufacturers of linear ICs are as follows:
Fairchild μA
μAF
National Semiconductor LM LH
LF
TBA
Motorola MC
MFC
RCA
CA
CD
Texas Instruments SN
Signetics N/S,NE/SE
Burr Brown BB
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The initials used by manufacturers in designing digital ICs may differ from those used for linear
ICs .For eg. DM and CD are the initials used for digital monolithic and CMOS digital IC original
s respectively by National Semiconductors. In addition to producing to their own ICs, a number
of manufacturers also produce one other popular IC. In second sourcing such ICs, the
manufacturers usually retain the original type number of the IC in their own IC designation. For
eg, Fairchild‟s μA741 is also manufactured by various other manufacturers under their own
designation, as follows:
National Semiconductor LM 741
Motorola MC1741
RCA CA3741
Texas Instruments SN52741
Signetics N5741
Note that the last three digits in each manufacturer‟s designation are 741. All these op-amps have
the same specifications and so behave the same. These ICs have different classes such as A, C,
E, S and SC. For e.g. 741, 741A, 741C, 741E, 741S and 741SC.
1. The 741 is a military grade op-amp (operating Temp. range: -55˚ to 125˚C)
2. The 741C is a commercial grade op-amp (operating Temp. range: 0˚ to 70/ 75˚C)
3. The 741A and 741E are improved versions of 741 and 741C, respectively, in that they have
improved electrical specifications over their counterparts.
4. The 741C and 741E are identical to 741 and 741A except that the former have their
performance guaranteed over 0˚ to 70/ 75˚C temperature instead of -55˚ to 125˚C.
5. The 741S and 741SC are military and commercial grade op-amps, respectively, with higher
slew rates than 741 and 741C.
SSI, MSI, LSI and VLSI Packages:
ICs are classified as per number of components (or gates, in case of digital ICs) integrated on the
same chip, as follows:
Small scale Integration SSI< 10 components
Medium scale Integration MSI<100 components
Large scale Integration LSI>100 components
Very Large scale Integration VLSI>1000 components
In the SSI Package, the number of components integrated on the same chip is typically smaller
than 10. Most of the arrays fall in this group .In the MSI IC, the number of components is
smaller than 100, whereas LSI package includes greater than 100 components .Almost all the
linear integrated circuits and integrated combination logic circuits are MSI package. Most of the
sequential logic circuit is of the LSI type .In the VLSI package, the number of components
formed on the same chip is typically greater than 1000.
Integrated Circuits (ICs) Package Types:
There are basically three types of IC packages as follows:
1) Flat pack
2) Metal can or transistor pack
3) Dual-in-line package (DIP)
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In Flat pack the chip is enclosed in rectangular ceramic case with the terminal leads extending
through the sides and ends as shown in figure. The flat pack comes with 8, 10, 14 or 16 leads.
These leads accommodate the power supplies, inputs and outputs and several special connections
required to complete the circuit.
In the Metal can or Transistor pack the chip is encapsulated in metal or plastic case. The
Transistor pack is available with 3 , 5, 8 ,10 or 12 pins .Most of the voltage regulator ICs, such as
LM117, have 3 pins .Power op-amp and audio power amplifier is usually available in 5 pin
packages. The metal can package is best suited for power amplifier as metal is good heat
conductor and consequently has better dissipation capability than the flat pack or dual in line
package. In addition, the metal can package permit the use of external heat sink. Most of the
general purpose op-amps come in 8, 10, or 12 pin package.
In Dual -line package (DIP), the chip is mounted inside a plastic or ceramic case, as shown in
figure. The DIP is the most widely used package type as it can be mounted easily. The 8 pin
dual-in-line packages are referred to as mini DIPs. Dual-in-line packages are also available with
12, 14, 16 and 20 pins. In general, as the density of components integrated on the same chip
increases, the number of pins also goes up. This is especially true in digital ICs. For e.g. there 64
pins on the MC6800 microprocessor chip, compared to 40 pins MC6800 microprocessor. Table
below is a summary of the number of pins and types of packages in which linear integrated
circuits are presently available. On the other hand, almost all digital ICs are DIP packages .Metal
can package are also available with dual-in-line formed leads (DIL –CAN) and with radial form
leads as shown in figure. Different outlines exists within each package style to accommodate
various die sizes and number of pins (leads) .for e.g. TO-100, TO-101 are some of the outlines
available in transistor pack.
Selecting an IC Package:
If the IC is used for experimentation/bread boarding purpose the best choice is DIP package as it
is easy to mount. The Mounting does not require bending or soldering of the leads. The DIP is
also suitable for mounting on PCB because of its lead construction and more spacing between
the leads. Generally the ceramic DIP is more expensive than the plastic DIP, but the ceramic one
dissipates more heat. The flat pack is more reliable and lighter than a comparable DIP package
and is so, common suited foe air borne application. On the other hand, the metal can is the best
choice if the IC is to be operated at the relatively high power and is expected to dissipate
considerable heat. When all the three packages are available for specific application, the choice
can be made based on the relative cost and ease of fabrication /bread boarding the IC. Some
application may not allow the choice of package as the IC is available in only one package style.
Temperature Ranges:
All ICs manufactured fall into one of the three basic temperature grades:
1. Military Temperature range: -55˚ to 125˚C (or -55˚ to +85˚C)
2. Industrial Temperature range: -20˚ to 85˚C (or -40˚ to +85˚C)
3. Commercial Temperature range: 0˚ to 70˚C (or 0˚ to +75˚C)
Individually datasheets specifies exact value of IC parameters and condition under which these
parameters are defined. The std. practice is to specify the IC parameter at room temperature i.e.
is 25˚C. The military and commercial grade ICs differ in specification for supply voltage , input
current and voltage offsets and drifts , the voltage and other parameters .The military grade
devices are almost always of superior quality with tightly control parameters and consequently
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cost more. Commercially grade ICs have the worst tolerances among the three types but are the
cheapest. In short performance and cost are the important factors in selecting an IC.
Ordering Information:
Generally in ordering an IC the following Information must be specified: Device type, Package
type and Temperature range. The Device type is a group of alphanumeric characters such as:
μA741, LM 741, MCI 741.These characters refer to the datasheet that specifies the devices
functional and electrical characteristics. The basic package type- Flat type, transistor pack or DIP
is represented by one letter. The Military Industrial or commercial is either numerically specified
or included in the device type number or represented by a letter. Unfortunately the manufacturers
do not have consistent format by which the ordering information should be specified. For e.g. the
ordering information for Fairchild‟s 741 Mini DIP with commercial temperature is as follows:
μA 741 T C
Device Type Package Type Commercial Temperature
(Op-amp) (Mini DIP) range (0˚ to 70˚C)
On the other hand, the ordering information format for a typical Motorola IC is as follows:
MC 34001 P 0˚ to 70˚C
Device Type Package Type Temperature range
(Op-amp) (Plastic DIP) (0˚ to 70˚C)
In National Semiconductor ICs the Temperature range is denoted in the device numbers itself:
LM 101A F
Device Type Package Type
(Op-amp) & Temperature range (Plastic DIP)
Device Identification:
The IC is identified by marking the device type, number on the face of IC. This number is
usually accompanied by the date code, indicating the year and week the device was
manufactured .figure shows an e.g. of Fairchild‟s device identification method.
Power Supplies for Integrated Circuits:
Most linear ICs use one or more differential amplifier stages, and differential amplifiers require
both a positive and a negative power supply for proper operation of the circuit. This means that
most linear ICs need both a positive and a negative power supply .A few linear ICs (especially
earlier op–amps) use unequal power supplies, and some ICs require only a positive supply. For
example, the 702 op-amps require unequal power supplies, whereas the 324 op-amps require
only a positive supply. When a single supply is used, it is normally necessary to connect an extra
circuit to the IC. Some dual supply op-amp ICs can also be operated from a single supply
voltage, provided that a special external circuit is used with it. Digital IC s, on the other hand,
generally requires only one positive supply voltage. [(An exception is the emitter-coupled logic
(ECL) IC] The two power supplies required for a linear IC are usually equal in magnitude, +15V
and – 15 V, for example .This power supply voltages must be referenced to a common point or
ground. Unfortunately, as in the case of ordering information, manufactures do not agree on
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power supply labeling. For example, Fairchild uses V+ to indicate the positive voltage and V- to
indicate the negative voltage or Vs to indicate both positive and negative voltages. On the other
hand, Motorola uses the symbols +Vcc and –VEE (as in discrete transistor circuits) to represent
positive and negative voltages, respectively. We will follow Motorola‟s notation for the power
supplies. Figure shows power supply connections for the 741 or 351 op-amps .The numerals
adjacent to the terminals are pin numbers. Thus, for the 741 or 351 op-amp, pin 7 is a positive
supply pin and pin 4 is a negative supply pin. The remaining pins on the 741 or 351 are omitted
for the sake of simplicity. Instead of using two separate power supplies, we can use a single
power supply to obtain +Vcc and –VEE, as shown in the figure1.In figure (a) below the value of
the total resistance(2R) should be ≥ 10KΩ so that it does not draw much current from the supply
Vs. The two capacitors provide for decoupling (bypass) of the power supply; they range in value
from 0.01 to 10μF. In figure (b) below Zener diodes are used to obtain symmetrical supply
voltages .The value of Rs should be chosen such that it supplies sufficient current for the diodes
to operate in the avalanche mode. The potentiometer is used in figure (c) below to assure
equality between +Vcc and –VEE values. Diodes D1 and D2 are intended to protect the IC if the
positive and negative leads of the supply voltage Vs are accidently reversed.
SECTION II
Aim: To Study the Transfer Characteristics of Op-amps.
Theory:
The equivalent circuit includes A , Ri , Ro, where A*Vid is the equivalent Thevenin‟s voltage
source and Ro is the Thevenin‟s equivalent resistance looking back into the output terminal of
op-amp .The equivalent circuit is useful in analyzing the basic operating principle of op-amp and
in observing the effect of feedback arrangements.
The output voltage is:
V0 = A* Vid =A*(V1-V2) ……………………….. (1)
Where,
A = Large signal voltage gain.
Vid = difference input voltage.
V1= Voltage at Non- inverting input terminal.
V2= Voltage at Inverting input terminal.
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The equation (1) indicates that the output voltage VO is directly proportional to algebraic
difference between two input voltages .The op-amp amplifies the difference between the two
input voltages. For this reason the polarity of output voltage depends on the polarity of the
difference voltage.
Ideal Voltage Transfer Curve:
Equation (1) is the basic op-amp equation , in which the output offset voltage is assumed to be
zero .the graphic representation of equation (1) is as shown in the figure below, where the output
voltage is plotted against difference voltage keeping “A” i.e. gain constant. Note however that
the output voltage cannot exceed the positive and negative saturation voltages .these saturation
voltages are specified by an output voltage swing rating of the Op-amp for a given values of
supply voltages. This means that the output voltage is directly proportional to the input
difference voltage only until it reaches the saturation voltages and that thereafter output voltage
remains constant.
Procedure:
To plot the Transfer Characteristic
1. Build the circuit shown below .Use ±5V to power up the op amp.
2. Connect node VX to the Channel 1 of the scope, and VY to Channel 2.
3. Use XY mode and inverted display for Channel 1.
4. For excitation, use 10Vpp sinusoid.
5. With switches SWP and SWN closed, record the transfer characteristic.
6. With switch SWN open and switch SWP closed, record the transfer characteristic.
SECTION III
Aim: To Study different Op-amp parameters.
Theory:
Op- amp performance parameters
1. Input Bias Current (IB)
An Input bias current IB is defined as the average of the two input bias currents, Ib1 and Ib2, is
given by
𝐼𝐵 =𝐼𝑏1 + 𝐼𝑏2
2
Where
Ib1 = DC bias current flowing into non inverting input
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Ib2 = DC bias current flowing into inverting input
Input Bias current
2. Input offset current (Iio)
An input offset current is defined as the algebraic difference between the two input bias currents
Ib1 and Ib2, is given by
𝐼𝑖𝑜 = 𝐼𝑏1 − 𝐼𝑏2 Where
Ib1 = DC bias current flowing into non inverting input
Ib2 = DC bias current flowing into inverting input
3. Input Offset voltage:
Input offset voltage Vio is the differential input voltage that exists between two input terminals
of an op-amp without any external input voltage applied .In other words, it is the amount of the
input voltage that should be applied between two input terminals in order to force output voltage
to zero.
Input Offset voltage
4. Common Mode Rejection Ratio (CMRR):
The CMRR is defined in several essentially equivalent ways by the various manufactures.
Generally; it can be defined as the ratio of differential voltage gain Ad to the common mode
voltage gain Acm.
𝐶𝑀𝑅𝑅 =𝐴𝑑
𝐴𝑐𝑚
The differential voltage gain Ad is same as large signal voltage gain A, which is specified on the
data sheet .However, the common mode voltage gain can be determined from the circuit using
the equation:
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𝐴𝑐𝑚 =𝑉𝑜𝑐𝑚
𝑉𝑐𝑚
where
Vocm=O/P common mode voltage
Vcm = I/P common mode voltage
Acm = common mode voltage gain
Generally, CMRR value is large and is specified in dB, where
𝐶𝑀𝑅𝑅 𝑑𝐵 = 20 log𝐴𝑑
𝐴𝑐
5. Power Supply Rejection Ratio (PSRR):
The change in an op-amp input offset voltage Vio caused by variation in supply voltage is called
as supply voltage rejection ratio (SVRR). A variety of terms equivalent to SVRR are used by
different manufacturers such as power supply rejection ratio (PSRR) and the power supply
sensitivity (PSS).
These terms are expressed in the microvolt/volt or in dB. If we denote the change in supply ΔV
and the corresponding change in input offset voltage by ΔVio, SVRR can be defined as follows:
𝑆𝑉𝑅𝑅 =∆𝑉𝑖𝑜
∆𝑉
6. Slew Rate (S.R.):
Slew rate (S.R.) is defined as maximum rate of output voltage per unit of time and is expressed
in volts per microseconds.
𝑆.𝑅. =𝜕𝑉𝑜
𝜕𝑡
=∆𝑉
∆𝑡
Slew rate indicates how rapidly the output of op-amp can change in response to change in the
input frequency.
7. Differential Input (Ri) and Output Resistance (Ro):
Differential input resistance is the equivalent resistance measured at either the inverting or non-
inverting input terminal with other input terminal grounded. It is denoted by Ri. Differential
output resistance Ro is the equivalent resistance measured between the output terminals of the
op-amp terminal ground.
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8. Input Capacitance (Ci):
Input Capacitance (Ci) is the equivalent capacitance that can be measured at inverting or non-
inverting terminal with the other terminal connected to ground.
9. Output Voltage swing:
The op-amp output voltage swing is limited .It gets decided by the supply voltage. It never
exceeds the limit +Vcc and –Vee. Above these values op-amp output gets saturated. Infact the
output voltage swing indicates the values of positive and negative saturation voltages of opamp.
10. Output short circuit current (Isc):
Nobody would deliberately want to short the output terminal of the op-amp to ground, but if such
an event were to happen accidently, the current through the short circuit would certainly be much
higher in value than either Ib or Iios. This high current may damage the op-amp if it does not
have short circuit protection. The 741 family op-amps do have short circuit protection built in.
The short circuit current is Isc = 25mA for 741 IC op-amp .This means that the built in short
circuit protection is guaranteed to withstand 25mA of current in protecting the op-amps.
11. Supply current (Is):
Supply current (Is) is the current drawn by the op-amp from the power supply .This parameter is
not given on most of the op-amp datasheets. For the 741 IC op-amp the supply current is 2.8mA.
12. Power Consumption (Pc):
Power consumption (Pc) is the amount of quiescent power (Vin= 0V) that must be consumed by
op-amp in order to operate properly.
13. Large Signal Voltage gain:
Since the op-amp amplifies the difference voltage between two input terminals, the voltage gain
of the amplifiers is defined as, voltage gain = output voltage / differential input voltage. That is
A = Vo / Vid. Because output signal amplitude is much larger than the input signal, the voltage
gain is commonly called as large signal voltage gain.
14. Thermal Drift:
The average rate of change of input offset voltage per unit change in temperature is called as
thermal voltage drift and is denoted by Δ Vio/Δ T. It is important to note that the drift is not a
constant value .That is it is not uniform over a specified operating temperature range.
Electrical Characteristics of μA 741 𝑉𝑠 = ±15𝑣,𝑇𝐴 = 25°𝐶
Sr. No. Characteristics Ideal values Practical values
1 Open loop voltage Gain
(Av)
∞ 2×10^5(106dB)
2 Input Resistance (Ri)
∞ 2MΩ ;BJT
1GΩ ;FET
3 Output Resistance (Ro)
0 75Ω
4 Input Offset voltage
0 20mV
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5 Input offset Current
_ 200nA
6 Input Bias Current
_ 500nA
7 Common Mode
Rejection Ratio(CMRR)
∞ 90dB
8 Supply Voltage
Rejection Ratio(SVRR)
0 150µv/v
9 Slew Rate (SR)
∞ 0.5V/µs
Conclusion:
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EXPERIMENT NO.:
TITLE:
BRANCH:
BATCH:
ROLL NO.:
DATE:
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INVERTING, NON-INVERTING, ADDER AND SUBTRACTOR MODES OF OP-AMP
Aim: Study of OP-AMP in Inverting, Non-Inverting, summer and Subtractor mode.
Apparatus: OP-AMP IC-741, Breadboard, Dual Power supply, Function Generator, CRO,
Resistors, and jumper wires.
Theory:
I. INVERTING AMPLIFIER:
The signal which is to be amplified is applied at the inverting (-) terminal of the OP-AMP. The
amplified output signal will be 180º out of phase with the input signal, in other words the output
signal is inverted. Therefore amplifier is known as inverting amplifier. The circuit is shown in
fig.1 (a). The output voltage Vo is fed back to the inverting input terminal through the Rf-R1
network where Rf is the feedback resistor. Input signal Vi (AC or DC) is applied to the inverting
input terminal through R1 and non-inverting input terminal of op-amp is grounded. The signal to
be amplified (VS) has been connected to the inverting terminal via the resistance R1. The other
resistor Rf, connected between the output and inverting terminal is called as the feedback
resistance. It introduces a negative feedback. The non-inverting (+) terminal is connected to
ground. As the OP-AMP is ideal one, its open loop voltage gain AV= -∞ and input resistance
Ri=∞. The negative sign for AV is due to the inverting configuration. The input and output
voltage waveforms are as shown in fig1 (b). Output is an amplified and inverted version of the
input signal VS.
Analysis: As Vd=0, node „A‟ is at ground potential and the current i1 through R1 is
𝑖1 =𝑉𝑖𝑅1
Also since op-amp draws no current, all the current flowing through R1 must flow through Rf.
The output voltage,
𝑉𝑜 = −𝑖1𝑅𝑓
= −𝑉𝑖𝑅𝑓
𝑅1
Hence, the gain of the inverting amplifier (also referred as closed loop gain) is,
𝐴𝐶𝐿 =𝑉𝑜𝑉𝑖
= −𝑅𝑓
𝑅1
Alternately, the nodal equation at the node „A‟ in fig.1 (a) is
𝑉𝑎 − 𝑉𝑖𝑅1
+𝑉𝑎 − 𝑉𝑜𝑅𝑓
= 0
Where va is the voltage at node „A‟. Since node „A‟ is at virtual ground Va =0. Therefore, we get,
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𝐴𝐶𝐿 =𝑣𝑜
𝑣𝑖
= −𝑅𝑓
𝑅1
The negative sign indicates the phase shift of 180o between vi and vo.
Practical circuit
Figure1 (a): Circuit Diagram
Input and Output Waveform:
Figure1 (b): Input and Output waveforms in inverting mode
PROCEDURE:
Rf
10kΩ
R1
1kΩ
VCC 15V
VEE -15V
U1
741
3
2
4
7
6
5 1
XSC1
A B
Ext Trig +
+
_ _ + _
XFG1
Ro 1kΩ
SNJB COE, CHANDWAD
1) Design a circuit and connect it as shown in fig1 (a).
2) Apply sine wave input and observe the output on CRO.
3) Note observation by varying the amplitude of input and take the readings and find Av.
4) Draw the input- output waveforms.
OBSERVATIONS TABLE:
Sr. No. Input Voltage Vin
(mV)
Output Voltage Vo
(V)
Gain
Av
1
2
3
4
5
CALCULATIONS:
1) Vin= Vo=
𝐴𝑣 =𝑉𝑜
𝑉𝑖𝑛
= −𝑅𝑓
𝑅1
=
2) Vin= Vo=
𝐴𝑣 =𝑉𝑜
𝑉𝑖𝑛
= −𝑅𝑓
𝑅1
=
3) Vin= Vo=
𝐴𝑣 =𝑉𝑜
𝑉𝑖𝑛
= −𝑅𝑓
𝑅1
=
4) Vin= Vo=
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𝐴𝑣 =𝑉𝑜
𝑉𝑖𝑛
= −𝑅𝑓
𝑅1
=
5) Vin= Vo=
𝐴𝑣 =𝑉𝑜
𝑉𝑖𝑛
= −𝑅𝑓
𝑅1
=
II. NON-INVERTING AMPLIFIER
If a signal is applied to the non-inverting input terminal and feedback is given as shown in fig.2
(a), the circuit amplifies without inverting the input input signal. Such a circuit is called non-
inverting amplifier. Here the signal which is to be amplified is applied to the non-inverting (+)
terminal of an Op- Amp. The input and output voltages are in phase (0º phase shift) with each
other. The negative feedback is incorporated in this circuit via the feedback resistor Rf which is
connected between the output and inverting terminal of Op- Amp.
As the differential voltage Vd at the input terminal of op- amp is zero, the voltage at node „a‟ in
fig.2 (a) is Vi, same as the input voltage applied to non-inverting input terminal.
Analysis: Now Rf and R1 forms a potential divider. Hence,
𝑉𝑖 =𝑉𝑜
𝑅1 + 𝑅𝑓𝑅1
as no current flows into the op- amp, 𝑉𝑜
𝑉𝑖=
𝑅1 + 𝑅𝑓
𝑅1
= 1 +𝑅𝑓
𝑅1
Thus, for non-inverting amplifier the voltage gain,
𝐴𝐶𝐿 =𝑉𝑜
𝑉𝑖= 1 +
𝑅𝑓
𝑅1
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Practical Circuit:
Figure2 (a): Circuit Diagram
Input and Output Waveforms:
Figure2 (b): Input and Output Waveforms in non-inverting mode
PROCEDURE:
1) Design a circuit and connect it as shown in fig2 (a).
2) Apply sine wave input and observe the output on CRO.
3) Note observation by varying the amplitude of input, take the readings and find Av.
4) Draw the input- output waveforms.
Rf
10kΩ
R1
1kΩ
VCC
15V
VEE
-15V
U1
741
3
2
4
7
6
51
XSC1
A B
Ext Trig+
+
_
_ + _
XFG1
R2
1kΩ
Ro1kΩ
SNJB COE, CHANDWAD
OBSERVATIONS TABLE:
Sr. No. Input Voltage Vin
(mV)
Output Voltage Vo
(V)
Gain
Av
1
2
3
4
5
CALCULATIONS:
1) Vin= Vo=
𝐴𝑣 =𝑉𝑜
𝑉𝑖𝑛
= 1 +𝑅𝑓
𝑅1
=
2) Vin= Vo=
𝐴𝑣 =𝑉𝑜
𝑉𝑖𝑛
= 1 +𝑅𝑓
𝑅1
=
3) Vin= Vo=
𝐴𝑣 =𝑉𝑜
𝑉𝑖𝑛
= 1 +𝑅𝑓
𝑅1
=
4) Vin= Vo=
𝐴𝑣 =𝑉𝑜
𝑉𝑖𝑛
= 1 +𝑅𝑓
𝑅1
SNJB COE, CHANDWAD
=
5) Vin= Vo=
𝐴𝑣 =𝑉𝑜
𝑉𝑖𝑛
= 1 +𝑅𝑓
𝑅1
=
3. SUMMER AMPLIFIER
Op- Amp may be used to design a circuit whose output is the sum of several input signals. Such
a circuit is called a summing amplifier or a summer.
Analysis: A typical summing amplifier with three input voltages V1, V2 andV3, three input
resistors R1, R2, R3 and a feedback resistors Rf is shown in fig.3 (a). Let the voltages at (-) input
terminal will also be Va. The nodal equation at node „a‟ is given by
𝑉1 − 𝑉𝑎
𝑅1+𝑉2 − 𝑉𝑎
𝑅2+
𝑉3 − 𝑉𝑎
𝑅3= 0
From which we have,
𝑉𝑎 =
𝑉1𝑅1 +
𝑉2𝑅2 +
𝑉3𝑅3
1𝑅1 +
1𝑅2 +
1𝑅3
The Op- amp and two resistors Rf and R constitute a non-inverting amplifier with
𝑉𝑜 = 1 +𝑅𝑓
𝑅 𝑉𝑎
Therefore, the output voltage is,
𝑉𝑜 = 1 +𝑅𝑓
𝑅1 𝑉1𝑅1 +
𝑉2𝑅2 +
𝑉3𝑅3
1𝑅1 +
1𝑅2 +
1𝑅3
Which is a non-inverted weighted sum of inputs.
Let 𝑅1 = 𝑅2 = 𝑅3 = 𝑅 =𝑅𝑓
2 then 𝑉𝑜 = 𝑉1 + 𝑉2 + 𝑉3.
SNJB COE, CHANDWAD
Practical Circuit:
Figure3 (a): Circuit Diagram
Input and Output Waveforms:
Figure3 (b): Input and Output waveforms in summer mode
R1 1kΩ
R3 1kΩ
Rf
4kΩ
R2 1kΩ
VCC
15V
VEE
-15V
U1
741
3
2
4
7
6
51
V11 Vrms
50 Hz
0° V2
1 Vrms
50 Hz
0° V31 Vrms
50 Hz
0°
Ro1kΩ
XSC1
A B C D
G
T
R
1kΩ
SNJB COE, CHANDWAD
PROCEDURE:
1) Design a circuit and connect it as shown in fig3 (a).
2) Apply sine wave inputs and observe the output on CRO.
3) Note observation by varying the amplitude of inputs and take the readings and find Av.
4) Draw the input- output waveforms.
OBSERVATIONS TABLE:
Sr. No. Input Voltage(Vin)
V1 V2
Output
Voltage
Vo
Gain
Av1 Av2
1
2
3
4
5
CALCULATIONS:
1) V1= Vo= Av1=
V2= Vo= Av2=
V3= Vo= Av3=
IV. SUBTRACTOR
A basic differential amplifier can be used as a subtractor as shown in fig.4 (a). The subtractor
circuit is used to obtain the subtraction of two input voltages. If all resistors are equal in value,
then the output voltage can be derived by using superposition principle.
Analysis: To find the output Vo1 due to V1 alone, make V2=0. Then the circuit of fig4 (a)
becomes a non-inverting amplifier having input voltage V1/2 at the non-inverting input terminal
and the output becomes
𝑉𝑜1 =𝑉1
2 1 +
𝑅
𝑅 = 𝑉1
Similarly, the output voltage Vo2 due to V2 alone (with V1 grounded) can be written simply for
an inverting amplifier as
𝑉𝑜2 = −𝑉2
Thus the output voltage Vo due to both the inputs can be written as
𝑉𝑜 = 𝑉𝑜1 + 𝑉𝑜2
SNJB COE, CHANDWAD
= (𝑉1−𝑉2)
Practical Circuit:
Figure4 (a): Circuit diagram
Input and Output Waveforms:
Figure4 (b): Input and output Waveforms in Subtractor mode
PROCEDURE:
1) Design a circuit and connect it as shown in fig4 (a).
2) Apply sine wave inputs and observe the output on CRO.
3) Note observations by varying the amplitude of input and take the readings and find Av.
4) Draw the input- output waveforms.
R2 10kΩ
Rf
10kΩ
R3
10kΩ
R1
10kΩ
VCC
15V
VEE
-15V
U1
741
3
2
4
7
6
51
V1
4 Vrms
50 Hz
0°
Ro1kΩ
XSC1
A B C D
G
T
V2
6 Vrms
50 Hz
0°
SNJB COE, CHANDWAD
OBSERVATIONS TABLE:
Sr. No. Input Voltage Vin
V1 V2
Output Voltage
Vo
Gain
Av
1
2
3
4
5
CALCULATIONS:
1) V1= Vo= Av1=
V2= Vo= A v2=
CONCLUSION:
SNJB COE, CHANDWAD
EXPERIMENT NO.:
TITLE:
BRANCH:
BATCH:
ROLL NO.:
DATE:
SNJB COE, CHANDWAD
O P - A M P A S I N T E G R A T O R , D I F F E R E N T I A T O R A N D C O M P A R A T O R
Aim: Study of OP-AMP as Integrator, Differentiator, Comparator.
Apparatus: OP-AMP IC-741, Breadboard, Dual Power supply, Function Generator, CRO,
Resistors, capacitors and jumper wires.
Theory:
I. INTEGRATOR
A Circuit in which the output voltage is the time integral of the input voltage waveform is called
as Integrator or Integrating Amplifier. Integrator produces a summing action over required time
interval and circuit is based on the general parallel inverting feedback model. Such a circuit is
obtained by using a basic inverting amplifier configuration if the feedback resistor Rf is replaced
by a capacitor Cf .
The expression for output voltage V0 can be obtained by writing Kirchoff‟s current law at node
V2,
𝐼𝑖 = 𝐼𝐵 + 𝐼𝐹
𝐼𝑖 = 𝐼𝐹 ……………… Since IB is negligibly small
The nodal equation at node N is,
𝑉𝑖𝑅1
+ 𝐶𝑓𝑑𝑉𝑜𝑑𝑡
= 0
Or, 𝑑𝑉𝑜𝑑𝑡
= −1
𝑅𝑓𝐶𝑓𝑉𝑖
Integrating both sides, we get,
SNJB COE, CHANDWAD
𝑑𝑉𝑜
𝑡
0
= −1
𝑅1𝐶𝑓 𝑉𝑖
𝑡
0
𝑑𝑡
𝑉𝑜 𝑡 = −1
𝑅1𝐶𝑓 𝑉𝑖 𝑡 𝑑𝑡 + 𝑉𝑜
𝑡
0
(0)
Where Vo (0) is the initial output voltage.
The circuit thus provides an output voltage which is proportional to the time integral of the input
and R1Cf is the time constant of the integrator. It may be noted that there is a negative sign in
the output voltage, and therefore, this integrator is also known as an inverting integrator.
Limitation of an ideal integrator circuit:
Even in the absence of input signal , the two components namely, the offset voltage and the bias
current contribute foe an error voltage at the output. Thus, it is not possible to get the true
integration of the input signal at the output. The output waveform is distorted due to this error
voltage. Further, the bandwidth of an ideal integrator is very small. Hence ideal integrator can be
used for very small ranges of input frequency only. In an ideal integrator circuit, a small dc offset
at the input can force the output into saturation. To avoid this, a resistor is placed in parallel with
the integrator capacitor to limit the low frequency gain. However, this has undesirable side effect
of limiting the useful integration range at higher frequencies.
Due to the above limitations, an ideal integrator is not used in practice. A few additional
components are used along with the ideal integrator circuit to minimize the effect of the error
voltage. Such an integrator is called Practical Integrator.
Practical Integrator Circuit:
The practical integrator circuit i.e. loss integrator shown in figure 1 (a). Here feedback capacitor
is shunted by a resistor Rf so that the gain of the integrator at low frequency is limited to avoid
any saturation problem. Since the parallel combination of resistor Rf and capacitor Cf dissipates
power, so this circuit is called as lossy integrator .the resistor Rf provides DC stabilization, by
limiting the low frequency gain to - Rf/ R1 .The resistor Rcomp is used to reduce the effect of
bias current.
Rcomp is given by
𝑅𝑐𝑜𝑚𝑝 = 𝑅1‖𝑅𝐹
And when RF>>R1
𝑅𝐹 = 𝑅1 CIRCUIT DIAGRAM:
INPUT AND OUTPUT WAVEFORM:
OPERATION:
DESIGN:
Design integrator for frequency of 1 KHz with C= 0.01 μF & gain 10.
fmax = fa = 1 KHz
Rcomp = R1||RF
Fb=10fa=10kHz
SNJB COE, CHANDWAD
𝑅𝐹 =1
2𝜋𝐶𝑓𝑓𝑎
=1
2𝜋 ∗ 0.01𝜇 ∗ 1𝐾
Rf= 15.915 KΩ
𝑅1 =1
𝑅𝐹
R1= 1.59 KΩ
Rcomp = R1||RF = 1.59K||15.9K =1.45K
PROCEDURE:
1) Design a circuit and connect it as shown earlier with above values designed.
2) Apply sine wave input and observe the output on CRO.
3) Note observation by varying the frequency and plot the graph and find fa and fb practically.
4) Draw the output waveforms for sine and square wave input.
5) For design purpose
i. Assume CF < 1 for calculation
ii. Assume fb = 10 fa for calculation
OBSERVATION TABLE: Vin=------------Vp-p
Sr. No. Input
Frequency
Output
Voltage
Gain(db)
1
2
3
4
5
6
7
8
9
SNJB COE, CHANDWAD
10
RESULT:
Parameters Theoretical Value Practical value
fa
fb
CONCLUSION:
SNJB COE, CHANDWAD
STUDY OF DIFFERENTIATOR
Aim: To Design and test Op-amp as a Differentiator for given Frequency.
Apparatus: Bread board, dual power supply, CRO, IC 741, Resistors, Capacitor and
Jumper wires.
Theory: The circuit performs the mathematical operation of differentiation; that is, the
output waveform is the derivative of the input waveform. The differentiator may be
constructed from the basic inverting amplifier if an input resistor R1 is replaced by a
capacitor C1.
The expression for the output voltage can be obtained from Kirchhoff‟s current equation
written at node v2 as follows:
𝑖𝐶 = 𝐼 + 𝑖𝐹
Since IB=0
iC =iF
𝐶1𝑑
𝑑𝑡(𝑣𝑖𝑛−𝑣2)=
𝑣2−𝑣𝑜𝑅𝐹
But v1=v2=0V, because A is very large. Therefore
𝐶1
𝑑𝑣𝑖𝑛
𝑑𝑡=
𝑣𝑜
𝑅𝐹
Or
𝑣𝑜 = 𝑅𝐹𝐶1
𝑑𝑣𝑖𝑛
𝑑𝑡
Fig: 1 Ideal Differentiator
SNJB COE, CHANDWAD
Thus the output vo is equal to RFC1 times the negative instantaneous rate of change of the
input voltage vin with time. Since the differentiator performs the reverse of the integrator
function, a cosine wave input will produce a sine wave output, or a triangular input will
produce a square wave output. However, the differentiator shown in fig 1 will not do this
because it has some practical problems. The gain of the circuit (RF/XC1) increases with
increase in frequency at the rate of 20dB/decade. This makes the circuit unstable. Also,
the input impedance XC1 decreases with increase in frequency, which makes the circuit
very susceptible to high frequency noise. When amplified, this noise can completely
override the differentiated output signal. The frequency response of the basic
differentiator is as shown in fig 2. In this figure, fa is the frequency at which the gain is
0dB and is given by
fa= 𝟏
𝟐𝝅𝑹𝑭𝑪
Also, fC is the unity gain bandwidth of the op-amp, and f is some relative operating
frequency.
Both the stability and high frequency noise problems can be solved by the addition of two
components: R1 and CF. The circuit given in fig 3 is the practical differentiator, the
frequency response of which is shown in fig 2 by dotted line.
Fig: 2 Frequency response of differentiator
SNJB COE, CHANDWAD
From frequency f to fb, the gain increases at 20db/deacade. However at fb the gain
decreases at 20db/decade. This 40db/decade change in gain is caused by the R1C1 and
RFCF combinations. The limiting frequency fb is given by
fb = 𝟏
𝟐𝝅𝑹𝟏𝑪𝟏
Fig: 3 Practical differentiator circuit
SNJB COE, CHANDWAD
Fig: 4 Input output waveforms.
Design
Design a differentiator with frequency 1 KHz.
fa=1KHz = 1
2𝜋𝑅𝐹𝐶1
Let C1=0.1µF; then
RF=1
2𝜋10310−7 = 1.59KΩ
fb = 20 kHz
fb= 1
2𝜋𝑅1𝐶1
R1=79.5Ω
Since R1C1=RFCF
CF=0.0055µF
Therefore RF=1.5kΩ
Procedure:
1. Design a circuit and connect it as shown earlierwith above values designed.
2. Apply sine wave input and observe the output on CRO.
3. Note observation by varying the frequency and plot the graph and find fa and fb
practically.
4. Draw the output waveforms for sine and square wave input.
5. For design purpose assume fb = 20fa for calculation
Observation Table: Vin = -------- VPP
Sr. No. I/p frequency Output
voltage Gain in dB
SNJB COE, CHANDWAD
Results:
Parameter Theoretical Practical
fa
fb
Conclusion:
SNJB COE, CHANDWAD
STUDY OF COMPARATOR
Aim: To test Op-amp as a Comparator.
Apparatus: Bread board, dual power supply, single power supply, CRO, IC 741,
Resistors and Jumper wires.
Theory: A comparator is a circuit which compares a signal voltage applied at one input
of an op-amp with a known reference voltage at the other input. It is basically an open
loop op-amp with output ± Vsat as shown in the ideal transfer characteristics of fig 1(a).
However a commercial op-amp has transfer characteristics of fig 1(b). It is seen that the
change in the output state takes place with an increment in input Vi of only 2mV. This is
the uncertainty region where output cannot be directly defined. There are basically 2
types of comparators.
i. Non inverting comparator.
ii. Inverting comparator.
Fig 1 Transfer Characteristics (a) Ideal comparator (b) Practical comparator
The circuit of fig 2 is called a non inverting comparator. A fixed reference voltage Vref is
applied to the inverting input and a time varying signal vi is applied to the non inverting
comparator. The output voltage is at -Vsat for vi < Vref. And Vo goes to +Vsat for vi > Vref.
The output waveform for a sinusoidal input signal applied to the (+) input is as shown in
fig 3 (a).
SNJB COE, CHANDWAD
Fig 2: Inverting comparator
Fig 3: Input and output waveforms for (a) Vref positive (b) Vref negative
Output voltage levels independent of power supply voltages can also be obtained by
using a resistor R and two back to back zener diodes at the output of op-amp as shown in
fig 4.
Applications of comparator:
1. Zero crossing detector
2. Window detector
3. Phase meter.
SNJB COE, CHANDWAD
Fig 4 Comparator with zener diodes
Results:
Conclusion:
SNJB COE, CHANDWAD
EXPERIMENT NO.:
TITLE:
BRANCH:
BATCH:
ROLL NO.:
DATE:
SNJB COE, CHANDWAD
8 0 5 1 A S S E M B L Y L A N G U A G E P R O G R A M M I N G O N T W O 8 - B I T N U M B E R S
AIM: Write Assembly language programming for 8051 Microcontroller (8-bit addition, 8-bit
multiplication, 16-bit addition, smallest number, largest number, ascending order, descending
order )
APPARATUS: Kiel µVision2 Assembler.
THEORY:
Bit 0
Nibble 0000
Byte 0000 0000
Word 0000 0000 0000 0000
Choosing a Microcontroller:Each microcontroller has a unique instruction set and register set;
therefore they are not compatible with each other. Program written for one will not run on others.
There are also 16-bit and 32-bit microcontrollers made by various chip makers with all these
different microcontrollers three criteria in choosing them are as follows:
1) Meeting the computing needs: µc must meet the task at hand efficiency and cost
effectively. We must first see whether an 8-bit, 16-bit, or 32-bit µc can best handle the
computing needs of the task most effectively. Among other considerations in this
category are:
a. Speed: what is the highest speed that the microcontroller supports?
b. Packaging: Does it come in a 40-pin DIP (Dual-In-line) or a QFP(Quad-Flat-
Package), some other package format? This is important in terms of Space,
Assembly, and prototyping the end product.
c. Power consumption
d. The amount of RAM and ROM on chip.
e. The no. of I/O pins and the timer on the chip.
2) Availability of software development tools: How easy it is to develop products around
it, i.e. availability of an assembler, debugger, a code-efficient C language compiler,
emulator, technical support and both in-house and outside expertise.
3) Wide availability of reliable sources of µc: Is its ready availability in needed quantities
both now and in future.
8051 Assembly Language Programming:
A program that consists of 0s and 1s is called as machine language.
SNJB COE, CHANDWAD
Assembly languages were developed that provided mnemonics for the machine code
instructions, plus other features that made programming faster and less prone to error.
The term mnemonics is frequently used in computer science and engineering
literature to refer to codes and abbreviations that are relatively easy to remember.
Assembly language programs must be translated into machine code by the program
called an assembler.
Assembly language is referred to as low-level language because it deals directly with
the internal structure of the CPU. To program in assembly language, the programmer
must know all the registers of the CPU and the size of each, as well as other details.
The assembler is used to convert the assembly language program into the machine
code (sometimes also referred to as object code or opcode for operation code), High-
level languages are translated into machine code by a program called compiler.
An assembly language instruction consists of four fields:
[Label:] mnemonic [operands] [; comment]
The label field allows the program to refer to a line of code by name. The assembly language
mnemonic (instructions) and operand(s) field together perform the real work of the program and
accomplish the task for which the program was written.
Assembling and running an 8051 Program: How Assembly language Program is Created,
Assembled and made ready to Run:-
ASSEMBLER
PROGRAM
OH
PROGRAM
LINKER
PROGRAM
EDITOR
PROGRAM
Filename.asm
Filename.lst
Other obj
files
Filename.obj
Filename.abs
Filename.hex
SNJB COE, CHANDWAD
Program: List file
1. First we use an editor to type in a program similar to above program. A widely used
editor is the MS-DOS EDIT program (or notepad in windows).The editor must be able to
produce an ASCII file. The source file has the extension “.asm” or “.src”, depending on
which assembler you are using.
2. The “asm” source file containing the program code created in step1 is fed to an 8051
assembler. The assembler converts the instructions into machine code. The assembler
will produce an object file and a list file. The extension for object file is “obj” while the
extension for the list file is “lst”.
3. Assemblers require a third step called linking. The link program takes one or more object
files and produces an absolute object file with the extension “abs”. This abs file is used
by 8051 trainers that have a monitor program.
4. Next the abs file is fed into a program called “OH” (object to hex convertor), which
creates a file with extension “hex” that is ready to burn into ROM. This program comes
with all 8051 assembler. Recent windows-based assemblers combine steps2 through 4
into one step.
I) Program Statement: WRITE A PROGRAM TO ADD TWO 8- BIT NO.S(1CH & 07H)
ORG 0000H ; Start (origin) at 0
MOV A, #1CH ; load one immediate no.1Ch into acc; A=1CH
MOV R0, #07H ; load second immediate no. in R0;R0=07H
ADD A, R0 ; add the contents of A and R0; A= A+R0
END ; and the source file
1 0000 ORG 0000H ; Start (origin) at 0 2 0000 7D25 MOV R5,#25H ;load 25H into R5
3 0002 7F34 MOV R7,#34H ;load 34H into R7
4 0004 7400 MOV A,#0 ;load 0 into A
5 0006 2D ADD A,R5 ;add contents of R5 to A; now A=A+R5 6 0007 2F ADD A,R7 ; add contents of R7 to A; now A=A+R7
7 0008 2412 ADD A,#12 ;add to A value 12H; now A=A+12H
8 000A 80FE HERE: SJMP HERE ; Stay in this loop 9 000C END ; end of asm source file
SNJB COE, CHANDWAD
Before Execution: After Execution:
Fig.1: output of addition of two 8- bit no.s
II) Program Statement: WRITE A PROGRAM TO MULTIPLY TWO 8-BIT NO.S
(1Dh&Ch)
ORG 0000H ; Start (origin) at 0 memory location
MOV A, #1DH ; load one immediate no. 1DH into acc; A=1D
MOV B, #0CH ; load another immediate value into B register; B=C
MUL AB ; multiply the contents of A with B; store the lower byte of result into A and
; Higher byte into B
END ; end the asm source file
SNJB COE, CHANDWAD
Before Execution: After Execution:
Fig.2: Output for multiplication of two 8-bit no.s
III) Program Statement: WRITE A PROGRAM TO ADD TWO 16-BIT NUMBERS
(02FD & E37A)
ORG 0000H ; start (origin) at 0
CLR C ; clear the carry flag; CY=00
MOV A, #0FDH ; move the lower byte of first immediate no. into A; A=FD
ADD A, #7AH ; add A with lower byte of second immediate no. 7AH;
A=A+7Ah
MOV R0, A ; move the lower byte of result into R0; R0=A
MOV A, #02H ; load acc with higher byte of first no.02H; A=02h
ADDC A, #0E3H ; add with carry the contents of A with higher byte of second
; Immediate no. E3h; A=A+E3h
END ; end source code file
SNJB COE, CHANDWAD
After Execution:
Fig. 3: Output for addition of two 16- bit no.s
IV) Program Statement: WRITE A PROGRAM TO FIND THE SMALLEST NO.
FROM TWO 8-BIT NO.S (09H & 9FH) PLACE RESULT IN B REGISTER
ORG 0000H ; Start (origin) at 0
MOV A, #09H ; load acc with value 09H; A=09
MOV B, #9FH ; load B with value 9FH; B=9F
CJNE A, B, NEXT ; compare the contents of A with contents of B
; If A>B; CY=0, if A<B; CY=1
SJMP LOOP ; If A=B, jump to address named loop
NEXT: JNC LOOP ; if A>B, jump to address named loop
AJMP LOOP
MOV B, A ;
LOOP: END ;
SNJB COE, CHANDWAD
Before Execution: After Execution:
Fig. 4: Output of smallest no.
V) Program Statement: WRITE A PROGRAM TO FIND THE LARGEST NO.
FROM TWO 8-BIT NO.S (C9H & 99H) PLACE RESULT IN B REGISTER
ORG 0000H ;
MOV A, #0C9H ; load A with value C9H
MOV B, #99H ; load B with 99H
CJNE A, B, NEXT ; compare contents of A with that of B
;If A>B; CY=0, if A<B; CY=1
SJMP LOOP ; If A=B, jump to address named loop
NEXT: JC LOOP ; Jump to address named LOOP, if A<B
MOV B, A ;
LOOP: END ;
SNJB COE, CHANDWAD
Before Execution: After Execution:
Fig. 5: output of largest no.
VI) Program Statement: WRITE A PROGRAM TO SORT THE TWO 8-BIT NO.S IN
ASCENDING ORDER (FDH & FAH)
ORG 0000H ; start at o location
MOV A, #0FDH ; load A with value FD
MOV B, #0FAH ; load B with value FA
CJNE A, B, NEXT ; compare contents of A with contents of B A<B, CY=1 A>B, CY=0
AJMP EXIT ; if A=B, jump to EXIT
NEXT: JC EXIT ; jump to EXIT if A<B
XCH A, B ; if A>B, place them in ascend order
EXIT: END ;
SNJB COE, CHANDWAD
Before Execution: After Execution:
Fig.6: output of no. in ascending order
VII) Program Statement: WRITE A PROGRAM TO SORT THE TWO 8-BIT NO.S IN
DESCENDING ORDER (7FH & FAH)
ORG 0000H ; start at 0
MOV A, #7FH ; load A with value 7F
MOV B, #0FAH ; load B with value FA
CJNE A, B, NEXT ; compare contents of A with contents of B A<B, CY=1 A>B, CY=0
AJMP EXIT ; if A=B, jump to EXIT
NEXT: JNC EXIT ; jump to EXIT if A>B
XCH A, B ; if A<B, place them in descend order
EXIT: END ; end asm source file
SNJB COE, CHANDWAD
Fig.7: output of no. in descending order
CONCLUSIONS:
SNJB COE, CHANDWAD
EXPERIMENT NO.:
TITLE:
BRANCH:
BATCH:
ROLL NO.:
DATE:
SNJB COE, CHANDWAD
8051 ASSEMBLY LANGUAGE PROGRAMMING ON TWO 8-BIT NUMBERS
AIM: Write Assembly language programming for 8051 Microcontroller for series of 10 numbers
(8-bit addition, 8-bit multiplication, smallest number, largest number, ascending order,
descending order )
APPARATUS: Kiel µVision2 Assembler.
I) Program Statement: WRITE A PROGRAM TO ADD SERIES OF 10 (8-BIT)
NUMBERS
ORG 0000H
MOV 40H,#01H
MOV 41H,#0CH
MOV 42H,#82H
MOV 43H,#02H
MOV 44H,#0D1H
MOV 45H,#06H
MOV 46H,#07H
MOV 47H,#0F1H
MOV 48H,#09H
MOV 49H,#0A3H
MOV R0,#40H
MOV R1,#10
CLR A
MOV R7,A
AGAIN: ADD A,@R0
JNC NEXT
INC R7
NEXT: INC R0
DJNZ R1,AGAIN
END
SNJB COE, CHANDWAD
Fig : addition of series of 10 no.
II) Program Statement: WRITE A PROGRAM TO MULTIPLY SERIES OF 10 (8-
BIT) NUMBERS
ORG 0000H
MOV 60H,#01H
MOV 61H,#02H
MOV 62H,#03H
MOV 63H,#02H
MOV 64H,#02H
MOV 65H,#02H
SNJB COE, CHANDWAD
MOV 66H,#02H
MOV 67H,#02H
MOV 68H,#01H
MOV 69H,#01H
MOV R0,#60H
MOV R1,#10
CLR A
MOV B,#01H
AGAIN:
MOV A,@R0
MUL AB
MOV B,A
INC R0
DJNZ R1,AGAIN
END
SNJB COE, CHANDWAD
Fig: multiplication of series of 10 no.s
III) Program Statement: WRITE A PROGRAM TO FIND SNALLEST NO. FROM
SERIES OF 10 (8-BIT) NUMBERS
ORG 0000H
MOV 50H,#1CH
MOV 51H,#0DAH
MOV 52H,#0ECH
MOV 53H,#7CH
MOV 54H,#0CH
MOV 55H,#45H
MOV 56H,#60H
MOV 57H,#25H
MOV 58H,#0DH
MOV 59H,#0F7H
MOV R0,#50H
MOV R1,#10
MOV B,#0F7H
BACK:
MOV A,@R0
CJNE A,B,LOOP
LOOP:
SNJB COE, CHANDWAD
JNC LOOP1
MOV B,A
INC R0
DJNZ R1,BACK
SJMP NEXT
LOOP1:
INC R0
DJNZ R1,BACK
NEXT:
MOV A,B
MOV 60H,A
END
SNJB COE, CHANDWAD
Fig: smallest no.from 10 no.s
IV) Program Statement: WRITE A PROGRAM TO FIND LARGEST NO. FROM
SERIES OF 10 (8-BIT) NUMBERS
ORG 0000H
MOV 50H,#1CH
MOV 51H,#02H
MOV 52H,#0ECH
MOV 53H,#7CH
MOV 54H,#0CH
MOV 55H,#45H
MOV 56H,#60H
SNJB COE, CHANDWAD
MOV 57H,#25H
MOV 58H,#0DH
MOV 59H,#0F7H
MOV R0,#50H
MOV R1,#10
MOV B,#00H
BACK:
MOV A,@R0
CJNE A,B,LOOP
LOOP:
JC LOOP1
MOV B,A
INC R0
DJNZ R1,BACK
SJMP NEXT
LOOP1:
INC R0
DJNZ R1,BACK
NEXT:
MOV A,B
MOV 60H,A
END
SNJB COE, CHANDWAD
Fig:largest no. from 10 no.s
V) Program Statement: WRITE A PROGRAM TO SORT THE SERIES OF 10 (8-
BIT) NUMBERS IN ASCENDING ORDER
ORG 0000H
MOV DPTR,#3000H
MOV A,#01H
MOVX @DPTR,A
INC DPTR
MOV A,#03H
MOVX @DPTR,A
INC DPTR
MOV A,#09H
MOVX @DPTR,A
INC DPTR
MOV A,#05H
MOVX @DPTR,A
INC DPTR
MOV A,#08H
MOVX @DPTR,A
INC DPTR
MOV A,#06H
MOVX @DPTR,A
SNJB COE, CHANDWAD
INC DPTR
MOV A,#02H
MOVX @DPTR,A
INC DPTR
MOV A,#07H
MOVX @DPTR,A
INC DPTR
MOV A,#04H
MOVX @DPTR,A
INC DPTR
MOV A,#0AH
MOVX @DPTR,A
MOV R0,#09H
START:
MOV DPTR,#3000H
MOV R1,#09H
BACK:
MOV R2,DPL
MOVX A,@DPTR
MOV R3,A
INC DPTR
MOVX A,@DPTR
MOV B,A
MOV A,R3
CJNE A,B,OVER
AJMP GO
OVER:
JC GO
MOV DPL,R2
MOV A,B
MOVX @DPTR,A
INC DPTR
MOV A,R3
MOVX @DPTR,A
GO:
DJNZ R1,BACK
DJNZ R0,START
END
SNJB COE, CHANDWAD
Fig. ascending order no.s
SNJB COE, CHANDWAD
VI) Program Statement: WRITE A PROGRAM TO SORT THE SERIES OF 10 (8-
BIT) NUMBERS IN DESCENDING ORDER
ORG 0000H
MOV DPTR,#3000H
MOV A,#01H
MOVX @DPTR,A
INC DPTR
MOV A,#03H
MOVX @DPTR,A
INC DPTR
MOV A,#09H
MOVX @DPTR,A
INC DPTR
MOV A,#05H
MOVX @DPTR,A
INC DPTR
MOV A,#08H
MOVX @DPTR,A
INC DPTR
MOV A,#06H
MOVX @DPTR,A
INC DPTR
MOV A,#02H
MOVX @DPTR,A
INC DPTR
MOV A,#07H
MOVX @DPTR,A
INC DPTR
MOV A,#04H
MOVX @DPTR,A
INC DPTR
MOV A,#0AH
MOVX @DPTR,A
MOV R0,#09H
START:
MOV DPTR,#3000H
MOV R1,#09H
BACK:
MOV R2,DPL
MOVX A,@DPTR
MOV R3,A
INC DPTR
MOVX A,@DPTR
SNJB COE, CHANDWAD
MOV B,A
MOV A,R3
CJNE A,B,OVER
AJMP GO
OVER:
JNC GO
MOV DPL,R2
MOV A,B
MOVX @DPTR,A
INC DPTR
MOV A,R3
MOVX @DPTR,A
GO:
DJNZ R1,BACK
DJNZ R0,START
END
SNJB COE, CHANDWAD
Fig. Descending order no.s
CONCLUSIONS:
SNJB COE, CHANDWAD
SNJB COE, CHANDWAD
EXPERIMENT NO.:
TITLE:
BRANCH:
BATCH:
ROLL NO.:
DATE:
SNJB COE, CHANDWAD
INTERFACING OF DAC WITH 8051 USING ASSEMBLY LANGUAGE
PROGRAMMING
AIM: Write a program to interface DAC with 8051.
APPARATUS: Keil µVision2 assembler.
THEORY: Digital-to-analog (DAC) converter
The digital-to-analog converter (DAC) is a device widely used to convert digital pulses to analog
signals. In this section we discuss the basics of interfacing a DAC to the 8051.
The two methods of creating a DAC: binary weighted and R/2R ladder. The vast majority of
integrated circuit DACs, including the MC1408 (DAC0808) used in this section use the R/2R
method since it can achieve a much higher degree of precision. The first criterion for judging a
DAC is its resolution, which is a function of the number of binary inputs. The common ones are
8, 10, and 12 bits. The number of data bit inputs decides the resolution of the DAC since the
number of analog output levels is equal to 2″, where n is the number of data bit inputs.
Therefore, an 8-input DAC such as the DAC0808 provides 256 discrete voltage (or current)
levels of output. Similarly, the 12-bit DAC provides 4096 discrete voltage levels. There are also
16-bit DACs, but they are more expensive.
MC1408 DAC (or DAC0808) In the MC1408 (DAC0808), the digital inputs are converted to current (Iout), and by connecting a
resistor to the Iout pin, we convert the result to voltage.
The total current provided by the Iout pin is a function of the binary numbers at the DO – D7
inputs of the DAC0808 and the reference current (Iref), and is as follows:
𝐼𝑜𝑢𝑡 = 𝐼𝑟𝑒𝑓 𝐷7
2+𝐷6
4+
𝐷5
8+
𝐷4
16+
𝐷3
32+
𝐷2
64+
𝐷1
128+
𝐷0
256
where D0 is the LSB, D7 is the MSB for the inputs, and Iref is the input current that must be
applied to pin 14. The Iref current is generally set to 2.0 mA. Figure 5-1shows the generation of
current reference (setting Iref = 2 mA) by using the
standard 5-V power supply and 1K and 1.5K-ohm standard resistors. Some DACs also use the
zener diode (LM336), which overcomes any fluctuation associated.
SNJB COE, CHANDWAD
Generating a sine wave:
To generate a sine wave, we first need a table whose values represent the magnitude of the sine
of angles between 0 and 360 degrees. The values for the sine function vary from -1.0 to +1.0 for
0- to 360-degree angles. Therefore, the table values are integer numbers representing the voltage
magnitude for the sine of theta. This method ensures that only integer numbers are output to the
DAC by the 8051 microcontroller. Table 5.1 shows the angles, the sine values, the voltage
magnitudes, and the integer values representing the voltage magnitude for each angle (with 30-
degree increments). To generate Table 13-7, we assumed the full-scale voltage of 10 V for DAC
output (as designed in Figure 13-18). Full-scale output of the DAC is achieved when all the data
inputs of the DAC are high. Therefore, to achieve the full-scale 10 V output, we use the
following equation.
Vout of DAC for various angles is calculated and shown in Table 13-7. See Example 13-5 for
verification of the calculations.
SNJB COE, CHANDWAD
Table 5.1: Angle vs. Voltage Magnitude for Sine Wave
Angle 9 (degrees)
Sin 0
Vout (Voltage Magnitude) Values Sent to DAC (decimal) 5 V + (5 V X sin
6) (Voltage Mag. X 25.6)
0 0 5 128
30 0.5 7.5 192
60 0.866 9.33 238
90 1.0 10 255
120 0.866 9.33 238
150 0.5 7.5 192
180 0 5 128
210 -0.5 2.5 64
240 -0.866 0.669 17
270 -1.0 0 0
300 -0.866 0.669 17
330 -0.5 2.5 64
360 0 5 128
Figure 13-19. Angle vs. Voltage Magnitude for Sine Wave
SNJB COE, CHANDWAD
PROCEDURE:
Algorithm for interface 8051 with DAC:
Step1: Connect the P1 of 8051 with D0-D7 pins of DAC
Step2: Give +5v to VCC & Vref of DAC
Step3: Connect -12v to VEE of DAC
Step4: Connect OPAMP to OUT pin of the DAC With 5K resistor
Step5: Connect the oscilloscope to the OPAMP to View the output
Program:
ORG 0000H
PORTA EQU 0000H
PORTB EQU 0002H
PORTC EQU 0004H
CWR EQU 0006H
MOV A,#08H
MOV DPTR,#PORTA
MOV A,#00H
L1:
MOVX @DPTR,A
INC A
CJNE A,#0FFH,GO
JNZ L1
L2:
DEC A
MOVX @DPTR,A
JNZ L2
JNZ L1
GO: END
CONCLUSION:
SNJB COE, CHANDWAD
EXPERIMENT NO.:
TITLE:
BRANCH:
BATCH:
ROLL NO.:
DATE:
SNJB COE, CHANDWAD
EXPERIMENT NO.:
TITLE:
BRANCH:
BATCH:
ROLL NO.:
DATE:
SNJB COE, CHANDWAD
TO DETERMINE THE EFFICIENCY AND REGULATION OF A SINGLE PHASE
TRANSFORMER BY CONDUCTING (A) OPEN CIRCUIT TEST AND (B) SHORT
CIRCUIT TEST.
AIM:
To understand the basic working principle of a transformer.
To obtain the equivalent circuit parameters from OC and SC tests, and to estimate
efficiency & regulation at various loads.
THEORY: Open circuit (OC) test The shunt branch parameters can be determined by performing this test. Since, the core loss and
the magnetizing current depend on applied voltage, this test is performed by applying the rated
voltage to one of the windings keeping the other winding open (generally HV winding is kept
open and rated voltage is applied to LV winding). The circuit diagram to conduct this test is
shown in Fig. Since, the secondary terminals are open (no load is connected across the
secondary), current drawn from the source is called as no load current. Under no-load condition
the power input to the transformer is equal to the sum of losses in the primary winding resistance
R1, and core loss. Since, no load current is very small, the loss in winding resistance is neglected.
Hence, on no load the power drawn from the source is dissipated as heat in the core. If Io and Pi
are the current and input power drawn by the transformer at rated voltage V1 respectively, then
𝐶𝑂𝑆𝜁0 =𝑃𝑖
𝑉1 . 𝐼0
From fig 1(b),
Ic=I0 cos 𝜁0 , Im=I0 sin 𝜁0 ,
Therefore,
R0 = V1/Ic, Xm = V1/Im
Fig.1-a:Circuit diagram for no-load test
SNJB COE, CHANDWAD
Fig1-b.: Phasor diagram for no-load test
Short circuit (SC) test
Consider the circuit shown in Fig.2-a. Suppose the input voltage is reduced to a small fraction of
rated value and secondary terminals are short-circuited. A current will circulate in the secondary
winding. Since a small fraction of rated voltage is applied to the primary winding, the flux in the
core and hence the core loss is very small. Hence, the power input on short circuit is dissipated as
heat in the winding. The circuit diagram to conduct this test is shown in Fig.6 (a). In this test, the
LV terminals of the transformer are short circuited. The primary voltage is gradually applied till
the rated current flows in the winding. Since, the applied voltage is very small (may be of the
order of 5-8%), the magnetizing branch can now be eliminated from the equivalent circuit. If Vsc
is the applied voltage to circulate the rated current (I02) on short circuit, and Pc is the power
input to the transformer then,
𝑍𝑠𝑐 =𝑉𝑠𝑐
𝐼′2
𝐶𝑂𝑆𝜃 =𝑃𝑐
𝑉𝑎𝑐 . 𝐼′2
Therefore,
(R1 + R’2) = Zsc cos θ ; (X1 + X’2 ) = Zsc sin θ
SNJB COE, CHANDWAD
Fig.2-a: Circuit diagram for short-circuit test
Efficiency:
Efficiency of the transformer is defined as:
ᵑ =output power
input power
In terms of losses,
ᵑ =
output power
output power + iron losses + copper losses
Let `S' be the rated VA of the transformer, `x' is the fraction of full load the transformer is
supplying, and 𝜁 is the load power factor angle. Under this condition the output power of the
transformer is = x.S.cos 𝜁. If Pc is the copper loss (loss in winding resistance) at rated current,
the corresponding loss while supplying the fraction of load is = x2.Pc. With transformers of
normal design, the flux in the core varies only a few percent between no-load to full load.
Consequently it is permissible to regard the core loss (iron loss) as constant, regardless of load.
Let this loss be Pi. Therefore equation becomes:
ᵑ =𝑥. 𝑆. cos 𝜁
𝑥. 𝑆. cos 𝜁 + 𝑃𝑖 + x2
. 𝑃𝑐
Regulation:
It can be seen that if the input voltage is held constant, the voltage at the secondary terminals
varies with load. Regulation is defined as the change in magnitude of secondary (terminal)
voltage, when the load is thrown off with primary voltage held constant. Since, the change in
secondary voltage depends only on the load current, the equivalent circuit is further simplified.
The vector diagrams for lagging, unity and leading power factor loads are shown in Fig.3. It can
be proved that angle σ is very small and can be neglected. In that case, the expression for
regulation is given by
%𝑟𝑒𝑔𝑢𝑙𝑎𝑡𝑖𝑜𝑛 =𝐼’2.𝑅𝑒𝑞. cos 𝜁 ± 𝐼’2.𝑋𝑒𝑞. sin 𝜁
𝑉′2× 100
Where,
I’2 =load current, Req = R1 + R’2,
Xeq = X1 + X’2,
`+' sign for lagging pf & `-' for leading pf.
PROCEDURE:
OPEN CIRCUIT TEST:
SNJB COE, CHANDWAD
1) Connect the circuit as shown in circuit Diagram, choosing suitable instrument.
2) Switch on the supply, keeping output voltage at auto-transformer at zero. Increase the
voltage in set up to rated and tabulated the no load current, input power and the primary
and secondary voltages corresponding to each value of the applied voltage.
Circuit Diagram:
SHORT CIRCUIT TEST:
1) Connect the circuit as shown in circuit diagram-2 ,choosing suitable instrument.
2) Keeping the output voltage of the auto-transformer at zero, switch on the circuit. Increase the
output voltage slowly and observe the primary and secondary currents carefully.
3) Adjust the output voltage of the transformer to get secondary short circuit current of 25%,
59%, 75%, 100% of the rated current.
SNJB COE, CHANDWAD
Circuit Diagram:
CALCULATIONS:
CONCLUSIONS:
SNJB COE, CHANDWAD
EXPERIMENT NO.:
TITLE:
BRANCH:
BATCH:
ROLL NO.:
DATE:
SNJB COE, CHANDWAD
Load test on a three phase Induction motor.
Aim: To determine how speed, efficiency, stator current, torque and slip of an induction. Motor
vary with load.
Equipments: Three phase squirrel cage induction motor: Along with DOL starter and Brake
Pulley arrangement.
Output power: 5 H.P. / 3.7 Watts. Rated speed: 1500 Rpm
Rated voltage: 440 Volts No. of poles: 4
Rated current: 7.5 Amp Frequency: 50 Hz
Apparatus:
Apparatus Type Range No.
Voltmeter AC 0 To 600 Volts 1
Ammeter AC 0 To 10 Amps. 1
Wattmeter AC 0 To 600 Volts. 1
Tachometer 1
Theory:
Three phase induction motor is an ac motor with constant speed characteristic like dc shunt
motor. It is widely used in practice due to simplest, most robust, cheapest & highly efficient
construction. In case of slip ring type induction motor by adding external resistance in the rotor
circuit, high starting torque & smooth speed variations are obtained. This is not possible in case
of squirrel cage induction motor (by adding external resistance in the rotor circuit, high starting
torque and smooth speed variations are obtained. This is not possible in case of and rings) .To
check the performance of small motors direct loading method is used. Here induction motor is
directly loaded by pulley brake arrangement, hence the method is called direct loading method,
At no load the slip is small and motor draws very small no load current from supply .As the
mechanical load on the motor s is increased, the speed drops due to its retarding effect, the slip
increases and hence the rotor power output increases. Thus, the motor adjusts itself to the new
load condition of increased output, corresponding to which to which the input (stator) current
also increases and the speed drops a little.
Output of the motor is given by
Pout = (2NT /60) Watt
Where 1
SNJB COE, CHANDWAD
Torque = T = (S1 – S1) x R 9.81 N m
R = Radius of the pulley in m.
N = Actual speed in rpm.
Power in out to the motor is given by,
Pin = (W1 + W2) Watts
Efficiency = Pout / Pin
Procedure:
1: Connect the circuit is as shown in the circuit diagram
2: Switch on the supply, using starter & run the motor at no load condition. Note down the
readings at this condition.
3: Increase the load on motor gradually & note the corresponding readings.
4: Repeat step no no. 3 till the full load is reached. In case any wattmeter starts indicating
negative reading (below zero) stop the motor & interchange one of the wattmeter coil
connections. Restart the motor at no load condition. Adjust the load and consider the power
reading after coil reversal to be negative.
Observation Table:
Radius of the pulley (r) = m.
Multiplying factor (MF) of W1 = Multiplying factor (MF) of W2 =
Sr.
No.
Voltage
V - Volt
Current
I - Amp
W1x MF
Watt
W2x MF
Watt
Spring Balance
Readings (kg.)
Speed
N - rpm
S1 S2
1
2
3
4
5
6
Calculation:
Pin = (W1 + W2) = Watts
SNJB COE, CHANDWAD
Torque = T = (S1 – S1) x R 9.81 = – N m
2NT
Pout = -------------
60
Where,
NS - N
% Slip = ---------------
NS
Pout
% Efficiency = -------------------- x 100
Pin
Result Table:
Sr. No. Input Power
Pin = Watt
Output Power
Pout - Watt
Torque -Nm % Slip % Efficiency
1
2
3
4
5
6
Graphs:
Draw the following characteristics
1: % Efficiency Vs Output Power
2: Torque Vs Output Power
3: Speed Vs Output Power
SNJB COE, CHANDWAD
4: Torque Vs % Slip
Conclusion:
