Section 1 Overview - Shrubberyheas/willem/PDF/ATMEL Flash...Angel Debug Monitor (with or without EmbeddedICE or Multi-ICE) 2.1.1 The ARMulator The ARMulator is a software emulator

AT91EB01 Evaluation Board User Guide 1

Section 1

Overview

1.1 Scope The AT91EB01 Evaluation Board enables real-time code development and evaluation.It supports the AT91M40400 family with its various memory options.

This guide focuses on the AT91 Evaluation Board as an evaluation and demonstrationplatform.

1. Section 1 provides an overview.

2. Section 2 describes the selection of the debugging system.

3. Section 3 details the set-up of the development board.

4. Section 4 contains the memory maps.

5. Section 5 gives the circuit description.

Following are 2 appendices covering configuration links and memory data, and sche-matics including pin connectors.

1.2 Deliverables The evaluation board is supplied with a DB9 plug to DB9 socket straight through serialcable to connect the target evaluation board to a PC. There is also a bare power leadwith a 2.1 mm jack on one end for connection to a bench power supply.

To use the evaluation board the user needs to provide a host computer and a debuggingsystem, both of which are described below.

1.3 SystemRequirements

The host computer must be running the debugger in the ARM® Software DevelopmentToolkit, version 2.1x.

If an earlier version of the Software Development Toolkit is being used, it is strongly rec-ommended to upgrade to the most recent version. Other software toolkits for the ARM,available from third parties, are not discussed in this guide. If a third-party toolkit is beingused, use this guide alongside the documentation supplied with the toolkit.

Overview

2 AT91EB01 Evaluation Board User Guide

1.4 The AT91EB01 Evaluation Board

The board consists of an AT91M40400 together with several peripherals:

■ Two serial ports

■ Reset button

■ Three Applicative Buttons (FIQ, TIOB0, IRQ0)

■ Three LEDs (TIOA0, TIOA1, TIOB0)

■ 512K bytes 16-bit SRAM (upgradable to 2048K bytes)

■ 128K bytes 16-bit Flash (of which 64K bytes is available for user software)

■ 20-pin JTAG interface connector

If required, user defined peripherals can also be added to the board. See “Appendix A -Configuration Links and SRAM Bank 1” on page 27 for details.

Figure 1. AT91EB01 Block Diagram

JTAGICE

Connector

ARM7TDMIProcessor

4K ByteRAM

EBI

SRAM Flash

EBIMonitor Points

AMBABridge

Buttons InterruptController

WatchdogTimer

CounterTimers

SerialPorts

RS232Drivers

ClockGenerator

VoltageRegulator

AT91M40400

ASB

APB

LEDs

Reset

ResetController

I/OExpansion

Points


Section 2

The Debugging System

The number of debugging systems available for the AT91EB01 is rapidly increasing.This section presents the characteristics and advantages of several of these debuggingsystems. If a debugging system has already been chosen, proceed to “Setting up theAT91EB01 Evaluation Board” on page 7.

2.1 Choosing a Debugging Sys-tem

The four debugging systems available for software applications developed to run on anAT91 microcontroller described in this document are:

■ The ARMulator

■ EmbeddedICE

■ Multi-ICE

■ Angel Debug Monitor (with or without EmbeddedICE or Multi-ICE)

2.1.1 The ARMulator The ARMulator is a software emulator of the ARM7TDMI processor. It supports both theARM and Thumb® instruction sets. The ARMulator enables the development of softwarebefore any hardware is available. It does this by providing an environment for the devel-opment of AT91-targeted software on non-ARM-based host systems. A target system isnot necessary to use the ARMulator. The ARMulator is included in the ARM SoftwareDevelopment Toolkit.

2.1.2 EmbeddedICE EmbeddedICE is a JTAG-based, non-intrusive, debugging system for ARM7TDMI pro-cessors. EmbeddedICE provides the interface between a debugger and the ARM7TDMIcore of the AT91M40400 on the evaluation board, using the JTAG port for communica-tion.

EmbeddedICE provides the user with:

■ Real-time address and data-dependent breakpoints (including ROM)

■ Single stepping

■ Full access and control of the ARM core

■ Full memory access (read and write)

■ Full I/O system access (read and write)

EmbeddedICE also enables the embedded microprocessor to access host systemperipherals, such as screen display, keyboard input, and disk drive storage.



EmbeddedICE is an extension to the architecture of the ARM7TDMI RISC processor,and provides the ability to debug cores that have been deeply embedded into systems.It consists of:

■ A set of debug extensions to the ARM7TDMI processor

■ The EmbeddedICE macrocell to provide access to the extensions from the outside

world

■ The ARM EmbeddedICE interface, to provide communication between the

EmbeddedICE macrocell and the debugger resident on the host computer

The EmbeddedICE macrocell is the integrated on-chip logic that provides debug supportfor the ARM7TDMI processor. The EmbeddedICE macrocell is programmed in serialthrough the Test Access Port (TAP) controller on the ARM7TDMI, via the JTAG inter-face. This is usually achieved via the EmbeddedICE interface. The EmbeddedICE mac-rocell consists of two real-time watchpoint units, together with a control and statusregister. One or both watchpoint units can be programmed to halt the execution ofinstructions by the ARM7TDMI.

The ARM EmbeddedICE interface is a JTAG protocol conversion unit. This translatesthe debug protocol messages generated by the debugger into JTAG signals that can besent to the EmbeddedICE macrocell, and vice versa. The interface can be connected tothe host computer using either the built-in serial port, or the built-in serial and parallelports. The serial port is used for bidirectional transfers, but the parallel port is only usedto download code. Using the parallel port increases the maximum download speed withEmbeddedICE to approximately 20K bytes/s. This is considerably greater than using theserial ports alone (even at 38400 baud), and so is the recommended method of usingEmbeddedICE (host permitting).

Although EmbeddedICE is generally non-intrusive, there are two exceptions:

■ When an ARM debugger is started, it attempts to find out the state of the target

microcontroller. To do this, it halts the target and inspects the state of the ARM

registers. This, however, can be considered non-intrusive if the debugging session

begins after the debugger has been started.

■ Watchpoints on structures or arrays that are larger than one word may cause the

target microcontroller to halt execution when writes occur close to the watchpointed

area. EmbeddedICE will restart execution transparently to the user, but this may still

cause problems if the application is real-time.

Note: The Debug Comms Channel is currently not supported on the AT91EB01 board.

2.1.3 Multi-ICE Multi-ICE is the latest ICE-compatible debug solution from Advanced RISC Machines. Itcomprises an interface unit which connects between the parallel port of a PC and theJTAG interface and software to allow an ARM debugger to communicate with the inter-face unit.

The Multi-ICE system is very similar to EmbeddedICE except that the Embedded ICEinterface unit contains a processor and software, whereas the Multi-ICE interface unitcontains no processor and the interface software runs on the host PC. There are a num-ber of advantages to this approach - a smaller, lighter interface unit with a lower powerconsumption (it can be target powered), easier updating of software, more flexible inter-faces.

Features of Multi-ICE:

■ Stored/Automatic configuration



■ Networked connections

■ High-performance code download

■ Low-voltage target operation

■ Small, lightweight unit improves ease of use

■ Additional power supply not normally required (powered from target)

■ Easy-to-use parallel port connection

■ Software configurable JTAG rate

■ Easy software upgrades - 100% host-based software

■ Extra user input/output bits for user-supplied drivers

2.1.4 The Angel Debug Monitor

Note: To aid readability, the term “Angel” is used to mean the Angel Debug Monitor on target throughout this user guide.

Angel is a program that enables development and debugging of applications running onthe AT91 microcontrollers. Angel communicates with a debugger that can handle theAngel communications protocol, such as the ARMSD, the ARM Debugger for Windows.

Angel can debug applications running in both ARM and Thumb state on the AT91 Eval-uation Board. A typical Angel system has two main components that communicate via aphysical link, such as a serial cable:

Debugger: This runs on the host computer. It gives instructions to Angel and dis-plays the results obtained from it. The debugger could be ARMSD, the ARM Debug-ger for Windows.

Angel: This runs alongside the application being debugged on the target platform.

The ARM Software Development Toolkit features two versions of Angel:

■ a full version for use on development hardware

■ a minimal version for use on production hardware.

Only the full version is provided with the AT91EB01.

Angel uses a debugging protocol called the Angel Debug Protocol (ADP), which sup-ports multiple channels. It requires control over the ARM’s exception vectors, but canshare these with your applications.

Angel can be used to:

■ evaluate existing application software on real hardware (as opposed to emulation of

the hardware)

■ develop software applications on the AT91 Evaluation Board

■ bring into operation new hardware that includes an ARM processor

■ port operating systems to the AT91 microcontroller

These activities require some understanding of how Angel’s components work together.Some involve modification of Angel itself, such as porting operating systems. For moredetailed information, see the ARM Software Development Toolkit User Guide (ARM DUI0040) and the ARM Software Development Toolkit Reference Guide (ARM DUI 0041).

The section “Using Angel” on page 19 gives details on the use of Angel on theAT91EB0x.



2.1.5 How EmbeddedICE and Multi-ICE dif-fers from a Debug Monitor

A debug monitor, such as Angel, is an application that runs on the board in conjunctionwith the user application, and requires some resource to be available for it on the board.When the board powers up, Angel installs itself by initializing the vector table so that ittakes control of the board when an exception occurs. Communication coming in fromthe host causes an interrupt, halting the user application and calling the appropriatecode within Angel. Angel then returns to the user application. This can complicate mat-ters if the application also requires access to interrupts. Similarly, if the applicationrequests some form of I/O to the host, this is implemented within the application using asoftware interrupt (SWI) instruction that is dealt with by Angel's SWI handler. Thismeans that Angel requires non-volatile memory to store the debug monitor code, RAMto store its data, and control over the exception vectors to enable it to gain control of theARM7TDMI while the user's application is running.

EmbeddedICE and Multi-ICE, on the other hand, require no such resource. Rather thanexisting as an application on the board, they work by using a combination of the debughardware on the core and the interface that handles communication between the core'sdebug hardware and the host. EmbeddedICE and Multi-ICE have been designed so thatdebugging via the JTAG port is as non-intrusive as possible:

■ The target microcontroller does not require special hardware to support debugging

(the debug extensions and the EmbeddedICE macrocell are all that are necessary).

■ The target microcontroller system does not require memory to be set aside for

debugging nor special software to be incorporated to allow debugging.

Note: Although EmbeddedICE and Multi-ICE require no memory on the target to oper-ate, the target still requires some memory to execute the application code: An ICE does not provide a memory emulation.

EmbeddedICE and Multi-ICE may pollute the exception vectors if semihosting and/or vector catch are enabled.

EmbeddedICE and Multi-ICE interact with the target processor by halting execution andthen forcing the processor into debug state to access data required by the debugger viathe JTAG interface. This results in the processor being halted for significant periods oftime, which may cause problems when you are debugging real-time systems.

Angel is invoked by an SWI instruction and does not halt the processor. Instead, controlis passed from the application code to the debug monitor. This may reduce the amountof dead time when data is accessed on behalf of the debugger. Furthermore, interruptscan be disabled for the minimum time needed by the debugger, allowing real-time appli-cation interrupts to be serviced.


Section 3

Setting up the AT91EB01 EvaluationBoard

3.1 Electrostatic Warning

The AT91EB01 Evaluation Board is shipped in protective packaging. The board mustnot be subjected to high electrostatic potentials. A grounding strap or similar protectivedevice should be worn when handling the board. Avoid touching the component pins orany other metallic element.

3.2 Requirements Requirements in order to set up the AT91EB01 Evaluation Board are:

■ the host computer running the ARM Software Development Toolkit (a time-limited

evaluation copy is provided with the Kit version of the AT91EB01)

■ the AT91EB01 Evaluation Board itself

■ suitable connection between the host and the development board (see the following

sections)

■ DC power supply capable of supplying 7.5V to 9V @ 500 mA (not supplied)

3.3 Layout Following is the layout of the AT91EB01 evaluation board.

Figure 2. Layout of the AT91EB01 Evaluation Board

Setting up the AT91EB01 Evaluation Board


3.4 Jumper Settings LK2 is used to select the clock frequency and by default is set to 16,384 MHz. For moreinformation about this jumper and also the various surface mount links see “Appendix A- Configuration Links and SRAM Bank 1” on page 27.

3.5 Powering Up the Board

DC power is supplied to the board via the 2.1mm socket (J4) shown below in Figure 1.The polarity of the power supply is not critical. The minimum voltage required is 7V.

The board has a voltage regulator providing +3.3V. The regulator allows the input volt-age to be from 7V to 9V. When you switch the power on, the red LED marked "POWER"will light up. If it does not, switch off and check the power supply connections.

3.5.1 Measuring Current Consumption on the AT91M40400

The board is designed so as to generate the whole power supply of the AT91 device,and only the AT91 device through the wirelink WL2. This feature enables measure-ments to be made of the current consumption of the AT91 device.

3.6 Getting Started with the AT91EB01

In the following, it is assumed that:

■ the ARM Software Development Toolkit has been installed,

■ there are no default options for the APM tools, and

■ the directory “Bin\Config” of the ARM setup is empty (except “readme.txt”).

3.6.1 Testing the Board Connect the straight cable between Serial A and Serial B. With the FIQ button presseddown, power up the board, or generate a reset. The 3 LEDs (green, amber, red) light up.Release the FIQ. The 3 LEDs go off and then blink once.

Press the TIOB1 button. The red LED lights up. Release the TIOB1. The red LED goesoff. If the board has 512 Kbytes SRAM, the green LED blinks twice. If the board has2048 Kbytes SRAM, the green LED blinks four times.

Press the FIQ button. The amber LED lights up. Release the FIQ. The amber LED goesoff and the green LED blinks four times. If the green LED blinks twice and then the redLED blinks twice, the straight cable is not connected.

Press the IRQ0 button. The amber and red LEDs light up. Release the IRQ0. The LEDsgo off and the green LED blinks twice.

3.6.2 Building the Soft-ware Library

Copy the AT91 library (complete folder and sub-folder) onto your hard disk in a directoryreferred to in the following description as <MyFolderAT91>.

Copy/move the files from the directory “<MyFolderAT91>\Template” in the directory“Template” of the ARM setup.

Start the ARM Project Manager (APM).

Open the project “at91_l16” in the directory “<MyFolderAT91>\Library” and build the 16-bit THUMB library.

Open the project “at91_l32” in the directory “<MyFolderAT91>\Library” and build the 32-bit ARM library.

positive (+)ornegative (-)

2.1 mm connector



3.6.3 Use with the Angel Debugger

Build the project for the Angel Debug System variant.

■ Open the project “led_blink.apj” in the directory “<MyFolderAT91>\Examples\

led_blink”.

■ Select the variant “EB01SramAngel”, and build the application.

■ Connect the AT91EB01 on your host computer.

■ Connect the COM port of the PC with the SERIAL A port of the AT91EB01 using the

straight cable.

■ Check the SW1 switch is on the “LOWER_MEM” position.

■ Supply power to the AT91EB01: the amber LED lights up.

■ Configure the debugger to work with Angel:

■ Start the ARM Debugger for Windows (ADW) in Armulate Mode.

■ Activate the menu “Options – Configure Debugger”.

■ If not already done, add the “remote_a.dll” target environment to the debugger.

■ Select the target environment “remote_a.dll” and configure it:

- “Serial” Remote Connection

- Heartbeat enabled

- COMx port at 38400 baud

■ Select OK: the debugger starts communicating with Angel, displaying a small window

with transmit and receive counters.

■ The connection with Angel is established. In the console window is displayed:

Angel Debug Monitor (serial) 1.04 (Advanced RISC Machines SDT 2.11a) for

AT91EB0x(1.01)

Angel Debug Monitor rebuilt on Sep. 14 1998 at 14:52:22

Serial Rate: 38400

Load the Image and start the application:

■ Activate the menu “File – Load Image…“.

■ Select the file “led_blink.axf“ in the directory

”<MyFolderAT91>\Examples\led_blink\EB01SramAngel”: the debugger loads the

image, displaying a window with transmits and receives counter.

■ Select “Execute – Go” or press F5: the debugger stops on the main function,

displaying the C source file.

■ Select “Execute – Go” or press F5 again: the console window continuously displays

“Loop 0, Loop 1, …” and the amber and red LEDs are blinking.

3.6.4 Use with Embedded ICE

Build the project for the Embedded ICE Debug System variant.

■ Open the project “led_blink.apj” in the directory

“<MyFolderAT91>\Examples\led_blink”.

■ Select the variant “EB01SramICE”, and build the application.

■ Connect the AT91EB01 on your host computer.



■ Connect the COM port of the PC to the DB09 connector of the Embedded ICE Box

with the crossed cable (not delivered with the AT91EB01).

■ Connect the parallel port of the PC to the DB25 connector of the Embedded ICE Box

with the parallel cable (not delivered with the AT91EB01).

■ Connect the 14-pin connector of the Embedded ICE Box to the 20-pin JTAG

connector of the AT91EB01 through the Embedded ICE to the JTAG target connector.

■ Check the SW1 switch is on the “LOWER_MEM” position.

■ Supply power to the AT91EB01 and to the Embedded ICE: the amber LED and the

red LED on the EmbeddedICE light up.

■ Configure the debugger to work with Embedded ICE:

■ Start the ARM Debugger for Windows (ADW) in Armulate Mode

■ Activate the menu “Options – Configure Debugger”.

■ If not already done, add the “remote_a.dll” target environment to the debugger.

■ Select the target environment “remote_a.dll” and configure it:

- “Serial/Parallel” Remote Connection

- Heartbeat enabled

- LPTx port and COMx port at 115200 bauds

■ Select OK: the debugger starts communicating with the Embedded ICE, displaying a

small window with transmit and receive counters.

■ The connection with Embedded ICE is established. In the console window is

displayed :

EmbeddedICE Manager (ADP, ARM7TDMI) 2.04 (Advanced RISC Machines SDT 2.11)

Define the top of memory

■ Activate the menu “View – Debugger Internals … “

■ Double click on the “top_of_memory” parameter and redefine it to be “0x0220 0000”.

Load the Image and start the application:

■ Activate the menu “File – Load Image…”.

■ Select the file “led_blink.axf” in the directory

“<MyFolderAT91>\Examples\led_blink\EB01SramICE”: the debugger loads the

image, displaying a window with transmits and receives counter.

■ Select “Execute – Go” or press F5: the debugger stops on the main function,

displaying the C source file.

■ Select “Execute – Go” or press F5 again: the console window continuously displays

“Loop 0, Loop 1,…” and the amber and red LEDs are blinking.

3.6.5 Use with the Multi-ICE Debugger

The procedure is the same as for EmbeddedICE (see “Use with Embedded ICE” onpage 9) except that the Multi-ICE Debugger for Windows (MDW) is used in place ofADW. The mode is automatic with Multi-ICE; the configuration of the debugger is use-less.



3.6.6 Programming and Executing in Flash

Open the project “led_blink.apj” in the directory “<MyFolderAT91>\Examples\ led_blink”.

Select the variant “EB01Flash”, and build the application.

Power up the AT91EB01 and establish a debugger (any one) with the target. Refer tothe sections above.

Execute the programming sequence (as described in the section “Using the FlashDownloader” on page 19):

$top_of_memory=0x02200000

load < MyFolderAT91 >\Tools\at91eb01\flash.li <MyFolderAT91>\Exam-ples\led_blink\EB01Flash\led_blink.axf 0x01010000

g

The flash programmer displays the following in the Console Window :**** AT91EB01 Flash Programming Utility ****

Trying to identify Flash at base address (0x1010000)

Flash recognised : AT29LV1024

Input file is : <filename>

Load address is: 0x1010000

Programming flash ("." = 1 sector)

................

........

Flash written and verified successfully

Start the application:

■ Exit from the debugger

■ Set the SW1 switch on the UPPER_MEM position

■ Reset the AT91EB01

The amber and red LEDs blink.

3.7 Booting with the Flash

3.7.1 Flash Memory Organization

The Flash memory is an AT29LV1024 (64K x 16). It is arbitrarily located at the address0x01000000 by the boot software (see “Programmer’s Model” on page 23). It has beensplit in two different spaces :

■ 0x01000000 up to 0x0100FFFF = boot and Angel software

■ 0x01010000 up to 0x0101FFFF = application software

The switch SW1 allows the signal “SW_A16” to be set (see Schematic 3 “External BusInterface”) which drives the bit A15 of the flash part:

■ “LOWER MEM” uses the bit A16 of the AT91M40400. The entire flash can be reached

by the AT91M40400, and the boot software at location 0x01000000 is executed at the

reset.

■ “UPPER MEM” uses the Vcc. Only the upper 64K can be reached, at the location

defined by the application software executed at the reset.

It is important to note that the examples provided by the AT91 library set up the EBI with:

■ Flash at address 0x01000000

■ SRAM at address 0x02000000



Nevertheless, when SW1 is set with “UPPER_MEM”, these addresses are under userapplication responsability.

At delivery, the flash is programmed with the following software:

■ Boot from 0x01000000 up to 0x01001FFF,

■ Angel from 0x01002000 up to 0x0100FFFF, and

■ Demo application from 0x01010000 up to 0101FFFF.

3.7.2 Flash Write Access The upper 64K of the Flash can be overwritten by using the Flash downloader (see“Using the Flash Downloader” on page 19) whatever the position of the switch SW1.This can also be done by using Angel rather than the Embedded ICE.

The lower 64K are write protected whatever the position of the switch SW1. This is toprevent the boot and Angel software stored in the lower 64K bytes from being erased.

Nevertheless, it is always possible to make this space unprotected by setting a jumperor a link on the footprint J7.

Note: If the lower 64K are not protected, the user must be especially careful. Even though one of the features of the boot is the ability to restore Angel, it cannot be saved itself. Once it is overwritten, the only way to restore the Flash is to use an Embedded ICE.

3.7.3 The Boot Software The boot software is started at the reset if SW1 is switched to ”LOWER MEM”.

It first initializes the EBI (see “Programmer’s Model” on page 23), then executes theREMAP procedure (see the AT91M40400 datasheet), and then checks the state of thebuttons:

■ If the button FIQ is pressed, all the LEDs are lit, and the Functional Test Software

(FTS) is activated

■ If the button TIOB1 is pressed, the red LED is lit, and the SRAM downloader is

activated

■ If neither TIOB1 nor FIQ are pressed, the amber LED is lit and Angel is activated.

The code sources of the boot software are included in the AT91 library in the folder“<MyFolderAT91>\Tools\BootEb01”.

3.7.4 The Functional Test Software (FTS)

The FTS is a part of the boot software which allows testing of the AT91EB01. It isstarted by the boot if the FIQ button is pressed at reset. At start of the FTS, the LEDs 1,2 and 3 light up. The user must then release the FIQ button. The LEDs switch off, andthen blink once.

The FTS then waits for one of the following user actions on the buttons:

■ If the TIOB1 button is pressed, the memory size is checked and the green LED blinks:

- 1 = 256K bytes

- 2 = 512K bytes

- 3 = 1024K bytes

- 4 = 2048K bytes

■ If the FIQ button is pressed, the USART are tested:

- Transfer one character from USART 0 to USART 0 (loopback mode)

- Transfer one character from USART 1 to USART 1 (loopback mode)

- Transfer one character from USART 0 to USART 1 (normal mode)

- Transfer one character from USART 1 to USART 0 (normal mode)



For each case, the green or the red LED blinks once following the positive or nega-tive result of the test. Note that the 2nd and 3rd tests can succeed only if the straightserial cable (provided) is connected between SERIAL A and SERIAL B.

■ If the IRQ0 button is pressed, the buses of the SRAM are tested:

- Address bus

- Data bus

In each case, the green or the red LED blinks once following the positive or negativeresult of the test.

3.7.5 The SRAM Downloader

The SRAM downloader is a part of the boot software and allows an application in theSRAM to be loaded at the address 0x02000000, then activated. It is started by the bootif the button TIOB1 is pressed at reset.

The procedure is as follows:

1. Connect the AT91EB01 to the host PC using either the straight serial cable (pro-vided) on the serial A, or a crossed serial cable (not provided) on the serial B.

2. Set the clock frequency (LK2) to the desired frequency. Note that this directly determines the baud rate for the download (cf. table below).

3. Generate a power on or a RESET with the TIOB1 pressed down.Wait for the red LED to light up and then release the TIOB1 button.

4. Start the BINCOM utility, located in the folder “<MyFolderAT91>\Tools”, on the host computer: Select the port and the baud rate for communications, then open the file to download and send it. Wait for the end of the transfer.

5. Press the button IRQ0 to terminate the download. The control is switched to the address 0x02000000.

If the downloaded program is Angel, start the ARM debugger (first exit BINCOM). Referto the section “Communicating with Angel” on page 17 for more details.

The following table shows the relationship between the clock rate on the board, and theserial baud rate:

Table 1. Clock Rate vs. Serial Baud Rate

Note that if the debugger is started through ICE while the SRAM downloader is on, thenboth serial channels are enabled.

3.7.6 The Angel Monitor The Angel monitor is located in the flash from 0x01002000 up to 0x0100FFFF. It isstarted by the boot if neither TIOB1 nor FIQ are pressed at reset. Refer to the section“Communicating with Angel” on page 17 and “Using Angel” on page 19 for more details.

The latest version of the Angel debugger is included in the AT91 library in the folder“<MyFolderAT91>\Tools“, file “Angeleb01.exf”. The file “Angeleb01.txt” contains the cor-responding prompt printed in the Console window at Angel startup.

The Angel on the AT91EB01 can be upgraded regardless of the version programmed onit. Refer to the section “Using the Flash Downloader” on page 19 for more details.

Note that if the debugger is started through ICEe while the Angel monitor is on, theAdvanced Interrupt Controller (AIC) and the USART channel are enabled.

3.8 Communicating with Embed-dedICE

The following elements are required:

■ AT91EB01 Evaluation Board

■ EmbeddedICE interface unit with its 14-way ribbon cable

Frequency Serial A Serial B

16 MHz 57600 19200

32 MHz (MASTER) 115200 38400



■ EmbeddedICE to Multi-ICE adapter (supplied with the EmbeddedICE interface)

■ 9-pin RS-232 cable (not supplied with the AT91EB01)

■ 25-pin parallel cable (optional, not supplied with the AT91EB01)

■ Two DC power supplies, 7.5V - 9V @ 500 mA (not supplied)

3.8.1 Connecting the EmbeddedICE Unit

To communicate between the host computer and the target system using the Embed-dedICE interface:

1. Connect the serial cable between the 9-pin serial port on the EmbeddedICE interface and the serial communications port of the host PC.

2. Connect the parallel port cable between the 25-pin parallel port connector on the EmbeddedICE interface and the printer port on the host PC. (This is not essen-tial, but will speed up download.)

3. Connect the EmbeddedICE interface to an external DC power supply, 500 mA or greater (not supplied).

4. Note that the interface has diode protection to prevent reversed supplies from damaging the board. For correct operation, the 2.1 mm power connector should have the positive supply connected to the center pin.

5. Power up the EmbeddedICE interface and press the red reset button.

6. On releasing the reset button, the LED on the unit lights up. If the LED immedi-ately blinks off once for a fraction of a second, the software version is Remote Debug Protocol (RDP) compatible, not Angel Debug Protocol (ADP) compatible.

7. Power up the evaluation board as detailed above.

8. Connect the EmbeddedICE interface unit to the target evaluation board using a 14-way ribbon JTAG cable and the EmbeddedICE to Multi-ICE adapter. The JTAG connection on the evaluation board is located on the same edge as the “Host PC” DB9 connector and the DC-power connector and is labeled “JTAG” (J2). Refer to the Layout diagram above.

3.8.2 Configuring the ARM Debugger for Windows to Use EmbeddedICE

To configure the ARM Debugger for Windows (ADW) to access a remote target ratherthan the ARMulator:

1. Start the ADW (not via the ARM Project Manager). In its default state, a message similar to the following is displayed in the console window:ARMULATOR 2.0 [Jan 6 1997]ARM7DTMI, 15.0MHz, 4Gb, Dummy MMU, Soft Angel

1.4,[Angel SWIs, Demon SWIs],FPE, Profiler, Tracer, Little endian

2. Choose “Configure Debugger...” from the Options menu. The Debugger Configu-ration property sheet is displayed.

3. Click on the “Target” tab.

4. Select “Remote_A” for ADP-compatible EmbeddedICE units.

Note: If you are using an older RDP version of the EmbeddedICE unit (the LED blinks on-off-on at reset),

5. Add the configuration file Arm21x\Bin\remote_d.dll for the Target Environ-ment and select “Remote_D”. Alternatively, upgrade your EmbeddedICE ROM (see http://www.arm.com for the latest version).

6. Click on “Configure...”

7. If you are using both serial and parallel cables, select “Serial/Parallel from Remote Connection”. If you are using only a serial cable, select “Serial”.

8. Select the serial and parallel communication ports, and the serial line speed. (The AT91 Evaluation Board operates at up to 38400 bps.)

9. Click on “OK”.



10. To select little-endian mode, click on the Debugger tab, and click on “Little” in the Endian selection.


The debugger is restarted. The Restarting dialog box is displayed. Rapidly changingnumbers are shown, indicating reading and writing to the target.

Note: If the target board does not respond (the numbers in the Restarting dialog box do not change), ADP times out within approximately five seconds and defaults back to ARMulator.

When the configuration has completed successfully, a message similar to the followingis displayed in your host console window:

EmbeddedICE Manager (ADP ARM7TDI) 2.01 (Advanced RISC Machines)

When you start EmbeddedICE, it automatically defaults to a particular configurationaccording to which version of the interface software is installed:

■ versions up to 1.03 default to ARM7DI

■ versions after this default to ARM7TDI

If any of the following messages are displayed when you start up the debugger or reloadan image, you must reconfigure the EmbeddedICE:

Error during initialization:

Recoverable error in RDI initialization

Target processor not stopped

Note: Ensure that the selected configuration is correct, otherwise problems may arise when you run a program.

To configure the EmbeddedICE interface:

1. Choose “Configure EmbeddedICE” from the Options menu.

2. Do one of the following:

- Choose the name from the list and type in the version. You can usually type any forthe version. Click on “Select”.

- Load a new agent: click on “Load Agent...”, select the required agent file (usuallyfound in ARM21x\Angel\Images\iceagent), and then click on “Open”.

- Load a new configuration file: click on “Load Config...”, select the required configu-ration file, and then click on “Open”. The required configuration data is usually con-tained within the agent itself, so this option is seldom used.


When the debugger closes down, the remote debugging option settings are stored inmemory. Thus at the next use of the debugger, the options may be recalled automati-cally.

3.8.3 Configuring the armsd Debugger to Use EmbeddedICE

When initializing armsd using EmbeddedICE, it is necessary to tell armsd the endian-ness of the target. This contrasts with running Angel, or using ARMulator, where there isa default endianness (little-endian).

To configure for a little-endian target using EmbeddedICE version 2.0 or later, the stan-dard serial and parallel ports, and the default linespeed (9600 bps), enter:

armsd -li -adp -port s,p

To use serial port 2 (rather than serial port 1), and line speed of 38400, enter: armsd -li -adp -port s=2,p -linespeed 38400

where:

-li is the little-endian switch

-adp is the switch to allow communication using the ARM Debug Protocol required by Angel



-port s=2,p indicates that the serial port is port 2 on the host computer, and the parallel port is the standard port. The serial and parallel ports can be shown numerically (1 or 2) or be the host device name required

-linespeed 38400 sets the baud rate for serial communications between the host computer and the Development System.

If you are using a version of EmbeddedICE earlier than 2.00 (that uses RDP rather thanADP communication), enter:

armsd -li -serpar

When you enter the correct command, the host displays the debugger's opening ban-ner, similar to:

A.R.M. Source-level Debugger vsn 4.46 (Advanced RISC Machines SDT 2.10)[Dec13

1996] EmbeddedICE Manager (ADP ARM7TDI) 2.01 (Advanced RISC Machines)

The following commands enable you to access EmbeddedICE configuration and agentfacilities from within armsd:

listconfig lists the configurations known to the debug agent. Note that the first configuration listed is the default for the version of the agent in use

selectconfig name version specifies the target configuration to use

where:name indicates the configuration to use, typically

ARM7DI or ARM7TDI

version indicates the version to be used:

any accepts any version (default)

n must use version n

n+ must use version n or later

The highest numbered version meeting the version constraint is used.

loadagent file downloads the replacement agent software into EmbeddedICE and starts it in RAM, rather than using the one in NUM. See the “ARM Software Development Toolkit User Guide” (ARM DUI 0040) for further details

loadconfig file specifies the file containing configuration data to be loaded. Note that this option is seldom needed because the required configuration data is usually contained within the agent itself

For further information on using EmbeddedICE, see the “ARM Software DevelopmentToolkit User Guide (ARM DUI 0040)”.

3.9 Communicating with Multi-ICE

The following is required:

■ AT91EB01 Evaluation Board

■ Multi-ICE interface unit with its 20-pin ribbon cable

■ 25-pin parallel cable

■ DC power supply, 7.5V - 9V @ 500 mA (not supplied)



3.9.1 Connecting the Multi-ICE Unit

To communicate between the host computer and the target system using the Multi-ICEinterface:

1. Connect the parallel port cable between the 25-pin parallel port connector on the Multi-ICE interface and the printer port on the host PC.

2. Connect the Multi-ICE interface unit to the target evaluation board using the 20-way ribbon JTAG cable. The JTAG connection on the evaluation board is located on the same edge as the “Host PC” DB9 connector and the DC-power connector and is labeled “JTAG” (J2).

3. Power up the evaluation board as described above.

3.9.2 Configuring the Mul-tiprocessor Debug-ger for Windows to Use Multi-ICE

To configure the Multiprocessor Debugger for Windows (MDW) to access a remote tar-get rather than the ARMulator:

1. Start Portmap.

2. Start the Multi-ICE Server.

3. When the Multi-ICE Server has loaded, click on the auto-configure icon. This should detect the ARM7TDMI RISC core. If not, manually select it - refer to the Multi-ICE manual.

4. Load MDW.

5. Choose “Configure Debugger...” from the Options menu. The Debugger Configu-ration property sheet is displayed.


7. If this is the first time using Multi-ICE, click on “add” and select multi-ice.dll. If not jump to step 9.


9. Select “Multi-ICE”.

10. Click on “Configure...”

11. In the “Location” box, enter “localhost” if the host PC is the PC you are using or, if another PC is the host, enter the Host PC’s network name.

12. Check that the correct core is shown in the “Processor Driver Selection” box.

13. Enter a name for the “Connection name”. The user’s name is a good idea.


15. Select little-endian mode (the AT91 Evaluation Board is little-endian only), click on the Debugger tab, and click on “Little” in the Endian selection.



Note: If the target board does not respond (the numbers in the Restarting dialog box do not change), ADP times out within approximately five seconds and defaults back to ARMulator.

Before running the application, set the variable:$top_of_memory=0x02200000

This can be done using the “Command” window or the “Debugger Internals” window.

3.10 Communicating with Angel

Note: System development using Angel is subject to special considerations. These are documented in “Application Note 43: Design Considerations when using Angel Debug Monitors” (ARM DAI 0043).

3.10.1 Serial Host Connec-tion

Connect the host computer to the Serial A port USART on the AT91 Evaluation Boardusing a 9-pin RS-232 cable. Power up the board (see “Powering Up the Board” onpage 8).



3.10.2 Configuring the ARM Debugger for Windows to Use Angel

To configure the ARM Debugger for Windows (ADW) to access Angel rather than theARMulator:

1. Start the ADW (not via the ARM Project Manager). In its default state, a message similar to the following is displayed:ARMULATOR 2.0 [Jan 6 1997]ARM7DTMI, 15.0MHz, 4Gb, Dummy MMU, Soft Angel

1.4,[Angel SWIs, Demon SWIs],FPE, Profiler, Tracer, Little endian

2. Choose “Configure Debugger...” from the Options menu.


4. Select “Remote_A”.

5. Click on “Configure...” and select “Serial”.

6. Select the serial communication port and line speed. (The AT91 Development Board operates at up to 57600 bps).



Note: If the target board does not respond (the numbers in the Restarting dialog box do not change), ADP times out within approximately five seconds and defaults back to ARMulator. When the configuration has completed successfully, a mes-sage similar to the following is displayed in the host console window:

Angel Debug Monitor (serial) 1.04 (Advanced RISC Machines SDT 2.11a) for

AT91EB0x(1.01)

Angel Debug Monitor rebuilt on Sep. 14 1998 at 14:52:22

Serial Rate: 38400

3.10.3 Configuring the armsd Debugger to Use Angel

To operate armsd with Angel using a serial connection, type:armsd -li -adp -port s=1 -linespeed 38400

where:-li is the little endian switch

-adp is the switch to allow communication using ARM Debug Protocol required by Angel

-port s=1 indicates that the serial port is port 1 on the host com-puter.Type the serial port number (1 or 2) or the host device name

-linespeed 38400 sets the baud rate for serial communications between the host computer and the Development System

When this command is entered, the host displays the debugger's opening banner, whichwill be similar to:

A.R.M. Source-level Debugger vsn 4.46 (Advanced RISC Machines SDT2.10) [Dec

13 1996] Angel Debug Monitor for AT91 (serial) 1.04 (Advanced RISC Machines

SDT 2.11a)

Note: The options available for armsd can be viewed by typing armsd -h at the com-mand line.



3.11 Using Angel Angel has been ported on the AT91EB01 so that the majority of features of theAT91M40400 are available to the application. The Angel Debug Monitor is intrusive.Therefore, this implies some limitations on the use of the resources:

■ USART 0 is reserved for communications with the debugger.

■ A Flash space is used for code saving.

■ A SRAM space is used for code running, data and stacks of Angel.

■ Care must be taken with the stacks and the interrupt handling.

3.11.1 Memory Mapping Angel is stored in the Flash from address 0x0100 2000, and occupies with the boot theentire lower 64K bytes of the Flash. When started, Angel automatically copies itself intothe SRAM at address 0x0200 8000. This allows faster execution than if running from theFlash; moreover, Angel can be used by the Flash programmer.

Stacks and variables needed by Angel are based from 0x0200 0000 up to 0x0200 7FFF.As 64K bytes are reserved for Angel and its future versions, it is mandatory to link anyapplication running in SRAM at addresses higher than 0x0201 8000. Otherwise, thedownload of the image will overwrite Angel’s code, and communications between Angeland the debugger will be lost.

3.11.2 Interrupt Handling The Angel’s interrupt handling uses the vectoring feature of the AT91’s Advanced Inter-rupt Controller. This implies that the ARM Interrupt vector ( at address 0x18 ) is set withthe instruction “ldr pc, [pc, #&-F20]” in order to access AIC_IVR.This is assumed byAngel itself.

If the user wants to use Interrupt Vectoring, he just has to store the handler addresses inthe AIC_SVR, and to set the AIC_SMR.

If he does not want to use this feature, he has to replace the ARM vector, then in thenew defined interrupt handling, to test if the interrupt which has occurred comes fromthe USART 0 ( Interrupt source number 2 ) and, in this case, branch at address saved inAIC_SVR[2].

3.11.3 Stacks Setup As Angel needs to manage interrupts, it initializes the Interrupt stack pointer (r14_irq).This register cannot be modified by the application without disagreement on the Angelcommunications.

Other stack pointers are also initialized by default by the Angel startup sequence. Par-ticularly, user mode stack is initialized at the top of the memory. As this last differsdepending on the version of the AT91EB01, it is fixed at 0x0204 0000.

3.12 Using the Flash Downloader

3.12.1 Flash Downloading with ADW & MDW

Downloading into Flash overwrites any existing image already stored there. This may bea version of Angel, or an application program. Ensure that the download completes suc-cessfully before you reset or power off the board.

The flash downloader for the AT91EB01 is based on the flash downloader utility pro-vided with the ARM Software Development Toolkit. With Angel, it works only if Angel isrunning from RAM, and not from the flash that is to be programmed. AlternativelyEmbeddedICE or Multi-ICE can be used rather than Angel.

The f l ash down loader i s i nc luded by the AT91 l i b ra ry i n the fo lde r“<MyFolderAT91>\Tools\FlashPgm\at91eb01“, file “flash.li”. This file can be used withAngel as well as with EmbeddedICE or Multi-ICE.



The download can be done by different ways :

■ with an ICE (Embedded or Multi).

■ with Angel started in flash by the boot and auto-copied in SRAM before execution

(refer to the section Memory Mapping in “Using Angel” on page 19).

■ with Angel downloaded and started by the SRAM downloader (see “The SRAM

Downloader” on page 13). The file to download is

“<MyFolderAT91>\Tools\Angeleb01.axf”.

Angel is started by pressing the button IRQ0, then the connection with the debugger canbe established.

Once the connection is established between the debugger on the PC and Angel/ICE onthe target, following steps must be performed to download a new image in flash :

1. Set the top of the memory for the debugger (ADW & MDW only):$top_of_memory=0x02200000

2. Load the flash programmer and set the arguments :load <MyFolderAT91>\Tools\FlashPgm\at91eb01\flash.li <filename>

<address>

where:filename is the file name (including the path) to download and programaddress is the address where the file is programmed (generally 0x01010000)

3. Activate the debugger:g

The flash programmer displays the following in the Console Window :

**** AT91EB01 Flash Programming Utility ****Trying to identify Flash at base address (0x1010000)Flash recognised : AT29LV1024Input file is : <filename>Load address is: 0x1010000 Programming flash ("." = 1 sector)........................Flash written and verified successfully

The sequence described above can be automatically executed by using a command file.Build a file <command_file> with the commands :

$top_of_memory=0x02200000load <MyFolderAT91>\Tools\FlashPgm\at91eb01\flash.li <filename> <address>g

and then execute the file by entering the command:

ob <command_file>Another way is by using the item “Flash Download” in the menu “File” of the debugger.For this, the file “flash.li” must be previously copied in the current directory or in the “bin”directory of the ARM setup. The arguments are <filename> and <address> .

In the case where the boot software has been overwritten, and before any use of theflash downloader, the EBI must be programmed :

EBI_CSR0: 0xFFE00000=0x01002535

EBI_CSR1: 0xFFE00004=0x02002121

REMAP done: 0xFFE00020=1

2M bytes per CS: 0xFFE00024=6



A command file called “ebi_eb0x” which performs the default EBI configuration is avail-able in “<MyFolderAT91>\Tools”.

3.12.2 Upper 64K Flash Downloading

The upper 64K Flash can be used to program then execute an application software (seethe section “Booting with the Flash” on page 11).

To have the application software executed at reset, the switch SW1 must be set with theposition “UPPER MEM”. Therefore, the image must be generated with a “Read only”space based at the address 0x01000000.

To download the application software in Flash, the switch SW1 must be set with theposition “LOWER MEM”. The argument <address> of the <load> command must be0x01010000.

The table below summarizes the address of the upper 64K Flash following the action:

Note: The address 0x0100000 for the “Read Only” space has been chosen so as to differentiate it from the address used by the boot software. Since the RESET is done by the application itself, any address above 0x00400000 (and allowed by the EBI) can be chosen.

3.12.3 Lower 64K Flash Downloading

The lower 64K of the Flash can be downloaded (e.g. to update an Angel version). To doso, the switch SW1 must be set with the position “LOWER MEM”, and the lower 64Kmust be unprotected by setting a jumper or a link on the footprint J7 (see section “Boot-ing with the Flash” on page 11). In any case, when an attempt to download the lower64K is done, the Flash downloader asks for a confirmation.Extra caution is required when the lower 64K are not protected. If the download fails or ifthe Flash is overwritten:

■ Angel can be restored by using the SRAM downloader (see “Angel Upgrade” on

page 21)

■ the boot can be restored only by using an ICE (Embedded or Multi)

3.12.4 Angel Upgrade Angel can be upgraded in the lower part of the flash. For this, it is mandatory to set ajumper on J7 in order to allow the writes to the lower part of the flash (see section“Lower 64K Flash Downloading” on page 21).

Execute the sequence described in the section “Flash Downloading with ADW & MDW”on page 19. The command is :

load <flash> <angel> 0x01002000

where:flash is the file “Tools\FlashPgm\at91eb01\flash.li” including the pathangel is the file “Tools\Angeleb01.axf” including the path0x01002000 is the address where Angel is started by the boot

Action Button SW1 Address

Downloading UPPER MEM 0x01010000

Executing LOWER MEM 0x01000000




Section 4

Programmer’s Model

4.1 Memory Map The memory map can easily be changed by reprogramming the external bus interface.This section details the default memory map that is set up by the Angel debug monitor.

Table 2. Memory Map

Name Address Size

Peripheral Devices HFFFFFFFF

HFFD00000

3M bytes

undefined

External Memory [7] H7FFFFFFF

H70000000

1, 4, 16 or 64M bytes - not used

undefined


H60000000

1, 4, 16 or 64M bytes -

not used

undefined


H50000000


undefined


H40000000


undefined


H30000000

1, 4, 16 or 64M bytes -

not used

undefined


H20000000


undefined


H02000000

256K bytes to 2048K bytes 16-bit SRAM - 4M bytes page size

undefined

Programmer’s Model


Note: For the peripheral memory map, refer to the AT91M40400 datasheet.

External Memory [0] H01FFFFFF

H01000000

128K bytes 16-bit Flash - 1M byte page size

undefined

On-chip RAM (reboot) H00300FFF

H00300000

4K bytes

Reserved On-chip device H002FFFFF

H00200000

1M byte

Reserved On-chip device H001FFFFF

H00100000

1M byte

On-chip RAM (normal) or External ROM (reboot)

H00000FFF

H00000000

4K bytes

Table 2. Memory Map (Continued)

Name Address Size


Section 5

Circuit Description

5.1 AT91EB01 Top Level

The top level schematic in “Appendix B - Schematics” on page 29 shows the blocks inthe system. Each block is described in the appropriate section below.

5.2 AT91M40400 Processor

This schematic shows the AT91M40400. The footprint is for a 100-pin TQFP package.

Wirelink (WL2) can be removed by the user to allow measurement of the currentdemand by the microcontroller.

5.3 I/O Expansion The I/O Expansion connector makes available to the user the General Purpose I/O(GPIO) lines, VDD and Ground. Surface mount links 5, 6, 7, 8 and 9 are used to selectbetween the I/O lines being used by the evaluation board or by the user via the I/Oexpansion connector. The connector is not fitted at the factory; however, the user can fitany 17 x 2 connector on a 0.1" (2.54 mm) pitch.

5.4 External Bus Interface

This schematic shows one AT29LV1024-15JC 128K bytes 16-bit Flash and four 512K x 8 SRAM devices.

Note: The AT91EB01 is fitted with four 128K x 8 SRAM devices.

The schematic also shows the Bus Expansion connector which, like the I/O Expansionconnector, is not fitted at the factory. The user can fit any 32 x 2 connector on a 0.1"(2.54 mm) pitch to gain access to the data, address, chip select, read/write, oscillatoroutput, and wait state pins. Pin 8 on this connector can be used to apply an externalclock frequency to the board assuming the clock select jumper is fitted accordingly (seeAppendix A). VDD and Ground are also available on the connector.

Switch 1 shown on this schematic is used to select either Read only access of all loca-tions in Flash or allow Read/Write access to the top 64K bytes. This is to prevent theAngel Debug Program which is stored in the lower 64K bytes from being erased.

5.5 Power, Crystal Oscillator and Clock Distribu-tion

The system clock is derived from a single 32.768 MHz crystal oscillator. This is dividedby a 4-bit binary counter to give alternate clock frequencies of 32.768 MHz divided by 2,4 or 8. The system clock frequency is selected by fitting a jumper link in one position ofthe link field (LK2) and details of this can be found in Appendix A. One position in LK2selects an external oscillator to be applied via the Expansion Bus Interface.

The Voltage Regulator provides 3.3V to the board and will light the red POWER LEDwhen operating. Power can be applied via the 2.1 mm connector to the regulator ineither polarity because of the diode rectifying circuit. The regulators can tolerate supplytransients to 30V although they will shut down without damage if they overheat.

Circuit Description


5.6 JTAG Interface, Reset, Interrupts & LEDs

An ARM-standard 20-pin box header (J2) is provided to enable connection of anEmbeddedICE interface (using an EmbeddedICE to Multi-ICE adapter) or Multi-ICEinterface to the JTAG inputs on the AT91. This allows code to be developed on theboard without the use of system resources such as memory and serial ports.

The IRQ, FIQ and TIOB0 switches are debounced and buffered. A supervisory circuithas been included in the design to detect and consequently reset the board when the3.3V supply voltage drops below 3.08V. It also provides a debounced reset signal.

The schematic also shows LEDs 1, 2 and 3 which are for general purpose use and areconnected to timer (or I/O) pins TIOA0/P1, TIOA1/P4 and TIOB0/P2.

5.7 Serial Interface Two 9-way D-type connectors (J5/6) are provided for serial port connection. Serial portA (J5) is used primarily for Host PC communication and is a DB9 Female connector.TXD and RXD are swapped so that a straight through cable can be used. CTS and RTSare connected together as is DCD, DSR and DTR.

Serial port B (J6) is a DB9 male connector with TXD and RXD obeying the standard RS-232 pinout. Apart from TXD, RXD and ground, the other pins are not connected.

RS-232 level conversion is provided by a MAX3223 device (U13) and associated bulkstorage capacitors.

5.8 Layout Drawing The layout diagram schematic shows an approximate floorplan for the board. This hasbeen designed to give the lowest board area, whilst still providing access to alltestpoints, links and switches on the board.

The size is approximately 4.5 inches square with four mounting holes, one at each cor-ner, into which feet are attached. The board has two signal layers and two powerplanes.


Section 6

Appendix A - Configuration Linksand SRAM Bank 1

6.1 Jumpers (LK2) The LK2 jumper is used to select the clock frequency. The frequency options are 32,768MHz, 32.768 MHz divided by 2, 4 or 8, or an external clock applied via the ExpansionBus interface.

6.2 Surface Mount Links (LK1,LK3-9)

By adding the I/O expansion and the Bus Expansion Connectors the user can add ownperipherals to the evaluation board. These peripherals may require more I/O lines thanavailable while the board is in its default state. Extra I/O lines can be made available bydisabling some of the on-board peripherals. This is done using the surface mount linksdetailed below. If these links need to be changed then a fine-tipped soldering iron isrequired. All links are 0R 0805 resistors unless stated otherwise.

LK1 should be left unaltered unless a memory upgrade is required. If this is the case,see the section headed “Increasing Memory Size” on page 28.

Note: Use a 10K resistor

LK21 3 5 7 9

2 4 6 8 10

EBI MAST /2 /4 /8

LK1 Function

A-C A18 is used as the chip select for SRAM bank1. Should be in this position for 128K x 8 SRAMs

B-C A20 is used as the chip select for SRAM bank1. Should be in this position for 512K x 8 SRAMs

LK3 Function

A-C Alternate boot mode NOT selected

B-C Alternate boot mode selected

Appendix A - Configuration Links and SRAM Bank 1


Note: Use a 10K resistor

6.3 Increasing Mem-ory Size

The AT91EB01 is supplied with four 128K x 8 byte SRAM memories. If, however, theuser needs more than 512K bytes of memory, the devices can be replaced with four512K x 8 3.3V 15/20 ns SRAMs giving in total 2048K bytes. If this is done, LK1 must bemoved to position B-C.

Note: The user must either have 128K x 8 SRAMs or 512K x 8 SRAMs fitted in Bank 0 and, if desired, Bank 1. The two SRAM sizes cannot be mixed.

LK4 Function

A-C RXD lines are set tri-state on the RS-232 transceiver so that the receiver signals to AT91 can be used for external I/O via the I/O connector

B-C Receive pins on AT91 used by on board serial ports

LK5 Function

A-C TXD0 connects to I/O connector

B-C TXD0 connects to RS-232 Transceiver

LK6 Function

A-C AT91 IRQ0 pin connects to I/O connector

B-C AT91 IRQ0 input is from IRQ switch

LK7 Function

A-C AT91 FIQ pin connects to I/O connector

B-C AT91 FIQ input is from FIQ switch

LK8 Function

A-C TXD1 connects to I/O connector

B-C TXD1 connects to RS-232 Transceiver

LK9 Function

A-C TIOB1 connects to I/O connector

B-C AT91 TIOB1 input is from TIOB1 switch


Section 7

Appendix B - Schematics

The following schematics are appended:

Figure 3. AT91M40400 Evaluation Board

Figure 4. PCB Layout

Figure 5. External Bus Interface

Figure 6. JTAG Interface, Reset, Interrupts and LEDs

Figure 7. I/O Expansion

Figure 8. Power, Crystal Oscillator and Clock Distribution

Figure 9. AT91M40400 in TQFP Package

Figure 10. Serial Interface

The pin connectors are indicated on the schematics:

• J1 = EBI Expansion - External Bus Interface (Figure 5)

• J2 = JTAG Interface - JTAG Interface, Reset, Interrupts & LEDs (Figure 6)

• J3 = I/O Expansion - I/O Expansion (Figure 7)

• J5 = Serial A - Serial Interface (Figure 10)

• J6 = Serial B - Serial Interface (Figure 10

Appendix B - Schematics


Schematics


Figure 3. AT91M40400 Evaluation Board

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TX

D[1

..0]

RX

D[1

..0]

TC

LK

[2..0]

IRQ

[2..0]

P1

2/F

IQT

XD

_O

NB

[1..0]

P12/F

IQ_O

NB

TIO

B1_O

NB

NW

DO

VF

P23

P[1

9..16]

IRQ

0_O

NB

P24/B

MS

EB

I

EB

IA[2

3..0]

D[1

5..0]

NW

R1/N

UB

NW

R0/N

WR

NC

S[3

..0]

NR

D/N

OE

P25/M

CK

O

NW

AIT

EB

I_M

CK

I

NR

ST

D[1

5..0]

A[2

3..0]

TIO

A[2

..0]

TIO

B[2

..0]

TC

LK

[2..0]

IRQ

[2 ..0

]

AT

91C

LKP

25

/MC

KO

P12/F

IQ

TC

KT

DI

TD

OTM

S

NC

S[3

..0]

TX

D[1

..0]

RX

D[1

..0]

SC

K[1

..0]

NW

R1/N

UB

NR

D/N

OE

NW

R0/N

WR

NW

AIT

NW

DO

VF

NR

ST

P23

P[1

9..16]

TMS

TD

IT

DO

NR

ST

TC

K

RX

D[1

..0]

AT

91C

LKE

BI_

MC

LK

TX

D_O

NB

[1..0]

TIO

B1

_O

NB

P12/F

IQ_O

NB

TIO

A0

TIO

A1

TIO

B0

IRQ

0_O

NB

IRQ

0_O

NB

TIO

B1

_O

NB

TIO

B[2

..0]

RX

D[1

..0]

SC

K[1

..0]

IRQ

[2 ..0

]P

12/F

IQ

P23

P[1

9..16]

NW

DO

VF

TIO

A[2

..0]

P12/F

IQ_O

NB

TC

LK

[2..0]

TX

D_O

NB

[1..0]

TX

D[1

..0]

P2

4/B

MS

P2

4/B

MS

NW

R0/N

WR

NW

AIT

P2

5/M

CK

OE

BI_

MC

LK

D[1

5..0]

NC

S[3

..0]

NW

R1/N

UB

A[2

3..0]

NR

ST

NR

D/N

OE

Schematics

Schematics


Figure 4. PCB Layout

1 1

2 2

3 3

4 4

5 5

6 6

7 7

8 8

AA

BB

CC

DD

LAY

OU

T S

UG

GE

ST

ION

SPDT

2x5

head

er

2x32

hea

der

2x17 header

LT1086

OSC.

AT

91M

40X

0XM

AX

3223

MA

X63

15

74LV14D

74LV161

FLA

SH

CHASSIS PLANE

GR

OU

ND

PLA

NE

&V

DD

PLA

NE

ST

AR

PO

INT

HO

LE H

AS

CO

NT

AC

TW

ITH

CH

AS

SIS

PLA

NE

DB

9 S

OC

KE

T

DB

9 P

LUG

JTA

G IN

TE

RFA

CE

(20

WA

Y B

OX

HE

AD

ER

)2.

1mm

PO

WE

RS

OC

KE

T

LEDs

LED

IRQ

0S

WIT

CH

FIQ

SW

ITC

HT

IOB

1S

WIT

CH

RE

SE

TS

WIT

CH

4mm

MO

UN

TIN

GH

OLE

S

SRAM

74LV

C13

9D

GR

OU

ND

SIG

NA

L FR

OM

DB

9 P

LUG

WIL

LB

E P

LAC

ED

OV

ER

CH

AS

SIS

PLA

NE

AN

DW

ILL

CO

NN

EC

T T

O G

RO

UN

D N

EA

RS

TA

RP

OIN

T

124.

3mm

112m

m

SRAM

SRAM

SRAM

0.1"

PIT

CH

LEA

VE

SP

AC

E A

RO

UN

D 2

x32

HE

AD

ER

TO

FIT

A D

IN41

612

SK

T (R

OW

S A

,B)

CO

NN

EC

TO

R IN

ITS

PLA

CE

IF N

EC

ES

SA

RY

RE

SE

T

IRQ0

FIQ

TIOB1

LED

1

LED

2

LED

3

POWER

MAST

/8

/4

/2

EBI

UP

PE

RM

EM

LOW

ER

ME

M

SE

RIA

L B

SE

RIA

L A

JTA

G

POWER

WR

ITIN

G IN

TH

IS F

ON

T S

HO

ULD

BE

PR

INT

ED

ON

TO

PC

B

EB

I

I/O EXP.

LK2

SW

1

U6

J2

J5

J4

R4

J6

74LV

C00

J72x

1 P

IN H

EA

DE

R

U1

U2

U4

U5

LK1

J3

J1

LK5

- 9

LK4

R21 - 26

LK3

AR

M E

OI-

0042

(D

RA

WIN

G.S

CH

)B

PC

B la

yout

(c)

AR

M L

td.

90 F

ulb

ourn

Road

Cherr

y H

into

nC

am

bridge

CB

1 4

JN

A2

28

Thurs

day, A

ugu

st 20, 1998

Titl

e

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

Schematics


Figure 5. External Bus Interface

1 1

2 2

3 3

4 4

5 5

6 6

7 7

8 8

AA

BB

CC

DD

16-B

IT w

ide

Fla

sh

Bus

Exp

ansi

on C

onne

ctor

Fit o

nly

if B

ank

1is

not

pop

ulat

ed

Ban

k 0

SR

AM

Ban

k 1

SR

AM

Fit o

nly

if ba

nk 1

is p

opul

ated

0R r

esis

tor

fact

ory

fitte

d in

pos

ition

A

-C fo

r A

T91

EB

01 b

oard

.F

or A

T91

EB

02 0

R r

esis

tor

fact

ory

fitte

d in

pos

ition

B-C

Con

nect

or n

ot fi

tted

on A

T91

EB

01.

AT

91E

B02

has

a s

trai

ght p

in h

eade

r co

nnec

tor

fitte

d

Leav

e sp

ace

on P

CB

to p

rint

Low

er m

em a

nd U

pper

mem

whi

chw

ill b

e in

dica

ted

by th

e po

sitio

n of

the

switc

h.

Whe

n fit

ting

128K

x8 S

RA

M p

arts

alig

npi

n 1

of t

he S

RA

M to

whe

re p

in 2

wou

ldbe

if a

512

K p

art w

ere

fitte

d.If

an

exte

rnal

inte

rrup

t sou

rce

is a

ttach

ed to

the

Bus

Exp

ansi

on C

onne

ctor

it m

ust b

e op

en-d

rain

or o

pen-

colle

ctor

.

Prin

t on

PC

B E

BI

Prin

t on

PC

B th

e po

sitio

nof

0R

res

isto

r i.e

. A-C

and

B-C

Do

Not

Fit

AR

M E

OI-

00

42

(E

BI.

SC

H)

B

Exte

rna

l B

us I

nte

rface

(c)

AR

M L

td.

90 F

ulb

ourn

Road

Ch

err

y H

into

nC

am

bridge

CB

1 4

JN

B

38

Th

urs

day, A

ugust 20, 1998

Titl

e

Siz

eD

ocu

me

nt

Nu

mb

er

Re

v

Da

te:

Sh

ee

to

f

GN

DG

ND

NW

R0

/NW

RN

WR

1/N

UB

NR

D/N

OE

NW

AIT

P2

5/M

CK

OE

BI_

MC

KI

NC

S0

NC

S1

NC

S2

NC

S3

VD

DN

RS

TA

0A

1A

2A

3A

4A

5A

6A

7G

ND

GN

DA

8A

9A

10

A1

1A

12

A1

3A

14

A1

5V

DD

VD

DA

16

A1

7A

18

A1

9A

20

A2

1A

22

A2

3G

ND

GN

DD

0D

1D

2D

3D

4D

5D

6D

7V

DD

VD

DD

8D

9D

10

D11

D12

D13

D14

D15

GN

DG

ND

A[2

3..0]

D[1

5..0]

A1A2A3A4

A6

A7

A8

A9

A10

A11

A12

A13

A14

A15

D15D14

D1

1D

10

D8

D7

D6

D5

D4

NCS0

NC

S[3

..0

]

NW

R1

/NU

B

NW

R0

/NW

R

NR

D/N

OE

P2

5/M

CK

O

NW

AIT

EB

I_M

CK

I

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

A15

A16

A17

D0

D1

D2

D3

D4

D5

D6

D7

NR

D/N

OE

CS

_B

AN

K1

NW

R0

/NW

R

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

A15

A16

A17

D8

D9

D1

0D

11

D1

2D

13

D1

4D

15

NR

D/N

OE

CS

_B

AN

K0

NW

R1

/NU

B

D1

0

A14

A13

A12

D1

1

A11

A10

A9

NR

D/N

OE

A8

NW

R1

/NU

B

A7

CS

_B

AN

K1

D1

5

A15

D1

4

A16

A6

A17

A5

D1

3

D8

A4

D9

A3

A2

D1

2

A1

A1

8/A

20

GN

D

CS

_B

AN

K1

VD

D

GN

D

NC

S1

CS

_B

AN

K0

NW

R0

/NW

RA

12

D5

A13

A1

A14

CS

_B

AN

K0

A15

A8

A16

NR

D/N

OE

A2

A3

D1

A9

D4

A17

A4

A5

D7

D0

A10

D3

A6

A7

A11

D6

D2

VDD

GND

NR

ST

A18

A19

A18

A18

A1

8

A19

A19

A1

9

A1

8/A

20

A18

A20

SW_A16

FLASH_WE

SW

_A

16

D1

2

D9

D13

A5

NRD/NOED0D1D2D3

GN

DA

16N

WR

0/N

WR

FL

AS

H_

WE

A16

VD

D

VD

DV

DD

VD

D

VD

D

VD

D

VD

D

VD

D

VD

D

VD

D

VD

D

R1

10

K

U6 74LV

C139D

1 2 3 4 5 6 7 8

12

11

10

914

13

15

16

E 1A

01

A1

1Y

01

Y1

1Y

21

Y3

GN

D

2Y

02

Y1

2Y

22

Y3

2A

02

A1

2E

VD

D

R4

0R

LK

1

SM

LIN

K

1 2 3

A C B

U1

51

2K

x8 S

RA

M

2 3 4 5 6 7 8 91

01

11

21

31

41

51

61

7

24

23

22

21

20

26

25

27

28

30

29

31

35

34

33

32

36

19

1

18

A0

A1

A2

A3

CS

I/O

0I/

O1

VD

DG

ND

1/O

21

/O3

WE

A4

A5

A6

A7

A1

2A

11

A1

0A

09

A0

8

I/O

5I/

O4

VD

DG

ND

1/O

71

/O6

OE

A1

6A

15

A1

4A

13

NC

NC

A1

7

A1

8

U2

51

2K

x8 S

RA

M

2 3 4 5 6 7 8 91

01

11

21

31

41

51

61

7

24

23

22

21

20

26

25

27

28

30

29

31

35

34

33

32

36

19

1

18

A0

A1

A2

A3

CS

I/O

0I/

O1

VD

DG

ND

1/O

21

/O3

WE

A4

A5

A6

A7

A1

2A

11

A1

0A

09

A0

8

I/O

5I/

O4

VD

DG

ND

1/O

71

/O6

OE

A1

6A

15

A1

4A

13

NC

NC

A1

7

A1

8

U5

51

2K

x8 S

RA

M

2 3 4 5 6 7 8 91

01

11

21

31

41

51

61

7

24

23

22

21

20

26

25

27

28

30

29

31

35

34

33

32

36

19

1

18

A0

A1

A2

A3

CS

I/O

0I/

O1

VD

DG

ND

1/O

21

/O3

WE

A4

A5

A6

A7

A1

2A

11

A1

0A

09

A0

8

I/O

5I/

O4

VD

DG

ND

1/O

71

/O6

OE

A1

6A

15

A1

4A

13

NC

NC

A1

7

A1

8

U4

51

2K

x8 S

RA

M

2 3 4 5 6 7 8 91

01

11

21

31

41

51

61

7

24

23

22

21

20

26

25

27

28

30

29

31

35

34

33

32

36

19

1

18

A0

A1

A2

A3

CS

I/O

0I/

O1

VD

DG

ND

1/O

21

/O3

WE

A4

A5

A6

A7

A1

2A

11

A1

0A

09

A0

8

I/O

5I/

O4

VD

DG

ND

1/O

71

/O6

OE

A1

6A

15

A1

4A

13

NC

NC

A1

7

A1

8

J1

CO

N6

4A

B

1 3 5 7 91

11

31

51

71

92

12

32

52

72

93

13

33

53

73

94

14

34

54

74

95

15

35

55

75

96

16

3

2 4 6 8 10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

42

44

46

48

50

52

54

56

58

60

62

64

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

C2

100n

C4

100n

C6

100n

C1

100n

C3

100n

C5

100n

TP

3

Te

st

Po

int

1TPT

P2

Te

st

Po

int

1 TP

TP

1

Te

st

Po

int

1 TP

U3

AT

29

LV

1024-1

5JC

123456

7 8 91

01

11

21

31

41

51

61

7

1819202122232425262728

29

30

31

32

33

34

35

36

37

38

39

4041424344

NCNCCE

I/015I/O14I/O13

I/O

12

I/O

11

I/O

10

I/O

9I/

O8

GN

DN

CI/

O7

I/O

6I/

O5

1/O

4

1/O31/O21/O11/O0OEDCA0A1A2A3A4

A5

A6

A7

A8

NC

GN

DA

9A

10

A1

1A

12

A1

3

A14A15NCWE

VDD

SW

1

213

U14

74LV

C00

1 2 4 591

0

12

13

3 681

1

14

7

1A

1B

2A

2B

3A

3B

4A

4B

1Y

2Y

3Y

4Y

VD

D

GN

D

R2

10K

TP

17

Te

st

Po

int

1 TP

R3

10K

C55

100n

TP

19

Te

st

Po

int

1 TP

TP

18

Te

st

Po

int

1 TP

J7

CO

N2

AP

12 ++

TP

16

Te

st

Po

int

1 TP

A[2

3..0]

D[1

5..0]

NW

R1

/NU

B

NW

R0

/NW

R

NC

S[3

..0]

NR

D/N

OE

P2

5/M

CK

O

EB

I_M

CK

I

NW

AIT

NR

ST

Schematics


Figure 6. JTAG Interface, Reset, Interrupts and LEDs

1 1

2 2

3 3

4 4

5 5

6 6

7 7

8 8

AA

BB

CC

DD

JT

AG

Inte

rfac

e

FIQ

In

terr

upt

But

ton

LED

1

LED

2

LED

3

To

rese

t the

TA

P c

ontr

olle

r ho

ld T

MS

hig

h fo

r5

TC

K c

ycle

s.

Sys

tem

Res

et

Use

rD

efin

edB

utto

n

IRQ

Inte

rrup

tB

utto

n

Dec

oupl

ing

capa

cito

r fo

r 74

LV14

20 w

ay b

oxhe

ader

Res

et T

hres

hold

= 3

.08V

Res

et h

eld

low

for

140m

s m

in.

Prin

t on

PC

B th

e fu

nctio

n of

eac

h pu

shbu

tton

i.e. F

IQ, T

IOB

1, IR

Q0,

RE

SE

T

The

cha

ssis

pla

ne w

ill b

e jo

ined

toth

e si

gnal

gro

und

plan

e at

one

poi

nton

ly. S

ee D

raw

ing.

sch

for

sugg

este

dpo

sitio

n of

the

wire

link

.

Pla

ce c

apac

itors

as

clos

e as

pos

sibl

eto

the

conn

ecto

r.

AT

91E

B01

will

hav

e in

divi

dual

LE

Ds

for D

1A, D

1B a

nd D

1C.

AT

91E

B02

has

the

LED

s in

asi

ngle

pac

kage

hen

ce th

e re

fere

nce

nam

es.

Prin

t on

PC

B th

e na

me

of e

ach

LED

i.e. L

ED

1, L

ED

2, L

ED

3

RE

D

AM

BE

R

GR

EE

N

Prin

t on

PC

BJT

AG

Fac

tory

fitte

d

AR

M E

OI-

0042 (

JTA

G.S

CH

)B

JTA

G in

terf

ace

, R

ese

t, Inte

rrupts

&

LE

Ds

(c)

AR

M L

td.

90 F

ulb

ourn

Road

Cherr

y H

into

nC

am

bridge

CB

1 4

JN

B

48

Thurs

day, A

ugust 20, 1998

Titl

e

Siz

eD

ocu

ment N

um

ber

Rev

Date

:S

heet

of

IRQ_ONB0

TIO

A0

TIO

A1

TIO

B0

TIO

A0

TIO

A1

TIO

B0

NR

ST

VDD

GND

TD

ITM

ST

CK

TD

ON

RS

T

VD

DV

DD

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

VD

D

VD

D

VD

D

VD

D

VD

DV

DD

VD

D

VD

D

VD

D

R5

10K

R12

10K

R9

470R

U7A

74LV

14D

12

+C

26

470n

TA

NT

SW

3S

WIT

CH

HO

RIZ

R6

10K

R8

10K

U7B

74LV

14D

34

U7C

74LV

14D

56

U7D

74LV

14D

98

U7E

74LV

14D

11

10

U7F

74LV

14D

13

12

R10

470R

R11

470R

R13

10K

R14

10K

+C

27

470n

TA

NT

+C

25

470n

TA

NT

U8

MA

X6315

US

31D

3-T

12

34

GN

DR

ES

ET

MR

VD

D

SW

4S

WIT

CH

HO

RIZ

SW

5S

WIT

CH

HO

RIZ

SW

2S

WIT

CH

HO

RIZ

R7

10K

J2

CO

N20A

P

1 3 5 7 911

13

15

17

19

2 4 6 8 10

12

14

16

18

20

+ + + + + + + + + +

+ + + + + + + + + +

C7

10pF

C10

10nF

C18

22pF

C8

10pF

C9

10pF

C16

10pF

C17

10pF

C11

10nF

C12

10nF

C13

10nF

C19

10nF

C20

10nF

C21

10nF

C14

10nF

C15

10nF

C22

10nF

C23

10nF

C24

100n

WL

1

WIR

E L

INK

R21

0R

R22

10K

R23

0R

R24

10K

R25

0R

R26

10K

D1A

TR

I-LE

D

21

D1B

TR

I-LE

D

43

D1C

TR

I-LE

D

65

TC

KT

MS

NR

ST

P12/F

IQ_O

NB

IRQ

0_O

NB

TD

O

TIO

B1_O

NB

TIO

A0

TIO

A1

TIO

B0

TD

I

Schematics


Figure 7. I/O Expansion

1 1

2 2

3 3

4 4

5 5

6 6

7 7

8 8

AA

BB

CC

DD

I/O E

xpan

sion

0R R

esis

tor

fact

ory

fitte

d in

pos

ition

B-C

for

all

of th

ese

surf

ace

mou

nt li

nks

Con

nect

or n

ot fi

tted

on A

T91

EB

01.

AT

91E

B02

has

a s

trai

ght p

in h

eade

r co

nnec

tor

fitte

d

Prin

t on

PC

B

I/O E

XP

.

Prin

t on

PC

B th

e po

sitio

nof

0R

res

isto

r i.e

. A-C

and

B-C

AR

M E

OI-

00

42

(IO

EX

P.S

CH

)B

I/O

EX

PA

NS

ION

(c)

AR

M L

td.

90 F

ulb

ourn

Road

Cherr

y H

into

nC

am

bridge

CB

1 4

JN

B

58

Tuesday,

July

14, 1998

Titl

e

Siz

eD

ocu

me

nt

Nu

mb

er

Re

v

Da

te:

Sh

ee

to

f

P1

2/F

IQ

TX

D[1

..0]

RX

D[1

..0]

TC

LK

[2..0]

IRQ

[2..0]

SC

K[1

..0

]

VD

D

RX

D0

SC

K0

TIO

A0

TIO

A1

TIO

A2

P18

P19

TIO

B2

TIO

B0

VD

D

P12/F

IQ_E

XP

P16

TC

LK2

TX

D0

P17

TX

D0_

EX

P

TX

D_O

NB

0

TX

D0_

EX

PTX

D1_

EX

P

TIO

B1_

EX

P

IRQ

2

TX

D1

TX

D1_

EX

P

TX

D_O

NB

1T

IOB

1_

ON

B

IRQ

0IR

Q0_

EX

P

IRQ

0_

ON

B

RX

D1

SC

K1

P1

2/F

IQ_

ON

BP

12

/FIQ

P12/F

IQ_E

XP

P1

2/F

IQ_

ON

B

TIO

B1

_O

NB

TX

D_

ON

B[1

..0

]

TC

LK0

TC

LK1

GN

DG

ND

P23

GN

DG

ND

NW

DO

VF

IRQ

1

VD

DIR

Q0_

EX

P

NW

DO

VF

TIO

A[2

..0

]

P[1

9..

16

]

P23

TIO

B[2

..0

]

P2

4/B

MS

VD

D

P2

4/B

MS

VDD

GND

TIO

B1

TIO

B1_

EX

P

VD

D

LK

5

SM

LIN

K

123

ACB LK

8

SM

LIN

K

123

ACB

LK

9

SM

LIN

K

123

ACB

LK

6

SM

LIN

K

123

ACB

LK

7

SM

LIN

K

123

ACB

J3 C

ON

34A

P

1 3 5 7 911

13

15

17

19

21

23

25

27

29

31

33

2 4 6 8 10

12

14

16

18

20

22

24

26

28

30

32

34

+ + + + + + + + + + + + + + + + +

+ + + + + + + + + + + + + + + + +

TP

4

Test P

oin

t

1TP

TP

5

Test P

oin

t

1TP

TP

7

Test P

oin

t

1TP

TP

6

Test P

oin

t

1TP

TP

8

Test P

oin

t

1TP

SC

K[1

..0]

TIO

A[2

..0]

TX

D[1

..0]

RX

D[1

..0]

TC

LK

[2..0]

IRQ

[2..0]

P1

2/F

IQ

TX

D_O

NB

[1..0]

IRQ

0_O

NB

P12/F

IQ_O

NB

TIO

B1_O

NB

NW

DO

VF

P[1

9..16]

P23

TIO

B[2

..0]

P24/B

MS

Schematics


Figure 8. Power, Crystal Oscillator and Clock Distribution

1 1

2 2

3 3

4 4

5 5

6 6

7 7

8 8

AA

BB

CC

DD

Inse

rt ju

mpe

r in

one

posi

tion

only

Vol

tage

inpu

t ran

ge :

7.5

to 9

V, 0

.5A

Not

e : P

ower

sup

ply

is in

put

prot

ecte

d to

30V

how

ever

re

gul

ator

will

trip

out

if it

gets

to h

ot.

Bin

ary

4-bi

tco

unte

r

Vol

tage

Reg

ulat

or O

utpu

tV

out =

1.2

5(1

+ (

Rb/

Ra)

)

Ra

Rb

Dis

tibut

e te

st p

ins

over

boa

rd

PO

WE

RLE

D

Link

fiel

d al

low

s se

lect

ion

ofon

boa

rd c

lock

or

divi

de b

y2,

4 a

nd 8

, or

exte

rnal

cloc

k so

urce

con

nect

ed

via

EB

I

Not

e : G

roun

d w

ill b

e ap

prox

. 0.7

Vh

igh

er t

han

th

e p

ow

er s

up

ply

gro

und

Pla

ce a

s ne

ar a

spo

ssib

le to

AT9

1

Sys

tem

Pow

er S

uppl

y -

VD

D (

3V3)

Pla

ce a

s ne

ar a

spo

ssib

le to

AT9

1

Pla

ce a

s ne

ar a

spo

ssib

le to

AT9

1

Pla

ce a

s ne

ar a

spo

ssib

le to

AT9

1

Mak

e as

sho

rtas

pos

sibl

e

Prin

t on

PC

B w

here

to p

ositi

on ju

mpe

rfo

r th

e va

rious

clo

ckfr

eque

ncie

s i.e

.MA

ST

, /8,

/4, /

2, E

BI

Pla

ce c

apac

itors

as

clos

e as

pos

sibl

eto

the

conn

ecto

r.

Prin

t on

PC

B P

ower

AR

M E

OI-

00

42

(O

SC

PO

WE

R.S

CH

)B

Po

we

r, C

ryst

al o

scill

ato

r a

nd

clo

ck d

istr

ibu

tion

(c)

AR

M L

TD

.

90 F

ulb

ourn

Road

Cherr

y H

into

nC

am

bridge

CB

1 4

JN

B

68

Tuesday,

July

14, 1998

Titl

e

Siz

eD

ocu

me

nt

Nu

mb

er

Re

v

Da

te:

Sh

ee

to

f

AT

91C

LK

/2 /4 /8

VD

D

GN

D

VIN

EB

I_M

CK

I

VD

DG

ND VD

D

VD

D

VD

D

VDD

GND

VD

D

VD

D

VD

D

VD

D

VD

D

VD

D

J4

2.1

mm

Po

we

r S

ock

et

321

R19

10K

+C

29

10

uF

(35

V)

+C

30

10u

R15

470R

U11

GX

O-U

10

832

.768

MH

z3V

3

1 234

EN

GN

DO

UT

VD

D

GN

D1

TE

ST

PIN

1

GN

D2

TE

ST

PIN

1

GN

D3

TE

ST

PIN

1

R18

33R

U9

LT

1086C

M3 2 1

INO

UT

AD

J

R17

360R

1206

R16

220R

1206

GN

D4

TE

ST

PIN

1

LK

2

CO

N10A

P

1 3 5 7 9

2 4 6 8 10

+ + + + +

+ + + + +

C28

22nF

(T)

2

1

3

C31

22nF

(T)

2

1

3

C32

100n

C33

100n

D3

ES

1B

21

D4

ES

1B

21

D2

ES

1B

2 1

D5

ES

1B

2 1U

10

74LV

161

3 4 5 6 710

2

9

1

14

13

12

11

15

16

8

D0

D1

D2

D3

CE

PC

ET

CLK

PE

MR

Q0

Q1

Q2

Q3

TC

VD

D

GN

D

TP

12

Test P

oin

t

1 TP

TP

9

Test P

oin

t

1 TP

TP

10

Test P

oin

t

1 TP

TP

11

Test P

oin

t

1T

P

TP

13 Test P

oin

t

1TP

TP

14

Test P

oin

t

1T

P

D6

LE

D-R

ED

2 1

AT

91C

LK

EB

I_M

CK

I

Schematics


Figure 9. AT91M40400 in TQFP Package

1 1

2 2

3 3

4 4

5 5

6 6

7 7

8 8

AA

BB

CC

DD

JTA

G s

igna

ls

Clo

ck, R

eset

& In

teru

pts

Tim

er &

UA

RT

- Can

be

I/O a

s w

ell

Pla

ce o

ne o

f the

se c

apac

itors

on

each

sid

e of

the

AT

91.

Not

e : I

nter

rupt

line

s ca

n be

use

d as

I/O

Fac

tory

fitte

d

4K7

resi

stor

fact

ory

fitte

din

pos

ition

C-B

. Thi

s se

lect

sal

tern

ate

boot

mod

e w

hich

mak

es th

e A

T91

boo

t fro

mex

tern

al 1

6-bi

t wid

e F

lash

.

Prin

t on

PC

B th

e po

sitio

nof

4K

7 re

sist

or i.

e. A

-C a

nd B

-C

AR

M E

OI-

0042 (

AT

91P

RO

C.S

CH

)B

AT

91M

40400 in

TQ

FP

pac

kage

(c)

AR

M L

td.

90 F

ulb

ourn

Road

Ch

err

y H

into

nC

am

bridge

CB

1 4

JN

B

78

Th

urs

day, A

ugust 20, 1998

Titl

e

Siz

eD

ocu

ment N

um

ber

Rev

Date

:S

heet

of

TC

K

TD

O

TD

I

TM

S

P2

5/M

CK

O

NR

ST

P1

2/F

IQ

TC

LK

[2..0]

TIO

A[2

..0

]

TIO

B[2

..0

]

SC

K[1

..0]

TX

D[1

..0]

IRQ

[2..0]

A4

A18

A3

A7

A14

TDO

A13

SC

K1

A1

A8

A16

TX

D0

RX

D0

TX

D1

AT91CLK

A21

A5

A20

IRQ

0

SC

K0

IRQ

1

NCS0NCS1NCS2

A2

A9

A11

A12

A17

TIO

A2

TIO

B2

RXD1

A23

TIO

A1

TIO

B1

TC

LK2

P12/F

IQ

A15

A19 A22A0

A10

IRQ

2

NRST

NCS3

A6

TC

LK1

A[23..0]

TIO

B0

TCK

P[1

9..16]

NC

S[3

..0]

P19

P18

P17

P16

P25/MCKO

NWR1/NUB

NW

R1/N

UB

NWDOVF

TDITMS

P23P24/BMS

P23

NRD/NOENWR0/NWR

NR

D/N

OE

NW

R0/N

WR

NW

AIT

NWAIT

RX

D[1

..0]

NW

DO

VF

AT

91C

LK

P2

4/B

MS

TIOA0

D3

D7D6D5

D14

D2

D8D9

D11

D12

TCLK0

D0

D10

D13

D15

D4

D1

P2

4/B

MS

VD

D_

PR

OC

VD

D VD

D_

PR

OC

VD

D

VD

D

+C

38

10u

WL

2

WIR

E L

INK

LK

3

SM

LIN

K(4

K7

)

1 2 3

A C B

U12

AT

91M

404

00

1 2 3 4 5 6 7 8 91

01

11

21

31

41

51

61

71

81

92

02

12

22

32

42

5

262728

3132333435363738394041424344454647484950

51

54

53

52

55

56

57

58

59

60

62

61

63

64

65

66

67

68

69

73

72

71

70

74

75

76777879808182838485

8786

888990919293

9594

96979899100

2930

A0

/NL

BG

ND

A1

A2

A3

A4

A5

A6

A7

VD

D_

PR

OC

A8

A9

A1

0A

11

A1

2A

13

A1

4G

ND

GN

DA

15

A1

6A

17

A1

8A

19

P2

8/A

20

/CS

7

P29/A21/CS6VDD_PROCVDD_PROC

D0D1D2D3D4GNDD5D6D7D8D9D10D11VDD_PROCD12D13D14D15P0/TCLK0P1/TIOA0

P2

/TIO

B0

P3

/TC

LK

1G

ND

GN

D

P4

/TIO

A1

P5

/TIO

B1

P6

/TC

LK

2P

7/T

IOA

2P

8/T

IOB

2P

9/I

RQ

0

VD

D_

PR

OC

VD

D_

PR

OC

P1

0/I

RQ

1P

11

/IR

Q2

GN

DP

12

/FIQ

P1

3/S

CK

0P

14

/TX

D0

P1

5/R

XD

0

P1

9P

18

P1

7P

16

P2

0/S

CK

1P

21

/TX

D1

/NT

R1

P22/RXD1NWR1/NUB

GNDNRST

WDOVFVDD_PROC

MCKIP23

P24/BMSP25/MCKO

GNDGND

TMSTDI

TDOTCK

NRD/NOENWR0/NWR

VDD_PROCVDD_PROC

NWAITNCS0NCS1

P26/NCS2P27/NCS3

P30/A22/CS5P31/A23/CS4

R20

10

K

C37

100n

C36

100n

C35

100n

C34

100n

D[1

5..0]

TD

O

TD

I

TM

S

A[2

3..0]

P2

5/M

CK

O

TC

K

NR

ST

NC

S[3

..0]

NW

R1

/NU

B

NR

D/N

OE

NW

R0

/NW

R

P1

2/F

IQ

IRQ

[2..0]

TC

LK

[2..0]

TIO

A[2

..0]

TIO

B[2

..0]

SC

K[1

..0]

RX

D[1

..0]

P[1

9..16]

P2

3

NW

DO

VF

AT

91

CL

K

TX

D[1

..0]

NW

AIT

P2

4/B

MS

Schematics


Figure 10. Serial Interface

1 1

2 2

3 3

4 4

5 5

6 6

7 7

8 8

AA

BB

CC

DD

Ser

ial I

/O fr

omA

T91

10K

Res

isto

r fa

ctor

y fit

ted

in p

ositi

on C

-B.

DC

DD

SR

RT

S

CT

SD

TR

Se

rial P

ort A

is u

sed

for

conn

ectio

nto

the

host

PC

usi

ng a

sta

ndar

d, s

traig

htth

roug

h ca

ble

- 9

way

D ty

pe p

lug

to 9

w

ay D

type

soc

ket.

Prin

t on

PC

B th

e po

sitio

nof

10K

res

isto

r i.e

. A-C

and

B-C

Pla

ce c

apac

itors

as

clos

e as

pos

sibl

eto

the

conn

ecto

r.

Pla

ce c

apac

itors

as

clos

e as

pos

sibl

eto

the

conn

ecto

r.

Prin

t on

PC

B S

eria

l B

Prin

t on

PC

B S

eria

l A

The

She

ll of

bot

h D

type

con

nect

ors

shou

ld b

e co

nnec

ted

to th

e ch

assi

s pl

ane

AR

M E

OI-

00

42

(R

S2

32

.SC

H)

B

Se

ria

l In

terf

ace

(c)

AR

M L

TD

.

90

FU

LB

OU

RN

RO

AD

CH

ER

RY

HIN

TO

NC

AM

BR

IDG

EC

B1

4JN

B

88

Tu

esd

ay,

July

14, 1998

Titl

e

Siz

eD

ocu

me

nt

Nu

mb

er

Re

v

Da

te:

Sh

ee

to

f

VD

DV

DD

VA

PG

ND

C1

AN

TX

D_

SA

C2

AP

RX

D_

SA

C2A

NR

XD

0

RX

D_

SA

VA

NV

DD

TX

D_

SB

TX

D_

ON

B0

TX

D_

SA

RX

D_

SB

TX

D_

ON

B1

RX

D1

GN

D

VD

DC

2A

PV

AP

VA

N

C1

AN

C2

AN

RX

D[1

..0]

C1

AP

C1

AP

TX

D_

ON

B[1

..0

]

RX

D_

SB

GN

DG

ND

TX

D_S

B

GN

D

VDD

GND

GN

D

VD

D

VD

D

+C

47

0.1

uT

AN

T

J5 D

B9

SO

CK

ET

594837261

U13

MA

X3

22

3C

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Documents

Section 1 Overview - Shrubberyheas/willem/PDF/ATMEL Flash...Angel Debug Monitor (with or without EmbeddedICE or Multi-ICE) 2.1.1 The ARMulator The ARMulator is a software emulator