SDX-MSC II MTM

Ed.00

PurposeThis manual describes the methods for checking the status of function blocks that configure the SDX-MSC II and methods for processing its faults.Document Content and Organization This manual is organized and separated into the following blocks : CIN Fault Handling

MP(MPH, OMPH) Fault Handling

PPH Fault Handling

NES Fault Handling

SSL Fault Handling

TSL Fault Handling

DSC Fault Handling

SS7 Fault Handling

DTI Fault Handling

PRI Fault Handling

APC Fault Handling

ConventionsThe following special paragraphs are used in this document to point out information that must be read. This information may be set-off from the surrounding text, but is always preceded by a bold title in capital letters. The three categories of these special paragraphs are :

WARNING

Indicate a potentially hazardous situation which if not avoided, could result in death or serious injury.

CAUTION

Indicate a potentially hazardous situation which if not avoided, may result in minor or moderate injury. It may also be used to alert against unsafe practices.

NOTE

Indicates additional information as a referenceConsole Screen Output

The lined box with Courier New font will be used to distinguish between the main content and console output screen text.

Bold Courier New font will indicate the value entered by the operator on the console screen

ReferenceSDX-MSC II System DescriptionThe SDX-MSC II System Description provides basic introductions for the SDX-MSC II and information needed to understand the SDX-MSC II such as hardware, software and functions, etc.

SDX-MSC II Command Description

The SDX-MSC II Command Description provides the uses and parameters of the MMC commands that are used in the SDX-MSC II system when in service.

SDX-MSC II Printout Description

The SDX-MSC II Printout Description provides the meanings and parameters of all kinds of system messages that are generated from the SDX-MSC II system when in service.

SDX-MSC II O&M Support InformationThe SDX-MSC II OSI provides all kinds of hardware information needed for the operations and maintenance of the SDX-MSC II.

Revision HistoryEDITIONDATE OF ISSUEREMARKS

0010.2002First Draft

For product safety and correct operation, the following information must be given to the operator/user and shall be read before the installation and operation.

Symbols

Caution

Indication of a general caution

Restriction

Indication for prohibiting an action for a product

Instruction

Indication for commanding a specifically required action

Caution

Inhibition of Metallic Accessories

No metallic accessories must be worn such as a watch, ring and so on when handling the system. This is to prevent any potential static electricity from being transferred to the system from the metallic materials.

Prevention of Static Electricity

Upon handling the system or boards, any static electricity must be prevented from reaching the system or boards. Otherwise, they may be damaged by the static electricity surge.

INTRODUCTIONIPurpose

IDocument Content and Organization

IIConventions

IIConsole Screen Output

IIIReference

IIIRevision History

SAFETY CONCERNSVSymbols

CautionVFault Handling for Each Block11CIN Fault Handling

11.1Introduction

11.2CIN Functions

31.3Fault Diagnosis

82MP Fault Handling

82.1MPH Fault Handling

112.2OMPH Fault Handling

163PPH Fault Handling

163.1Introduction

163.2PPH Functions

173.3Fault Diagnosis

204NES Fault Handling

204.1Introduction

204.2NES Functions


255SSL Fault Handling

255.1Introduction

255.2SSL Functions


306TSL Fault Handling

306.1Introduction

306.2TSL Functions


377DSC Fault Handling

377.1DSMSA Introduction

427.2DSDTA Introduction

467.3DSCMA Introduction

497.4DSVMB Introduction

558S7H Fault Handling

558.1S7H Introduction

558.2Online Test Entries and Implementations

579DTI Fault Handling

579.1Introduction


6110PRI Fault Handling

6110.1Introduction

6110.2PRI Functions


6711APC Fault Handling

6711.1Introduction

6711.2APC Functions


ABBREVIATION

1A ~ CAbbreviation-

2D ~ L

Abbreviation-

3M ~ RAbbreviation-

4S ~ VAbbreviation-

1CIN Fault Handling

1.1IntroductionThe CIN block connects subsystems(CCS and ASS) with the IPC network. The CIN block reads only the address field from the data frame and thereby performs the hardware self-routing without software control for the IPC data communicated between the subsystems, and feeds the path for high-speed data transmission.

The faults that can be generated from the CIN block are F5120 IPC NODE FAULT, Node duplication fault and no communication of a specific IPC node, etc.1.2CIN Functions

The CIN block is composed of the Communication Inter-working Processor(CIP) and the Communication Inter-working(CI). The CIP includes the CINMA PBA and the CI includes the CINIA PBA.

The CIP performs a function of the IPC network management and CI block management, and the CI provides the UPC data path between the subsystems.

Communication Inter-working Node Maintenance Assembly(CINMA)

The CINMA performs the CI network management and is responsible for the O&M function of the CINIA that is used for the CI network interface. The CINMA performs the following functions :

To control the duplication mode of the Active/Standby through serial channel.

To make the M-bus communication for each node state for monitoring and maintenance.

To provide the IPC channel(U-link) for inter-processor communication.

To feed a synchronous signal to the D-bus, the common bus of the nodes.

To make the TD-bus interface for the independent maintenance channel.Communication Inter-working Node Interface Assembly(CINIA)

The CINIA performs functions of self-routing, queuing and flow control for asynchronous data between the processors. The CINIA is composed of the following function blocks :

1) Fault Center & Node Controller Block

The Fault Center & Node Controller Block is composed of a CPU (MC68302FC25C) and highly integrated EPLD(EPF10K40ARC240-3), and manages the CINIA.2) Node[0..3] Block

The Node[0..3] Block is responsible for the IPC data buffer and has independent both-way(BU and UB) channels.3) Arbiter Block

The Arbiter Block receives FRS and ASTCLK from the active CINMA through the D-bus, and makes it possible for Node[0..3] to transmit data to the D-bus.

4) Frame Address Checker Block

The Frame Address Checker Block controls the inter-processor communication path.5) D-bus Monitor & Select Block

The D-bus Monitor & Select Block supervises the D-bus status. If the D-bus generates a fault, the block informs the fault center of the fault.

6) U-link Block

The IPC communication path between the CINIA and subsystem, which is the U-link block is designed along with the IEEE RS-422 and full-duplication mode.7) M-bus Block

The communication path between CINMA and CINIA, the M-bus Block is designed along with the IEEE RS-485 and half-duplication mode.8) D-bus Interface Block

The D-bus Interface Block makes it possible to do high-speed 16-bit data transmission and consists of upper and lower sides of the shelf.1.3Fault DiagnosisDiagnosis Procedure

1.3.1Diagnosis of Node faults

If a fault is generated from a node, the following message is displayed on the screen.

F5120 IPC NODE FAULT

LOC : CIN/CINIA/SLOTxx/NODExx

INF : TYPE=CINIA_FLT CONTENT=xxxxxxxxxxxxxxxxx

The reason for an F5120 message is as follows :

Power off CINIA demounted CINIA function failed Pertinent subsystem(CCS, ASS) fault U-Link cable disconnectedNode Fault Handling procedure1) Check the power status. Turn on the power if the reason is a power-off.

2) Check if the CINIA has been correctly mounted. Remount the CINIA if it has been demounted.

3) Check the RUN LED status of the CINIA. Replace the board if the RUN LED does not indicate a normal state(green).

4) Check the status of the subsystem connected to the pertinent node. Recover the subsystem from the abnormal state if it is not normal.

5) Check the U-link connected to the pertinent node. Connect the U-link cable correctly if its connection is not correct.

Related commands

Use the following commands to check the CIN state :

DIS-NODESTS

RESET-NODE

TEST-NODE

1.3.2Diagnosis of the Node StatusThe change of the node status will result in the following message being generated :

S5120 IPC NODE STATUS CHANGE

LOC : CIN/CINIA/SLOTxx/NODExx

INF : NODE DIE(NODE ALIVE / SWITCH-OVER)

The S5120 message results from the following cases :

Change of the node status from an active to standby. Node blocked along with Node not used mode. CINIA function failed instantaneously or CINIA restarted. M-bus fault between CINMA and CINIA or a fault between the duplication CINIAs. Node change of the active/standby state by means of the MMC.Node status diagnosis procedure1) Check the ACT LED status of the node on the CINIA. Reset the CINIA if the ACT LED does not light up green. If the CINIA does not recover even after resetting, replace the CINIA.

2) Check if the node is in Node not used mode(J1 ~ J4 Strap). Take off the strap if it is in the Node not used mode.

3) Check if the CINIA fails to function. Reset the CINIA if a Function Failed has occurred. If the Function Failed has frequently occurred(4 ~ 5 times or more a day), replace the CINIA with a new one.

4) Check whether or not the Gateway Node is normally duplicated in Active/Standby.

Related commands

Use the following commands to check the CIN status :DIS-NODESTS

RESET-NODE

TEST-NODE

SWT-GW

1.3.3CIN Status MonitoringThe CIN status monitoring is done by the SSC, the software block of the OMP, by means of the IPC answer-back as to the ASP and CIP at regular intervals. The monitoring applies to the CIN control processor(CIP), CIP node, CCS gateway node and U-Link cable(between the CCS gateway node and OMP gateway).The CIN status monitoring can be done only if the TD-bus connection is normal through the CCPP. If the normal condition is negative, the following message appears on the screen :

F5140 IPC NODE FAULT CHECK REPORT

INF : CHECK IF CCPP IS ABNORMAL

CIN state monitoring procedure

1) Check the OMP state and P-bus state of the CCS.

2) Check the data collected by the CCPP through the TD-Bus, by means of combination.

CIN state output

The output of the CIN status monitoring result is as follows :

CCS link faultF5140 IPC NODE FAULT CHECK REPORT

INF : CHECK CIN MODULE

CIP node faultF5140 IPC NODE FAULT CHECK REPORT

LOC : CINI(CIP node)

INF : MMC[TEST-NODE | RESET-NODE]

CCS gateway node faultF5140 IPC NODE FAULT CHECK REPORT

LOC : CINI(CCS gateway)

INF : MMC[SWT-GW | TEST-NODE | RESET-NODE]

U-Link cable faultF5140 IPC NODE FAULT CHECK REPORT

INF : CHECK CABLE BETWEEN CCSGW and OMPGW

CIP no responseF5140 IPC NODE FAULT CHECK REPORT

LOC : CIP FOR IPC

INF : MMC[RESET-CIP]

TD-Bus faultF5140 IPC NODE FAULT CHECK REPORT

INF : CHECK IF TD-BUS ABNORMAL

Related commandsUse the following commands to check the CIN status :DIS-CISTS

RESET-NODE

TEST-NODE

SWT-GW

RESET-CIP

2MP Fault Handling

2.1MPH Fault Handling

2.1.1Introduction The Main Processor Hardware(MPH) block is composed of the Main Processor Duplication Manager Assembly(MPDMA) and the Main Processor Back Panel Assembly-A(MPBPA) or the Main Processor Back Panel Assembly-B(MPBPB).

2.1.2MPH Function

The MPH performs the operations and maintenance for each subsystem, call processing controls, number translations and low-level processor controls.

MPDMA

The MPDMA is composed of the following function blocks :

1) Main Control Part(MCP) Main Processor : MC68LC060, 50 MHz

Main Memory : 16 ~ 128 Mbytes(Default 128M : 32M x 4 EA)

Peripheral : MC68901(MFP) ( 2

VME Interface : CA91C078(VME64 supportable)

LAN Interface : AM79C965, 10Base-T

F/W : 2 Mbytes Flash EPROM

Alarm Gathering/Reporting2) Inter Processor Communication Handling(IPCH)

Co Processor : MC68360, 25 MHz

Local Memory : 4 Mbytes DRAM

P-BUS Interface

3) Shared SRAM

2 Mbytes Fast SRAM

Communication path between the MCP and IPCH, and used to store the IPC data.

4) U-Link Interface

U-Link Interface/P-Bus Interface

5) Duplication Control Part Concurrent writing in duplication mode.

The DRAM of MCP and the Shared SRAM are both duplicated.MPBPA

The MPBPA is the back panel that accommodates PBAs of the MPH block and has two pieces of MPDMAs. MPBPA configures duplication channels between the MPs and its configuration includes the SPA-B type of power source as well.

Besides, the MPBPA is connected with various kinds of signals including the duplication signals between the MPDMAs, P-BUS, U-Link, VME Bus and those for alarm interface with other blocks.

2.1.3Fault DiagnosisDiagnosis procedure

Visual Check1) MPDMAs LED Check

Read the OSI of the SDX-MSC II and check the status of the MPDMA.

2) MPH block cable Check

Read the OSI of the SDX-MSC II and check the cable connection status of the MPH block.

Status Check using the MMC

Use the following command to check the MPH state.

DIS-PRC-STS:MP;

Test Point CheckThe diagnostic entries for each test point of the MPH are as follows :

Test PointDiagnostic entries

IPC pathBoot up the MP in the diagnostic mode and perform the > t ipchstart test.

MPDMA IPCH functionBoot up the MP in the diagnostic mode and perform the > t bi (Booting IPCH) test.

P-Bus functionConnect the Debugger Port to the IPCH and perform the IPCH> db 1 test to check the Loopback function.

Function between U-Link and P-BusIf the CI block / Switch block is normal, perform the logic test; and boot up the MP in diagnostic mode to perform the > t oneboard test.

Duplication functionPerform the > t mdDup, > t msDup, > t isDup test for both sides.

Memory statusPerform the > t mcpdram test for the DRAM.

Perform the > t mcpshare, > t ipchshare, > t jointshare test for the SRAM.

Resource access functionIf the MFP, LAN chip or VME chip is suspicious of a fault, perform the > t mpiclan, > t 140 ~ 144, > t 160 test.

2.2OMPH Fault Handling2.2.1IntroductionThe Operating and Maintenance Processor Hardware(OMPH) is a high-level processor in the Common Control Subsystem(CCS) of the SDX-MSC II, and a hardware block that performs the system-level operation, O&M-related functions and the Man-Machine Communication(MMC) function.2.2.2OMPH Function

The OMPH configures the high-level processor in the CCS in order to keep a high reliability going and easy-to-make operational management and O&M for the SDX-MSC II switching system. It provides various kinds of functions; information processing, program and data memory, IPC function for communication with other processor units, interface with secondary memory units such as SDU and DKU, I/O unit interface between the switching system and user, and alarm collection from the PP of the internal block. The OMPH has a duplication structure of active and standby sides in preparation for functional reliability, and all the I/O ports and the SCSI bus are configured in duplication mode as well. Main Processor Duplication Manager Assembly(MPDMA)The MPDMA provides various kinds of functions ; main processor function, memory, duplication mode, IPC communication with other subsystems and its processor units within the same subsystem.The MPDMA is composed of the following function blocks :

1) Main Control Part(MCP)

Main Processor : MC68LC060 50/66 MHz

Main Memory : 32 ~ 128 Mbytes Peripheral : MC68HC901(MFP) x 2

MPS Bus interface : SCV64(VME64 supportable)

LAN interface : AM79C790(AMD), 10Base-T

F/W : 1 Mbyte Flash Memory

2) IPC Handling Part(IPCH)

Co-Processor : MC68360, 25/33 MHz.

Local Memory : 1 Mbyte DRAM.

U-link interface : Gateway for communication with the processors of the other subsystems.

P-BUS interface : Serial bus for communication with PP in the same subsystem. 2 Mbytes Shared Memory : Used for communication between the MCP and IPCH, and for the IPC data memory.

Duplication Control : Supports Concurrent Writing in the duplication mode. The DRAM of MCP and the Shared SRAM are both duplicated. Collection of alarm signals from the PP block of the same subsystem.Main Processor SCSI Bus Interface Assembly(MSBIA)The MSBIA transmits messages and data through the MPDMA and MPS Bus, and controls secondary memory units such as SDU and DKU through the single-ended type of SCSI bus standard universal I/O mode. Also, the MSBIA provides an interface with various kinds of I/O devices for communication between the system and user.The MSBIA is composed of the following function blocks :

Main Processor : MC68360 33 MHz

Memory : 256 Kbytes Flash Memory, 16 Mbytes Local DRAM

Single-Ended type of SCSI-II interface : NCR53C720 x 2

16-Async ports for I/O device interface : CL-CD1865x 2

2-Sync ports for the V.35 interface : SCC2, 3 of MC68360

MPS Bus interface

Shared memory for MPS Bus interface : 512 Kbytes SRAM

I/O Auto-Port-Switching and Level(TTL RS232C) conversionsOperating and Maintenance Back Panel Assembly(OMBPA)The OMBPA is the backboard that accommodates the MPDMA and MSBIA of the OMPH, and is connected with the U-link, P-BUS and alarm cable. The OMBPA has an SCSI bus and I/O port connector.

Disk Driver Unit(DKU)The DKU is a random access storage device which is compatible with a single-ended type of SCSI-II interface. The DKU memorizes a generic program, database and I/O messages at the system level.Two DKUs are connected with the SCSI-Bus(A and B) and are duplicated in a pair, but run in one. When data is written to the DKU, the data is simultaneously written to both DKUs and when data is read from the DKU, the reading is done from the active DKU not the standby.Digital Audio Tape Driver Unit(DAU)

The DAU is compatible with the single-ended type of SCSI-II interface and uses a universal digital audio tape driver whose operation is performed by means of the conversion of -48V input into +12/+5V. This keeps information of billing, statistics, O&M and operational management, etc.As for the DAU number, 0 and 1 are assigned to the two DAUs connected with the SCSI A bus, and number 2 is assigned to one DAU connected with the B-bus. Upon mounting, DAU or RDAKU is regarded as an SDU, and then they operate as SDU 0, SDU 1 and SDU 2 respectively when using the MMC commands.

2.2.3Fault DiagnosisDiagnosis procedureVisual Check1) OMBPA Strap and Cable Check

Read the OSI of the SDX-MSC II and perform a visual check.

2) SCSI Device ID and SCSI Termination Check


3) Check the LED and Strap of the MPDMA, MSBIA and DKU

Read the OSI of the SDX-MSC II and perform a visual Check.

Check the status using the MMC commands Use the following commands to check the status of the processor, SCSI device and I/O ports, etc :

DIS-PRC-STS

DIS-DKU-STS

DIS-SDU-STS

TEST-SDU

DIS-IO-PORT

Test points checkThe test points and its diagnostic entries of the MPDMA are as follows :

Test PointDiagnostic Entries

IPC pathBoot up the MP in diagnostic mode and perform the > t ipchstart test.

MPDMA IPCH functionBoot up the MP in diagnostic mode and perform the > t bi(Booting IPCH).

P-Bus functionConnect the debugger port to the IPCH and execute the IPCH> db 1 to test the Loopback function.

Function between U-Link and P-BusIf the CI block /Switch block is normal, perform the G->U & U->G logic test.

Boot up the MP in diagnostic mode and perform the > t oneboard test.

The test points and its diagnostic entries of the MSBIA are as follows :


SCSI Interface signal contactSCSI Controller Chip(NCR53C720x2)

RS-232C signal contactI/O communications Chip(CD1865x2)

3PPH Fault Handling3.1Introduction The PPH is a low-level processor block and interface block between the telephony device and high-level MP block, and provides a P-bus interface and TD-bus interface.

The PPH block is composed of the Telephony Device Control Master Assembly (TDCMA) board.

3.2PPH Functions

TD-BUS status check

Check if a fault exists on the TD-bus by reading data from the register that is used for communication between the PP and device.PPprtu

prtu on

(If you key in prtu when it remains off, it gets active toggle mode.)

Execute the following command in the prtu on state :

PPaccessdev port mode offset r|w data Port(0~3) : A~D port

Mode(0~7) : MODE 0~7 Offset : Value of each device

R|W : Read or Write

Data : Data for writing

As an example, if the checked result of the communication state between the PP and NSCMA is regarded as normal. accessdev 0 0 020006 w aa

PP> accessdev 0 0 020006 r

Adderss : 020006 Data : aa

IPC bus state CheckExecute the IPC log.

3.3Fault DiagnosisDiagnostic procedureVisual Check1) Check DIP switch and cable of the TMBPA

Read the OSI of the SDX-MSC II to perform a visual check.

2) TDCMA LED Check

Read the OSI of the SDX-MSC II to perform a visual check.

Status check using the MMC commands

Execute the following command to check the processors status.

DIS-PRC-STS

Test points check

1) Short-circuit the 2-7 shunt of the J2 stick, mount the board and perform the test for each entry.

The output below shows an example of a test for the entry No. 100.

> t 100

100 - MCP Dram Data Bus

101 - MCP Dram Address Bus

102 - MCP Dram Full Address

103 - MCP Dram Full Plus Read After Write

104 - MCP Dram Byte Read

105 - MCP Dram Byte Write

106 - MCP Dram Mis-align Read

107 - MCP Dram Mis-align Write

108 - MCP Dram Cache Line Read

109 - MCP Dram Cache Line Write

111 - MCP Dram Execution

120 - MCP Shared Data Bus

121 - MCP Shared Address Bus

122 - MCP Shared Full Address

123 - MCP Shared Full Plus Read After Write

124 - MCP Shared Byte Read

125 - MCP Shared Byte Write

126 - MCP Shared Mis-align Read

127 - MCP Shared Mis-align Write

130 - MCP Flash Byte Read

131 - MCP Flash Mis-align Read

140 - MCP MFP Chip Access

141 - MCP MFP Timer

144 - MCP MFP Interrupt

170 - MCP Interrupt from IPCH

171 - MCP Interrupt to IPCH

189 - Set Data Cache Off

198 - MCP Load Sram and Start IPCH

199 - MCP Load Sram and Start IPCH Xray

200 - IPCH Dram Data Bus

201 - IPCH Dram Address Bus

202 - IPCH Dram Full Address

203 - IPCH Dram Full Plus Read After Write

204 - IPCH Dram Byte Read

205 - IPCH Dram Byte Write

206 - IPCH Dram Mis-align Read

207 - IPCH Dram Mis-align Write

220 - IPCH Shared Data Bus

221 - IPCH Shared Address Bus

222 - IPCH Shared Full Address

223 - IPCH Shared Full Plus Read After Write

224 - IPCH Shared Byte Read

225 - IPCH Shared Byte Write

226 - IPCH Shared Mis-align Read

227 - IPCH Shared Mis-align Write

298 - IPCH Boot Diags to Dram

299 - IPCH Boot Xray to Dram

>

4NES Fault Handling4.1IntroductionThe Network Synchronization System(NES) is a block that makes the system synchronize with the reference clock of a switching network in order to avoid a slip that may be generated from the clock frequency due to an inconsistency.

The NES block receives DOTS, TRUNK and the standard clock as reference clock, and generates and distributes other clocks synchronized with the reference clock. Also, the NES block uses a clock from the oscillator(OVCXO) in order to generate a clock needed for the system operation, and distributes the real-time clock.

4.2NES Functions

The NES block is composed of a clock generation part(NSCMA) and clock distribution part(NSCGA).

Network Synchronization Clock Maintenance Assembly(NSCMA)The NSCMA performs the following functions :

DP-PLL control : Consists of Z80180, PROM and SRAM.

Detection of the phase error : Detects the different phase between the system oscillators clock and the reference clock. Adjustment of the OVCXO output frequency : Controls the OVCXO, using the phase error data from built-in firmware and the D/A converter.

Calendar function : Provides the basic clock for the system.

Generation of the systems basic clock : 32.768 MHz.

Interface for the low-level processor(PP).Network Synchronization Clock Generation Assembly(NSCGA)The NSCGA performs the following functions :

Reference clock Rx Trunk RS-485 Diff. Level 3 lines(T1/CEPT clock, Frame Alarm)

DOTS : Bipolar Diff. Level 2 lines(CEPT clock) Standard clock : 50 ohm co-axial cable 2 lines

Selection of reference clock : Selects the Trunk, DOTS and standard clock in sequence controlled by the PP.

Selection of the system basic clock(32.768 MHz) : Receives a clock of four lines from the system clock generation part and selects one line. Distributes 16.384 MHz(CP2) and 8 KHz(FP2).

Distributes 64 ports in maximum to the SSL block -- (3x3 cable 64 e/a)

Uses 96-pin secondary connector.

Fine-tuning of the different phases of the 32.768 MHz clock : Fine-tunes the different phases between two kinds of oscillator clocks, loaded on two lines, from the clock generation part. Supervision of all types of clock : Monitors all kinds of clock on the NSCGA board.Network Synchronization Back Panel Assembly(NSBPA)The NSBPA, the back panel, accommodates the NES block including four NDCMAs and two NSCGAs.

The NSBPA performs the following functions :

Input of the trunk line clock : Receives reference clock for 3 ports in maximum through the 3x3 cable from the trunk line.

classificationABC

1NSRF-FA-

2NSRF+FA+

3

Input of the DOTS clock : Receives a 2.048 Mbps PCM clock through two ports in maximum from the DOTS equipment. Input of standard clock : Receives a 10 MHz clock through four ports in maximum from the BNC coaxial cable. TD-BUS interface : Transmits and receives the pertinent data to/from the PP through a 3x7 cable.

classificationABC

1SCLK+ACTOUT+SCLK-

2FS+ACTOUT-FS-

3RDY+DOFALMRDY-

4MAD0+PGNDMAD0-

5MAD1+ACFALMMAD1-

6MAD2+FUFALMMAD2-

7MAD3+MAD3-

Output of the system clock : Displays the system clock to 64 ports in maximum to the SSL block, including the duplication mode.

classificationABC

1CP2+VALFP2+

2CP2-FP2-

3GNDGND

4.3Fault DiagnosisDiagnosis procedure

Visual Check1) Check DIP switch and cable of the NSBPA


2) Check LEDs of the NSCGA/NSCMA


3) Strap check for the NSCGA/NSCMA


Status check using MMC commands

Execute the following commands to check the NES block status :DIS-NES-STS

DIS-NES-REF

DIS-NES-SLIP

Execute the following commands to check the phase detectors status :DIS-NES-FREQ

DIS-DATE

Test points check

1) Use the point of the NSCMA J1 stick to check the following entries :


Input Reference Frequency(PERF0, PERF1)Input Reference Frequency 4 KHz Chip

Output 32 MHz Frequency(TP32)Output 32 MHz Drive Chip

2) The diagnostic entries for each test point of the NSCGA are as follows :


Input Reference Input reference clock

Analog PLL 4 KHz Analog PLL

32.768 MHz from NSCMAChip for clock Rx from NSCMA

System clock CP2, FP2System clock transceiver chip

PP Interface Fault Diagnosis

Connect the RS-232C port to the PP of the pertinent board and execute the following command :PP> prtu

prtu on

If it is in a prtu off state, execute the prtu again to activate the function.

If prtu on, execute the following command to write(w) data and test the function to read(r) the data correctly.pp> accessdev port mode offset r|w data

Port(0~3) : A~D port

Mode(0~7) : MODE 0~7 Offset : Value of each device

R|W : Read or Write Data : Data for writingDACW range Check

Execute the following command to check the DACW value of the NSCMA.

DIS-NES-STS

Generally, when the DACW value reaches a value as much as 3/4 of the threshold, it is called a Range Over. This applies to the DACW value less than the H1fff or equal to or greater than He000.

The Range Over can be generated from the aging of the oscillator. In that case, adjust the natural frequency of the oscillator.

Slip generation check

Execute the following command to check the slip count of the NSCMA.

DIS-NES-STS

When the locking mode of the NES is kept in a NORM state, the slip count shall be 0. If the slip count is not 0, check the oscillator.

5SSL Fault Handling5.1IntroductionThe Space Switch & Link(SSL) block pertains to the Interconnection Network Subsystem(INS). The Space Switch Matrix(SSMXA) of the SSL block receives PCM data of 16.384 Mbps in parallel 9 bits/ch 2.048 time slots per highway -- at a differential level from the Central Optic Transfer & Receiver Interface(CTRIA), and performs the space division switching by means of parallel switching.

5.2SSL FunctionsThe SSL receives control data for the space division switching through the Telephony Device Bus(TD-bus) from the INPP and stores the data to the built-in control memory(SCM) of the SSMXA, then reads it sequentially for switching.

The CTRIA receives PCM data switched by time division in the Time Switch & Link (TSL) block of the Access Network Subsystem(ASS), and transmits the data to the SSMXA.

The SSL receives synchronous clock -- FP2(8 KHz) and CP2(16.384 MHz) in duplication from the CDPIA for internal working.

Alarm signals generated from the SSL are transmitted to the INPP.Optic Transfer & Receiver Module Assembly(OTRMA)

The OTRMA is mounted on the TSL and SSL blocks, and performs the E/O & O/E conversion function. The OTRMA is a daughter board that is installed in the rear side of the TSBPA and SSBPA.

Central optic Transfer & Receiver Interface Assembly(CTRIA)The CTRIA configures the 155.520 Mbps STM-1(OC-3) frame made of 64 Kbps subscriber telephony channel data(2,048 time slots), the subscriber data-related signals(256 time slots), and the 8.192 Mbps IPC data. Through the data link, the CTRIA is connected with the Local Optic Transfer & Receiver Interface Assembly (LTRIA) of the TSL pertaining to the ASS, and interfaces with the SSMXA(Matrix) for 16.384 Mbps N highway(9 bits by one). (A total of 8 in the ASS->INS direction and a total of 4 in the INS->ASS direction)

The clock used by the CTRIA to interface with the SSMXA and to transmit data to the TSL is the clock information from the Clock Distribution & Processor Interface Assembly(CDPIA). The clock used by the CTRIA to receive and process the data from the TSL is the timing-recovered clock in the Rx data.Space Switch Matrix Assembly(SSMXA)The SSMXA receives the parallel 9-bit highway link data of 16.384 Mbps at pseudo ECL differential level from the CTRIA. Also, it transmits the parallel 10-bit matrix output highway data of the space division switched 16.384 Mbps to the CTRIA, at pseudo ECL level, in the form of a back board pattern. One piece of SSMXA has the capacity of connecting 8 highway links(2,048 time slots) to the CTRIA.The SSMXA collects and memorizes all kinds of internal faults and when the INPP requests it to transmit the fault status data, it performs a reporting function.

Also, the SSMXA receives the system synchronous clock FP2(8 KHz) and CP2 (16.384 MHz) at pseudo ECL differential level from the CDPIA.

Clock Distribution & Processor Interface Assembly(CDPIA)The CDPIA receives a clock from the Network Synchronization(NES) block and generates and distributes all kinds of timing signals requested by the SSL. From the NES, the CDPIA receives CP2(16.384 MHz) and FP2(8 KHz), but practically the CTRIA needs SP2(19.44 MHz) and SFP2(8 KHz), as well. Therefore, the CDPIA has a PLL circuit capable of generating the SP2 based on the FP2 as a reference signal from the NES. When a fault occurs in the clock from the NES, the CDPIA uses the clock that is internally generated from its oscillator. In this case, a communication path can be made only between the ASSs whose connection has been made with the same SSBPA.

Additionally, the CTRIA interfaces with the INPP through the TD-BUS, and performs the O&M function such as alarm & error collections from the SSL, duplication controls, link status monitoring and test, etc. Space Switch Back Panel Assembly(SSBPA)The SSBPA accommodates 8 CTRIAs, 2 CDPIAs receiving a clock from the NES and interfacing with the processor and 6 SSMXAs performing the space division switching for the PCM data.5.3Fault DiagnosisDiagnosis Procedure

Visual Check1) SSBPA DIP switch and cable Check


2) Checksum & Version Check

Check the checksum value and version of the FPGA/EPLD to see whether or not

it has the latest values.

3) Check LEDs of the SSMXA/CTRIA/CDPIA

Read the OSI of the SDX-MSC II and perform a visual check.4) Strap check of the NSCGA/NSCMA


Check the status using the MMC commands

Check the SSL block status using the following commands :DIS-SSL-STS

DIS-SNLK-STS

DIS-SSCM-STS

DIS-PATH-STS

For details of each command refer to the SDX-MSC II COD

Check the SSL path status, using the following commands :TEST-LP

TEST-BER

TEST-PATH

TEST-SSW-CM

CHG-SN-MODE


SSL Status Management Fault Check

Connect the RS-232C port to the PP of the pertinent board and execute as follows :PP> prtu

prtu on

If the PRTU remains deactivated, execute the PRTU once more to activate it -- toggle command.

If in a prtu on state, execute the following command to write (w)data and then, perform a test to read(r) the data to see if it is correct.pp> accessdev port mode offset r|w data Port(0~3) : A~D port

Mode(0~7) : MODE 0~7 Offset : Address to access

R|W : Read or Write Data : Data for writing Parameter offset format

A23~A21

A20~A16

A15~A13A12~A11A10~A0

Back Bd IDSlot NumberSCM#Time Slot Number

Slot Number

BOARDA20A19A18A17A16Remark

CTRIA A[3:0]000nn0x00~0x07

CTRIA B[3:0]100nn0x10~0x17

CDPIA(A)001000x04

CDPIA(B)101000x14

SSMXA A[3:0]010nn0x08~0x0b

SSMXA B[3:0]110nn0x18~0x1b

SSMXA clock status check

Check the 16.384 MHz and 8 KHz frame pulses, the switching clock, manipulating the test point on the front side of the SSMXA.CTRIA clock status check

Check the 16.384 MHz & 8 KHz frame pulses, and 19.44 MHz(SP2) & 8 KHz(SFP2) frame pulses, manipulating the test point on the front side of CTRIA.

6TSL Fault Handling6.1IntroductionThe Time Switch & Local Link(TSL) block pertains to the Access Switching Subsystem(ASS) and performs the functions of a Time Slot Interchange(TSI), concentration, IPC communications path configuration, tone feeding, optic interface, and so on. Also, the TSL connects subscribers and trunk line equipment with the signal processing equipment, announcement machine/conference call equipment.

6.2TSL FunctionsThe TSL block is composed of the Time Switch Control & Maintenance Assembly (TSCMA), Sub-highway Multiplex & De-multiplex Assembly(SMDXA) and Local optic Transfer & Receiver Interface Assembly(LTRIA) for the SSL.Optic Transfer & Receiver Module Assembly(OTRMA)

The OTRMA is built in the TSL and SSL blocks, and performs the E/O & O/E conversions.

The OTRMA is a daughter board mounted on the rear side of the TSBPA and SSBPA.

Local optic Transfer & Receiver Interface Assembly(LTRIA)The LTRIA configures 64 Kbps subscriber telephony channel data of 2,048 time slots(131.072 Mbps), subscriber data-related signal of 256 time slots and 8.192 Mbps IPC data into a frame of 155.520 Mbps STM-1(OC-3). Also, the LTRIA links to the Central optic Transfer & Receiver Interface Assembly(CTRIA) of the SSL of INS through a data link.Sub-highway Multiplex & Demultiplex Assembly(SMDXA)The SMDXA receives 2.048 Mbps serial data from 64 pieces of sub-highway and converts the data into 8.192 Mbps parallel data through the MUX, then performs the multiplexing for two links that are arranged by 1K respectively. After this, it transmits the data to the TCSMA through the memory of the multi-time slot function.

The SMDXA receives a 8 KHz frame pulse and 16.384 MHz clock from the TSCMA and transfers them to the MUX/DMUX, then generates the address of multi-time slot memory and de-multiply 4.096 MHz clock. After this, it transmits them to a device through the sub-highway cable along with the frame pulse.

Time Switch Control & Maintenance Assembly(TSCMA)The TSCMA receives the multiplexed voice data from the SMDXA and performs the time switching. The Intra-Junctor side of the TSCMA performs the functions of Intra-Junctor, additional service equipment interface and signal processing interface.

Also, the TSCMA feeds tone and inserts and extracts the BERT and the Cut-Off-Call Bit(COB).6.3Fault DiagnosisDiagnosis procedureVisual Check1) DIP switch check of the TSBPA and its cableRead the OSI of the SDX-MSC II and perform a visual check.

2) Checksum & Version check

Check the Checksum value and version of the SMDXA/TSCMA to see whether or not it has the latest values.3) Check LEDs of the SMDXA/TSCMA LED



Use the following commands to check the TSL block status :DIS-TONE-STS

DIS-TSW-STS

DIS-IJ-STS

Use the following commands to check the TSL path status :TEST-LP

TEST-SP

TEST-TONE

TEST-TSW-CM

CHG-SN-MODE


Test points check

1) Check the SMDXA J2 Stick

Pin 1 : MFS

Pin 2 : M4CLK

Pin 3 : FP2

Pin 4 : SDCP2

Pin 5 : MDCP2

Pin 6 : FP3

2) Check the TSCMA J4 & J5 Stick

StickSignal

J4 StickPin 1 : CP_ST

Pin 2 : MCLK_ST

Pin 6 : MFS_ST

Pin 7 : FP_ST

J5 StickPin 1 : FS_A

Pin 2 : MAD0_A

Pin 3 : MAD1_A

Pin 4 : MAD2_A

Pin 5 : MAD3_A

Pin 6 : RDY_A

Pin 8 : SCLK_A

SMDXA Fault CheckFaultsSolution procedure

SMDXA function failed1. Check the LED status.

2. Diagnose the internal board fault.(Use the PP interface command.)

3. Replace the function-failed chip if it is the internal board fault.

SHW data communication failedPerform the loop test for the pertinent SHW. If a specific SHW is at fault, check if the MUX/DMUX and Driver/Receiver chip are at fault, and replace them with new ones.

CP2, FP2 clock failed1. Check whether the TSCMA is faulty or mounted, and is normal.

2. Check the waveform of test point J2 on the internal board.

3. If the waveform is not normal, trace the clock generation part and replace the fault chip with a new one.

PP communication failedPerform the communication test, using the PP interface command. If it fails the test, Check the TD-BUS EPLD and Driver/ Receiver Chip and replace the faulty one with a new one.

TSCMA Fault CheckFaultsSolution procedure

TSCMA function fail1. Check the LED status.

2. Diagnose the internal board fault.(Use the PP interface command.)

3. Replace the function-failed chip if it is the internal board fault.

PCM data communication failedCheck that a specific data line/CH or all the lines and channels are faulty, concerning the TEST-SP/TEST-PATH. Then, replace the faulty chip on the path.

Intra-Junctor SHW

Data communication failedPerform the loop test for the Intra-Junctor SHW. If a fault exists on a specific SHW, check if the MUX/DMUX and Driver/Receiver Chip are at fault. Then, replace faulty one with a new one.

PP communication failedPerform the communication test, using the PP interface command. If it is a communication fault, check if the TD-BUS EPLD and Driver/ Receiver Chip are faulty, and replace the faulty one with a new one.

No tone and fault1. Check the working state of the TDSP ASIC chip(PP Interface communication test).

2. Check if it comes from the path.(Use the TSCMA online test command.)

3. If a fault occurs in the test, replace the ASIC chip and a faulty one on the path with a new one.

SMDXA Registers Test>accessdev 0 0 040000 r(enter)

34(normal) => board ID

>accessdev 0 0 040001 r(enter)

00(normal) => D7:FUF, D6:DOF_A, D5:DOF_B, D4:OACF, D3:OFUF, D2~D0:Not used


00(normal) => D7~D3:Not used, D2:DMUX Fail, D1:MUX Fail, D0:CP2 Clock Fail


xx => D7:Act/Std chang, D6:FUF Masking, D5:ACF Masking, D4:Not used, D3:My ACT/STB status, D2: Other ACT/STB status, D1:Other DEL ALM, D1: Other PWR ALM

>accessdev 0 0 040006 w aa(enter)


Check if the written aaH value is normally read.

TSCMA Registers Test>accessdev 0 0 000000 r(enter)

30(normal) => board ID


00(normal) => D7:FUF, D6:DOF_A, D5:DOF_B, D4:OACF, D3:OFUF, D2~D0:Not used


00(normal) => D7:Not used, D6:MUX Odd Fail, D5:MUX Even Fail, D4:DMUX Odd Fail, D3:DMUX Even Fail, D2:TDSP Fail, D1:Tone on-line state, D0:CP2,FP2 Fail


xx => D7:Act/Std chang, D6:FUF Masking, D5:ACF Masking, D4:Not used, D3:My ACT/STB status, D2: Other ACT/STB status, D1:Not used, D1: Other PWR ALM

>accessdev 0 0 000006 w aa(enter)


Check if the written aaH value is normally read.

One-way call

A One-way call can occur due to the following reasons :

Read/Write error in the control memory of the time switch

Control memory write error in the space switch

PCM data communication error of the SMDXA

Control error of the SCCIA, the DLC block

PCM data communication error of the SCCIA

For a One-way call, perform the test as follows :

Perform the test using the TEST-LP command.

Check the data timing of the SMDXA. If the timing is not correct, replace the pertinent chip with new one.

Perform the Read/Write test for the control memory of the SCCIA and Check the PCM data timing.

Noise during a call

For noise during a call, perform the test as follows :

Data communication timing : If the timing is abnormal, check the pertinent chip. Then, replace it with a new one if it is abnormal.

Writing on the control memory of the time switch. Check the subscriber block : Check if the noise on the PCM data is getting worse.

7DSC Fault Handling

7.1DSMSA IntroductionThe DSMSA performs the In-bank signal processing in the SDX-MSC II system.

The DSMSA is composed of the following function blocks : TD-Bus interface : Interfaces the TD-bus with TDCMA. DPRAM interface : Uses one piece of Dual Port I/O RAM(2K Byte) to supply the Word Operation for control data Tx/Rx to/from the u-processors (MC68306FC16A) in the TDCMA and DSMSA. UP and peripheral circuitry : Performs the control data interfacing with the PDCMA, signal processing part control and state control for the DSMSA.

Signal processing function : Performs the PCM data processing. Alarm and state interface : Collects all kinds of alarm and status information generated from the DSMSA.

SHW interface : Performs the interfacing of the PCM path(of TSL block) with the signal processing part. Reset function : Performs the initialization for the DSMSA.7.1.1Fault DiagnosisDiagnostic procedureVisual Check1) DSMSA LED Check


2) DSMSA cable Check

Read the OSI of the SDX-MSC II and Check the sub-highway cable connection, the path of the PCM data assigned in the DSC block.


Use the following commands to check the DSC block status :DIS-DSC-STS

DIS-DSC-CONF

TEST-DSC

TD-Bus interface ability Test

Connect the RS232C port cable with the debug port(choose the upper port of the two ports) of the ASPP that controls the DSC block, and performs the following test, and reads data from the registers that are used for communication between the PP and DSMSA. Then, check if a fault exists on the PBA.

RMOS_PP:1010>accessdev

RMOS_PP:1010>

Usage : accessdev port mode offset r|w [data]

port : 0 ~ 3 mode : 0 ~ 7 offset : 0x000000 ~ 0xffffff

RMOS_PP:1010>accessdev 1 0 040000 rThe accessdev command has the following parameters :

Port : Port of the TD-Bus(1 means port B). Mode : Mode 0 means byte.

Offset : The offset is composed of the slot ID and address, and the address means that of the Board Identification Register(BIRD) indicating the board ID.

D5D4D3D2D1D0

Slot IDADDRESS

R/W : Indicates Read/Write.

Check the result of the following accessdev command for the board ID and version depending on the meaning of each bit whose data has been read.

RMOS_PP:1010>accessdev 1 0 040000 r

RMOS_PP:1010>

cnt = 00, sr = 0 48 7

cnt = 1, sr = 0 4c 7

cnt = 2, sr = c0 4f 7

Actual Addr : 7040000 Read : 3c Actual Address : The DPRAM address of the PP when access is made from the PP to DSMSA.

Read : 3c is because the r(read) has been designated in the command option and has the address structure as follows : (00111100 => 0x3c)REGISTER NAMEBIDR(Board Identification Register)Remark

ADDRESS0(Read Only)

D7~D2BIDUnique ID of each board (DSVMB : 0x12)

D1~D0VERVersion No(1)

Online check of the PP

1) Check the information of the TD-bus port that is used by the DSMSA board.

RMOS_PP:1010>ucmport

RMOS_PP:1010>

+----------+--------+-----------+---------+------------+------------+

| port_no | equip | svc_side | state | my_dcbus | part_dcbus|

+----------+--------+-----------+---------+------------+------------+1 EQ MY ACTIVE 0 0 0 0

Check the connection status of the TD-bus referring to the result of the ucmport command or replace the TD-bus with a new one.

2) Check the information of the boards mounted on the DSC block.

RMOS_PP:1010>ucmcard

RMOS_PP:1010>

+--------+--- -----+--------+---- ------+------ -+---------+

| card_no|card_conf|card_info|card_state|svc_flag|spec_flag|

+--------+---------+---------+----------+--------+---------+ 0 DSVMB DSVMB NORM ON -

1 DSCMA DSCMA NORM ON -

2 DSMSA DSMSA NORM ON -


4 DSDTA NEQ EJECT OFF CLEAR

5 NEQ NEQ NEQ OFF -

6 NEQ NEQ NEQ OFF -

7 NEQ NEQ NEQ OFF -

8 NEQ NEQ NEQ OFF -

9 NEQ NEQ NEQ OFF -

10 NEQ NEQ NEQ OFF -







Check if the DSMSA board has been already mounted on the same slot as that indicated in the result of the ucmcard command.3) Check the emergent fault register (CASR) and the detailed fault status register (DASR) as to the board displayed.

RMOS_PP:1010>ucmalarm

RMOS_PP:1010>

Usage : ucmalarm typetype : c -> cmx, d -> dte, u -> usi, v ->vmh

RMOS_PP:1010> ucmalarm u

>

+-------+----+---+------+-----+--+---+- +--+--+

|card_no|type|FUF|DOF(A)|DOF(B)|B4|B3|B2|B1|B0|

+-------+----+---+------+-----+--+---+- +--+--+ 2 DSMSA X X X - - - - -

3 DSMSA X X X - - - - -

4 DSDTA X X X - - - - -

>

+--------+----+----+------+------+----+----+--+--+--+

| card_no|type|PCLK|SHW(1)|SHW(2)|DGF |CPU |B2|B1|B0|

+--------+----+----+------+------+----+----+--+--+--+ 2 DSMSA X X X X X - - -

3 DSMSA X X X X X - - -

4 DSDTA X X X X X - - -

FUF : Indicates that a fault has occurred in the internal board. Disconnect and mount the board again.

DOF(A) : Check if the A port TD-Bus cable is disconnected.

DOF(B) : Check if the B port TD-Bus cable is disconnected.

PCLK : Indicates the state of the SHW PCM clock, which failed.

SHW(1) : Indicates the state of the PCM SHW cable open.

SHW(2) : The internal DSMSA sets this bit to logical low.

DGF : Indicates that the board state is normal according to the self-diagnosis. Demount and remount the board again.

CPU : Indicates the CPU status failed. Demount the board and inspect the appearance of the CPU chip(MC68306FC16A).

The remaining bits are set to logical low in the DSMSA, so the value is 0.

7.2DSDTA IntroductionThe DSDTA performs the Tx characteristic test for the trunk under the control of the ASPP or Centralized Automatic Reporting On Trunk(CAROT).

There is a Code105 test and Code108 test in the Tx characteristic test of trunk.

Code105 test Measurement of residual loss Measurement of frequency loss(Gain Slope)

Measurement of psopho-metric noise(C-Message Noise)

Measurement of non-psopho-metric noise(C-Notched Noise)

Measurement of return los(ERL, SRL Hi, SRL Low)

Code108 test(BERT function)

511 Bits Pattern BERT

2047 Bits Pattern BERT

Fixed pattern test7.2.1Fault DiagnosisDiagnostic procedure

Visual Check1) DSDTA LED CheckRead the OSI of the SDX-MSC II and perform a visual check.

2) Check the DSDTA CableRead the OSI of the SDX-MSC II and check the connection status of the sub-highway cable, the PCM data path assigned to the DSC block.


Execute the following command to check the DSC block status :DIS-DSC-STS

DIS-DSC-CONF

TEST-DSC

TD-Bus interface testConnect the RS232C cable to the debug port(choose the upper port of the two ports) of the ASPP that controls the DSC block, and perform the following test, and reads data from the registers that are used for communication between the PP and DSDTA. Then, check if the PBA is faulty.RMOS_PP:1010>accessdev

RMOS_PP:1010>




The accessdev command has the following parameters : Port : Port of the TD-Bus(1 means the B Port.)

Mode : The mode 0 means byte.

Offset : Depends on the mounted slot.

00000x : For DSDTA0 Address0(when it has been mounted on the slot 0)

01000x : For DSDTA1 Address0(when it has been mounted on the slot 1)

02000x : For DSDTA2 Address0(when it has been mounted on the slot 2) r/w : Designates Read/Write.

Check the result of the following accessdev command as to the board status depending on the meaning of each bit of the read data.


cnt = 00, sr = 0 48 7

cnt = 1, sr = 0 4c 7

cnt = 2, sr = c0 4f 7

Actual Addr : 7020000 Read : xx

Meaning of each bit of the read data

D7D6D5D4D3D2D1D0

PCLKSHW0DGFCPUDSP00

PCLK : PCM Clock Fail[0 : Normal, 1 : Abnormal]

SHW : PCM Sub_Highway Cable Open Fail[0 : Normal, 1 : Abnormal]

DGF : Diagnostic Test Fail[0 : Normal, 1 : Abnormal]

CPU : The current state of the CPU[0 : Normal, 1 : Abnormal] DSP : Four DSPs states[0 : Normal, 1 : Abnormal]If the result of the command indicates a Diagnostic Test Fail, demount and remount the board again. Also, if it is regarded as DSP failed, demount the board and check the appearance of the DSP chip(320C50).

Additionally, use the following commands to check if the state of the TD-bus interface is normal by writing and reading data to/from the loopback register which is used in the PP communication online.

RMOS_PP:1010>accessdev 1 0 020006 w 55

cnt = 00, sr = 0 48 7

cnt = 1, sr = 0 4c 7

cnt = 2, sr = c0 4f 7

Actual Addr : 7020006 Write : 55


cnt = 00, sr = 0 48 7

cnt = 1, sr = 0 4c 7

cnt = 2, sr = c0 4f 7

Actual Addr : 7020006 Read : 55Code108 test function state Check

Check if the Bit Error Rate Test(BERT) is normal, using the trunk line test channel.1) Check if the BER testing No.(BERT DN) has been already registered at the counterpart station.

2) Check if the DSC block state is normal, execute the DIS-DSC-INF command.

3) Check if the Code108 test function is normal, execute the TEST-TRK-BERT command.

Code105 test function state Check

Check if the speech quality of the trunk channel is normal using the trunk line testing channel.1) Check the information of the counterpart station needed for the trunk line test, by executing the DIS-FER-INF command.

2) Check if the DSC block state is normal, by executing the DIS-DSC-INF command.

3) Check if the Code105 test function is normal, by executing the TEST-TRK-C105 command.

7.3DSCMA IntroductionThe DSCMA performs a three-way call function and conference call function in the SDX-MSC II system.

7.3.1Fault DiagnosisDiagnostic procedure

Visual Check1) Cable Check

Read the OSI of the SDX-MSC II and check the SHW cable and TD-Bus cable.

2) Checksum and Version CheckCheck if the checksum value and version of the DSCMA are last values.

3) DSCMA LED Check

Read the OSI of the SDX-MSC II and perform a visual check.Function Test

Use the following command to perform the functions of the local loopback test, remote loopback test and M34116 loopback test.TEST-BER


Use the following commands to check the DSCMA state :DIS-DSC-STS

TEST-DSC


Test points check

TD-Bus Interface TestConnect the RS232C cable with the debug port(choose the upper port of the two ports) of the ASPP that controls the DSC block, and perform the following test, and reads data from the registers that used for communication between the PP and DSCMA. Then, check if the PBA has a fault.


RMOS_PP:1010>




The accessdev command has the following parameters : Port : Port of the TD-Bus(1 means the B Port.)


OffsetD5D4D3D2D1D0

Slot IDAddress

R/W : Designates Read/Write.

Data : Data to write

7.4DSVMB IntroductionThe DSVMB saves and supplies an announcement message in the SDX-MSC II system.

The DSVMB is composed of the following function blocks :

TD-Bus interface : Makes a connection between the TDCMA and TD-Bus.

SHW interface : Makes a connection between the signal processing circuit and the PCM path from the TSL block.

SHW interface : Provides a PCM path between the TSL block and board, and receives clock and frame signals from the TSL and distributes them to the boards. Front side interface : Feeds the announcement message recording/replaying through the front side of the board. It can have editable data loading through the RS-232C port and can have F/W loading in the internal board as well.

P circuit : Performs the main function of the board and consists of program flash memory and data memory of the processor. Memory circuit : Is composed of DPRAM and flash memory. DPRAM can transmit and receive data for communication between P and the high-level processor within the board, and flash memory can save the fixed/editable message. Also, there is SRAM which is capable of memorizing temporary data for the addition/change of fixed message up to the time length of 64 seconds. Logic circuit : Sets up an environment for recording/replaying on the interface circuit on the front and makes the high-level processor accessible to the device within the board. Also, performs the status management function for all kinds of alarms.

7.4.1Fault DiagnosisDiagnostic procedure

Visual Check1) DSVMB LED Check


2) DSVMB Cable Check

Read the OSI of the SDX-MSC II and check the connection status of the sub-highway cable, the PCM data path assigned in the DSC block.


Use the following commands to check the DSC block status :DIS-DSC-STS

DIS-DSC-CONF

TEST-DSC


TD-Bus Interface TestConnect the RS232C cable to the debug port(choose the upper port of the two ports) of the ASPP that controls the DSC block, and reads data from the registers that are used for communication between the PP and DSVMB. Then, check if the PBA has a fault.


RMOS_PP:1010>



RMOS_PP:1010>accessdev 1 0 040000 rThe accessdev command has the following parameters : Port : Port of TD-Bus(1 means the B Port.)


Offset : Composed of the slot ID and address. The address means that of the Board Identification Register(BIRD) indicating the board ID.

D5D4D3D2D1D0

Slot IDADDRESS

R/W : Designates Read/Write.

Check the result of the following accessdev command as to the board ID and version depending on the meaning of each bit of the read data.


RMOS_PP:1010>

cnt = 00, sr = 0 48 7

cnt = 1, sr = 0 4c 7

cnt = 2, sr = c0 4f 7

Actual Addr : 7040000 Read : 3c Actual Address : DPRAM address of the PP when the PP has access to the DSVMB

Read : 3c is because r(read) has been designated in the command option and has the following address structure.(00111100 => 0x3c)REGISTER NAMEBIDR(Board Identification Register)Remark

ADDRESS0(Read Only)

D7~D2BIDEach board has a unique ID (DSVMB : 0x12)

D1~D0VERVersion No.(1)

Online Check of the PP1) Check the TD-bus port information used by the DSVMB.

RMOS_PP:1010>ucmport

RMOS_PP:1010>

+----------+--------+-----------+---------+------------+------------+

| port_no | equip | svc_side | state | my_dcbus | part_dcbus|

+----------+--------+-----------+---------+------------+------------+1 EQ MY ACTIVE 0 0 0 0

Check the connection status of the TD-bus referring to the result of the ucmport command or replace the TD-bus with a new one.

2) Check the boards information mounted on the DSC block.

RMOS_PP:1010>ucmcard

RMOS_PP:1010>

+--------+--- -----+--------+---- ------+------ -+---------+

| card_no|card_conf|card_info|card_state|svc_flag|spec_flag|

+--------+---------+---------+----------+--------+---------+ 0 DSVMB DSVMB NORM ON -

1 DSCMA DSCMA NORM ON -



4 DSDTA NEQ EJECT OFF CLEAR

5 NEQ NEQ NEQ OFF -

6 NEQ NEQ NEQ OFF -

7 NEQ NEQ NEQ OFF -

8 NEQ NEQ NEQ OFF -

9 NEQ NEQ NEQ OFF -








Check if the DSVMB has been already mounted on the same slot as that of the ucmcard command result.3) Check the emergent fault register(CASR) and the detailed fault status register (DASR) of the board.

RMOS_PP:1010>ucmalarm

RMOS_PP:1010>

Usage : ucmalarm type

type : c -> cmx, d -> dte, u -> usi, v ->vmh

RMOS_PP:1010> ucmalarm v

>

+---------+------+-----+-------+--------+----+-----+----+----+----+

| card_no | type | FUF | DOF(A)| DOF(B) | B4 | B3 | B2 | B1 | B0 |

+---------+------+-----+-------+--------+----+-----+----+----+----+

0 DSVMB X X X - - - - -

1 DSCMA X X X - - - - -

>

+--------+------+------+--------+--------+-----+-----+----+----+-----+

| card_no| type | PCLK | SHW(1) | SHW(2) | DGF | CPU | B2 | B1 | B0 |

+--------+------+------+--------+--------+-----+-----+----+----+-----+

0 DSVMB X X X X X - - -

1 DSCMA X X X X X - - - FUF : Indicates that the board has an internal fault. Demount and mount the board again.

DOF(A) : Check if the A port TD-Bus cable is still connected.

DOF(B) : Check if the B port TD-Bus cable is still connected.

PCLK : Indicates the state of the SHW PCM clock, which failed.

SHW(1) : Indicates the state of the PCM SHW cable open.

SHW(2) : This bit is set to logical low in the internal DSVMB.

DGF : Indicates whether or not the board state is normal by means of self-diagnosis. Demount and mount again the board.

CPU : Indicates the CPU status failure. Demount and check the appearance of the CPU chip.

The remaining bits are set to logical low in the internal DSVMB, so its values are 0.

8S7H Fault Handling

8.1S7H Introduction The S7H performs the signal processing function of the ITU-T common line signal mode in the SDX-MSC II. Each SSPHA of the S7H can process traffic of 0.2 Erlang per signal link in a normal state and can process traffic of 0.4 Erlang or more per signal link in an emergency state.

Visual Check1) SSPHA LED Check


2) SSPHA Strap Check


8.2Online Test Entries and Implementations P-BUS Loopback Test : When receiving the previously defined primitive(P-BUS Test) from the higher-level test block while the PBA is in-service, this function reports the result after transmitting/receiving a certain volume of messages to/from the P-BUS.

Local Signal Link Activation Test : With the PBA in-service, it makes the deactivated signal link within the PBA, being activated at the request of the high-level test block and informs the result.(It has an RA Loop as a variable within the test primitive.)

External Loop Test : To check if the interface with the TSL is normal, this function performs the Active/Non-active test and the Test Message Tx/Rx Test for each link in the state of being looped at the outside of the Line Driver/Receiver which is the termination point to the sub-highway.

Signal Terminal TEST : Execute the TEST-ST command.

NEW> TEST-ST:1,3,ST;

ACCEPTED

NEW>

+++ SLSTPM2 2000-01-03 08:57:01 FRI ON RPORT 03

M8311 TEST SIGNALLING TERMINAL

STG=1/ST=03/TYPE=ST

RESULT = OK

COMPLETED RA Loop TEST : Execute the TEST-ST command.NEW> TEST-ST:1,3,RA;

ACCEPTED

NEW>


M8311 TEST SIGNALLING TERMINAL

STG=1/ST=03/TYPE=RA

RESULT = OK

COMPLETED T-Switch Loop TEST : Execute the TEST-SLK-PATH command.

NEW> TEST-SLK-PATH:1,3,TSW;

ACCEPTED

NEW>


M8312 TEST SIGNALLING LINK PATH

STG=1/EN=03/TYPE=TSW TEST

RESULT = OK

COMPLETED


9DTI Fault Handling9.1IntroductionThe Digital Trunk Interface(DTI) block provides the function to interface with the counterpart station through trunk line.9.2Fault DiagnosisVisual Check1) CDTIA LED Check


Check by Debug PortConnect the 9-pin connector on the front of CDTIA with the COM port of the PC. (Connection conditions : 9600bps/8-1Stop Bit/Non Parity.)

1) When the CDTIA is switched on or restarted.

*************************************************

*

SDX-MSC II TRUNK BOAD (CDTIA)

*

(V1.0 By SEC)

*

Designed by S.W HAN

VOICE TEST LINK-01 O.K !




CDTIA>

*CDTIA ON LINE(HE For HELP!)

CDTIA>

This diagnostic test transmits Pseudo Random Test Data to 120 voice(information) time slots of 4 PCM links, reads the data returned by digital local loop from the E1 Framer, and compares this with the Tx test data. Then, it checks if the pertinent PCM link has a fault.

When SS command is entered at the prompt.CDTIA>SS

BOARD TYPE:TWISTE PAIR(COAXTIAL)

DP CLOCK:F(.)

LN: RA RM OF 16 OS AS LO CF CO

01: . . . . . .

02: . . . . . .

03: . . . . . .

04: . . . . . .

.:Normal

f:Fail

Remote Alarm(RA) : If the main station transmits low quality signal, the counterpart station transmits the frame signal whose remote alarm bit is activated to the main station. The main station detects this remote alarm bit and activates the remote alarm LED. The F/W informs the higher-level PP of this fact.

Receive Multi-frame Alarm(RM) : After checking the multi-frame synchronous signal, the counterpart station transmits the RM to the main station using the bit 5 allocated to the TS 16 of Frame #0, when the synchronous signal concerned is not normally received. Then, the main station detects the bit concerned and generates an alarm.(CCS Mode : Not use.)

Out of Frame Alignment(OF) : This alarm is activated when the Frame Alignment Signal Pattern from each PCM link continuously generates errors(3 ~ 4 times or more), or when the bit 2 of Non-frame Alignment Signal Pattern is continuously lost three times. 16(RX Timeslot 16 AIS) : This alarm is activated when the signaling mode of each link is CAS and the TS 16 value of all the frames is received as 1.(But, if the signaling mode is CCS, it does not exist.)

Out of Super Multi-frame(OS) : This alarm is activated when all the low-level 4 bits of the TS 16 of the Frame #0 are not received as 0. It is not used in the CCS mode. Alarm Indication Signal(AS) : This alarm is activated when all the 512 bits of each link data are received continuously as 1. Loss of Signal(LO) : This alarm is activated when the Rx data of each PCM link is 175 pieces of continuous Zero bits. Sub-Highway Clock Fail(CF) : This function detects the clock from the system, clock generated from the internal PLL and clock recovered on the PCM line. If these clocks do not exist, the function makes the clock-failed LED activate; the F/W analyzes the type of clock failure and informs the higher-level PP of the fact. Sub-Highway Cable Open(CO) : Makes the cable open LED activated when the sub-highway cable or the TD-BUS cable is open.

Offline TestWhen receiving the OF command in the Online Service, the CDTIA changes into an Offline test mode. Upon executing the TS command in the Offline test mode, select the test menu.

To change the Offline Test Mode into the Online Mode, use the GO 0 command.

CDTIA>OF

*OFF LINE DEBUG MODE

Z80_BUG>TS

---------------CDTIA TEST MENU----------------

A: ALL TEST

B: DIGITAL LOOP TEST

C: SUB HGH WAY LOOP TEST

Q: RETURN TO DEBUG

ALL TEST : Performs the Speech/Signaling Loop Test for all the links and then displays the result.

Speech Loop Test : Transmits the fixed data to the voice channels of all the links and compares Tx data and Rx data, then displays the result.

Signaling Loop Test : Transmits the fixed data to the signaling channels(TS 16) of all the links and compares the Tx data with the Rx data, then displays the result. Sub-Highway Loop Test : Transmits the fixed data to the SHW of all links and compares the Tx data with the Rx data, then displays the result.H/W CharacteristicsThe hardware characteristics of each link connected to the CDTIA are as follows :

Line speed : 2048 kbps 50 ppm

Line symbol : HDB3

Frame type : Basic Frame(CCS)/16 Multiframe(CAS)

The pulse mask test checks if the system satisfies the pulse standard recommended in the ITU-T as shown below. While performing the test, apply a test load resistance of 120 ohm to the tip of oscilloscope and the ground terminal, and then transmit an AIS pattern to the link to be tested.

10PRI Fault Handling10.1IntroductionThe Primary Subscriber Interface(PRI) block accommodates the primary group access(30B+D) function and Conference of European Postal and Telecommunications(CEPT) applies the line.

10.2PRI FunctionsThe PRI block is composed of the ISDN Primary rate CEPT Interface Assembly (IPCIA) board and ISDN D-Channel Control Processing Assembly(IDCPA) board. The IPCIA board processes the layer 1 and 2 Protocol, and IDCPA board performs the TSL, PPH interface, MUX/IMUX for packet data and IPCIA maintenance.ISDN D-Channel Control Processing Assembly(IDCPA)

TSL interface

B/D-channel extraction and synthesis D-channel packet information processing On-board power supply Packet interface Line concentration of 2:1~16:1

16 Highway single DLC control Change of DLC Gain and PCM Coding(A-Law/U-law)

F/W Downloading

ESD discharge pathISDN Primary rate CEPT Interface Assembly(IPCIA )

DS1 level(2.048 Mbps) primary group access(30B+D) 2 links(60B+2D) per board B/D-channel extraction and synthesis LAPD(Link Access Procedure on the D-Channel) processing E1 trunk interface and alarm processing & recovery On-board power supply Change of the DLC Gain and PCM Coding(A-Law/U-law)

F/W Downloading

10.3Fault DiagnosisDiagnostic procedureVisual Check1) IPBPA DIP Switch and Cable Check


2) IPCIA J2 Strap Check

Check if the IPCIA J2 Straps are all off.

3) IDCPA/IPCIA LED Check

Read the OSI of the SDX-MSC II and perform a visual check.Check the status using the MMC commands

Use the following commands to check the subscribers status :DIS-SLC-CONF

DIS-SLC-STS

DIS-LFLT-STS

DIS-LUUS-STS

DIS-LLO-STS


Test points Check1) IDCPA Signal Check

MCLK : 4 MHz

SCLKA : 2.5 MHz(5 MHz for TD-BUS 5 MHz operation)

SCLKA(P1,A11+,A12-), FSA(P1,B11+,A12-), RDYA(P1,A17+,A18-), MAD0A(P1,A13+,B13-), MAD1A(P1,A14+,B14-), MAD2A(P1,A15+,B15-), MAD3A(P1,A16+,B16-)

SC_CLK(P1,E9) : SC-BUS CLK(2 MHz) SC_FS(P1,E8) : SC-BUS Frame Sync.

LCLK(P1,A9) : LC-BUS CLK(3.4 MHz) LPFS(P1,A8) : LC-BUS Frame Sync.

2) IPCIA Signal Check

Check the Sub-Highway clock, SC-bus and LC-bus clock on the edge pin of the IPCIA, and determine if the following signals are generated :

Sub-Highway clock : MCLK(A11) & MFS(C11)

SC-BUS clock : SC-CLK(A20) & SC-FS(C20)

LC-BUS clock : LCLK(A27) & LFS(C27)

PP Interface Check

Subscriber disconnected when the test is run.

When the following PP Interface test is run in the offline test mode, the

subscriber gets disconnected during the test.

[STEP 1] Check of Registers

Connect the RS-232C cable to the communication port of the PP that controls the PRI block, and perform the following test :1) Make the PP offline.RMOSdebug

debug on

2) Enter the Control-C key.pbug>

3) When using the A port TD-bus of the PP, execute the following and make the A side active. Then, read data from the registers.pbug>ms 4000000 04000000;l

Effective Address : 04000000pbug>ms 5000003 7f:1;b

Effective Address : 05000003pbug>md 5000000;b05000000 : 80 xx xx xx 7f xx xx .....4) Compare the data from the register with the IDCPA PBA Description, and check if it is identical with the current settings.

[STEP 2] Check of LC-Bus

Connect the RS-232C cable to the communication port of the PP that controls the PRI block and execute the following commands to read the data from the DPRAM.

pbug>ms 4000000 44000000;l

Effective Address : 44000000

pbug>md 5004080;w

05004080 : ff00 ff00 2000 2000 ff00 ff00 ff00 2000 ff00 : Board demounted 2000 : IPCIA board mounted Other values : Abnormal working of LC-BusIf the DPRAM data is the same as the mounting location of the mounted IPCIA board at that moment, the LC-Bus and DC-Bus are deemed to be normal.[STEP 3] Check of SC-Bus Tx

Connect the RS-232C cable to the IDCPA and check the following command to see if any data exists.[IDCPAV1.0] psf

psf on

[IDCPAV1.0] prf

prf on

[IDCPAV1.0] data

data on[IDCPAV1.0] ipctest 100 10 500 10 0 0 0 0If Tx data exists, it means the SC-Bus Tx part is normal.

[STEP 4] Check of SC-Bus Rx

1) Connect the RS-232C cable to the IPCIA and execute the following command :[IDCPAV1.0] ipctest 10 500 102) Connect the RS-232C cable to the IDCPA and execute the following command to check whether or not data exists.[IDCPAV1.0]prf

prf on

[IDCPAV1.0]data

data on

If Rx data exists, it means the SC-Bus Rx part is normal. 11APC Fault Handling11.1IntroductionThe Alarm Panel Control(APC) block collects all kinds of alarms generated from the internal/external system and notifies the peripheral processor(PP) of them. Also, it receives visible and audible signals & alarms from the PP and controls the Remote Alarm Panel Unit(RAPUA).

The RAPUA indicates alarm and signal information received from the APC block in visible and audible form.

11.2APC FunctionsAlarm Panel Control Interface(APCIA) This collects 120 types of environmental alarms and 2 kinds of OMP Function Fail Alarms.

To perform the serial communication function(RS-232C) for 3 ports To perform the interface with the 3-unit RAPUA

To perform the PP interfaceRemote Alarm Panel Unit(RAPUA) To perform the serial communication(RS-232C) interface To implement the RS-422 and Rs-232C driver circuit To drive visible alarms To drive audible alarms To control the control switch11.3Fault DiagnosisDiagnostic procedureVisual Check1) Check the RCBPA DIP Switch and CableRead the OSI of the SDX-MSC II and perform a visual check.

2) Checksum and Version CheckCheck the checksum value and version of the APCIA/RAPUA and determine if these are the last values.

3) APCIA/RAPUALED Check



Use the following commands to check the APC block status :DIS-ADU

TEST-ADU


Check of PP Interface[STEP 1] Registers Check

Connect the RS-232C cable to the communication port of the PP that controls the APC block and execute the following commands below. Then, read the data from the registers that are used for communication between the PP and APC blocks ; then check if the PBA has a fault.

>prtu(enter)

>prtu on

>accessdev port mode offset r|w data

Port(0~3) : A~D port

Mode(0~7) : MODE 0~7

OffsetA23~A20A19~A16A15~A12A11~A8A7~A4A3~A0

Slot IDAddress

Slot ID : 00H=APCIA(A), 10H=APCIA(B) R|W : Read or Write

Data : Data to write

A

AISAlarm Indication Signal

APCAlarm Panel Control Block

APCIAAlarm Panel Control Interface Assembly

ASCRAccess Switching Control Rack

ASPAccess Switching Processor

ASPPAccess Switching Peripheral Processor

ASSAccess Switching Subsystem

ASS-CAccess Switching Subsystem Complex

ASS-PAccess Switching Subsystem Primary Rate Interface

ASS-W/TAccess Switching Subsystem Wireless subscriber/Trunk

B

BERBit Error Rate

C

CALIACompact Analog Line Interface Assembly

CCIRCentral Control Interface RackCCSCentral Control Subsystem

CDMACode Division Multiple Access

CDTIACEPT Digital Trunk Interface board Assembly

CDPIAClock Distribution & Processor Interface Assembly

CIBPACommunication Interworking Back Panel Assembly

CIMCharge Interface Management Block

CINControl Interworking on Node

CINRCommunication Interface Node Rack

CINIAControl Interworking Node Interface Assembly

CINMACommunication Interworking Node Maintenance Assembly

CIPControl Interworking Processor

CTRIACentral Optic Transfer & Receiver Interface AssemblyD

DCI

Digital CEPT Interface Block

DKU

Disk Unit

DPRAM

Dual Port RAM

DSC

Digital Service Controller

DSBPA

Digital Service circuit Back Panel Assembly

DSCMA

Digital Service circuit for Call Mixer Assembly

DSDTA

Digital Service circuit for Digital trunk Test Assembly

DSMSA

Digital Service circuit for Multi-frequency Signaling Assembly

DSVMB

Digital Service circuit for Voice Message Assembly

DTI

Digital Trunk/T1 Interface Block

DTMF

Dual Tone Multi-Frequency

EENIP

Ether Network and X.25 Interface Processor

FFPBPA

Frame relay & Packet protocol Back Panel Assembly

FPHCA

Frame relay & Packet protocol Handling Controller Assembly

FPRCA

Frame relay & Packet protocol Routing Controller Assembly

FS

Frame Synchronization

HHDD

Hard Disk Drive

HW

Highway

IIBG

Inter Block Gap

IDCPA

ISDN D-channel Control Processor Advanced

INP

Interconnection Network Processor

INPP

Interconnection Network Peritheral Processor

INS

Interconnection Network Subsystem

IPBPA

ISDN Primary Subscriber Back Panel Assembly

IPC

Interprocessor Communication

IPCIA

ISDN Primary Subscriber CEPT Interface type A

LLRP

Location Registration Processor

LRS

Location Registration Subsystem

LTRIA

Local optic Transceiver Interface Assembly

MMPBPA

Main Processor Back Panel type A

MPBPB

Main Processor Back Panel type B

MPDMA

Main Processor Duplication Manager Assembly

MSBIA

Main processor SCSI Bus Interface Assembly

MSC

Mobile Switching Center

MVQTA

Mobile Voice Quality Test AssemblyNNES

Network Synchronization Block

NSBPA

Network Synchronization Back Panel Assembly

NSCGA

Network Synchronization Clock Generation Assembly

NSCMA

Network Synchronization Clock Maintenance Assembly

OO&M

Operation and Maintenance

OMBPA

OMP Back Panel Assembly

OMP

Operation & Maintenance Processor

P

PBA

Printed Circuit Board Assembly

PCM

Pulse Code Modulation

PP

Peripheral Processor

PPH

Peripheral Processor Hardware Block

PSTN

Public Switched Telephone Network

R

R2MFC

R2 Multi-Frequency Compelled

RCBPA

Remote Control Back Panel AssemblyRG

Ring Generator Block

RSGUA

Ring Signal Generator Unit Assembly

SSCCIA

Subscriber Circuit Control Interface Assembly

SHW

Subhighway

SIBPA

Subscriber Interface Back Panel Assembly

SLIR

Subscriber Line Interface Rack

SMDXA

Sub-highway Multiplex & Demultiplex Assembly

SPBPA

Signaling System No.7 Protocol Handler Back Panel Assembly

SSBPA

Space Switch Back Panel AssemblySSL

Space Switch & Link Block

SSNo.7

Signaling System No.7

SSMXA

Space Switch Matrix Assembly

SSPHA

Signaling System No.7 Handler Assembly

SSW

Space Switch Block

SSWR

Space Switch Rack

TTBSEL

TD-Bus Selection

TD-Bus

Telephony Device Control Bus

TDCMA

Telephony Device Control Master Assembly

TSBPA

Time Switch Back Panel Assembly

TSCMA

Time Switch Control & Maintenance Assembly

TSL

Time Switch & Link

TSW

Time Switch Block

VVLR

Visitor Location Register

COPYRIGHT

This manual is proprietary to SAMSUNG Electronics Co.Ltd. and is protected by copyright. No information contained herein may be copied, translated, transcribed or duplicated for any commercial purposes or disclosed to third parties in any form without the prior written consent of SAMSUNG Electronics Co.Ltd.

TRADEMARKS

SAMSUNG, are registered trademark of SAMSUNG.

SDX-MSC II is registered trademark of SAMSUNG.

Product names mentioned in this document may be trademarks and/or registered trademarks of its respective companies.

Product names mentioned in this document may be trademarks and/or registered trademarks of their respective companies.

Disclaimer

This manual should be read before the installation and operation, and the operator should correctly install and operate the systemproduct by using this manual.

This manual may be changed for the system improvement, standardization and other technical reasons without prior notice.

For further information on the updated manual or have a question the content of manual, contact Document Center at the address below .

Address : 442-370742 Document Center 2th Fl. IT Center. 416 Metan-3dong Paldal-gu, Suwon-si, Gyeonggi-do, Korea

e-mail : [email protected]

Or contact Call Center at the telephone below if you have any questions or concerns regarding the operation of your systemequipment.

Phone : 81-1588-4141

http://www.samsungnetwork.com

This manual should be read before the installation and operation, and the operator should correctly install and operate the product by using this manual.

Disclaimer

This manual may be changed for the system improvement, standardization and other technical reasons without prior notice.

For further information on the updated manual or have a question the content of manual, contact Document Center at the address below .

Address : 442-370 Document Center 2th Fl. IT Center. 416 Metan-dong Paldal-ku, Suwoon-si, Kyungki-do, Korea

e-mail : [email protected]

Or contact Call Center at the telephone below if you have any questions or concerns regarding the operation of your equipment.

Phone : 81-1588-4141


2002 SAMSUNG Electronics Co., Ltd. All rights reserved.

MANUAL TITLESDX-MSC II

PART I. PART TITLEOperation and Maintenance Manual (MTM)

2002 Samsung Electronics Co., Ltd.

All rights reserved.

Information in this document is proprietary to SAMSUNG Electronics Co., Ltd

No information contained here may be copied, translated, transcribed or duplicated by any form without the prior written consent of SAMSUNG.

Information in this document is subject to change without notice.

Visit us at


SDX-MSC II

Operations and Maintenance

Manual (MTM)

10. 2002.

2001

This page intentionally left blank

Caution

End

Result

Check the Node status.

Result

Check the Node fault.

Detect the reason of occurrence.



Check the CIN status.

OK

OK

OK

OK

NOT OK

NOT OK

NOT OK

Result

Start

Normal

Find out the reason.


Normal

Check the test point.

Check the MMC command stateus.

Check the MPDMA Board LED state.

&

Check the MPDMA Cable connection.

End

Normal

Start


Y

N

Y

N

Y

N

Y

Y

Y

N

N

N




Check the MMC command status.

N Normal

N Normal

N Normal

Check the test points.

Check the LEDs of the MPDMA and MSBIA board.

Check the LEDs of the DKU and RDKU.

Check the SCSI cable connection and the ID Setting.

End

S Start

Y

Y

Y

N

N

N




Check the MMC command status.

N Normal

N Normal

N Normal

Check the test points.

Check the LEDs of the MPDMA and MSBIA board.

Check the LEDs of the DKU and RDKU.

Check the SCSI cable connection and the ID Setting.Check the LED of the TDCMA board.

Check the status of the TMBPA/MPBPA DIP switch

and cable connection

End

S Start

Y

Y

Y

N

N

N




Check the MMC command s

Documents

SDX-MSC II MTM