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SDI/ISTC Seminar Adam Lake GPGPU, Intel Adam Lake is a member of Intel’s GPGPU architecture team. He represented Intel for OpenCL 1.2 and 2.0 and was instrumental in the design of features includ- ing shared virtual memory, device side enqueue, improving the execution and memory models, and driving support for an intermediate repre- sentation. He was a Sr. Software Architect on Larrabee, (now Xeon Phi), and has over 40 pat- ents or patents pending. Adam worked previ- ously in non-photorealistic rendering and the design of stream programming systems which included the implementation of simulators, assemblers, and compilers. He did his under- graduate work at U. Evansville, his grad studies at UNC Chapel Hill, and spent time at Los Alamos National Laboratory. He has been a co-author on numerous peer reviewed publications in the field of computer graphics, and was the editor of Game Programming Gems 8. The Compute Architecture and Software Ecosystem of Intel Processor Graphics Discrete GPUs provide massive parallelism to support today’s most interesting high throughput workloads such as deep learning, computational finance, and visual analytics. Intel is making strides in increasing the capability of the GPU on the SoC to support these workloads and there are cases where an integrated GPU can be a compelling solution with a lower total cost of ownership for GPGPU computing. In this talk we will go into the architectural details of the GPGPU Architecture of Intel Processor Graphics and address the question: How do I program the full teraflop GPU integrated with my CPU? Wednesday, March 29, 2017 RMCIC 4th Floor Panther Hollow Room 10:00 - 11:30 am PLEASE NOTE SPECIAL DAY AND TIME VISITOR HOST: Michael Kozuch For more information or questions: Karen Lindenfelser, 8-6716, [email protected] http://www.pdl.cmu.edu/SDI/ Girish Ravunnikutty GPGPU, Intel Girish Ravunnikutty is a member of GPGPU architec- ture team at Intel. During his career at Intel, Girish’s major focus has been GPU compute performance analysis and path finding features for future GPU architectures. His analysis and optimizations efforts led to multiple software design wins for Intel Graphics. Girish archi- tected the first OpenCL performance analysis tool from Intel. Before joining Intel, Girish worked with Magma Design Automation and IBM labs. He did his Master’s specializing in GPU Compute at University of Florida, Gainesville, and he worked with Oakridge National Laboratories accelerating Particle in cell algorithm on GPU’s.

SDI/ISTC Seminar · 2017-03-22 · SDI/ISTC Seminar Adam Lake GPGPU, Intel Adam Lake is a member of Intel’s GPGPU architecture team. He represented Intel for OpenCL 1.2 and 2.0

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Page 1: SDI/ISTC Seminar · 2017-03-22 · SDI/ISTC Seminar Adam Lake GPGPU, Intel Adam Lake is a member of Intel’s GPGPU architecture team. He represented Intel for OpenCL 1.2 and 2.0

SDI/ISTC Seminar

Adam LakeGPGPU, Intel

Adam Lake is a member of Intel’s GPGPU architecture team. He represented Intel

for OpenCL 1.2 and 2.0 and was instrumental in the

design of features includ-ing shared virtual memory, device side enqueue,

improving the execution and memory models, and driving support for an intermediate repre-

sentation. He was a Sr. Software Architect on Larrabee, (now Xeon Phi), and has over 40 pat-ents or patents pending. Adam worked previ-ously in non-photorealistic rendering and the

design of stream programming systems which included the implementation of simulators,

assemblers, and compilers. He did his under-graduate work at U. Evansville, his grad studies at

UNC Chapel Hill, and spent time at Los Alamos National Laboratory. He has been a co-author on

numerous peer reviewed publications in the field of computer graphics, and was the editor of

Game Programming Gems 8.

The Compute Architecture and Software Ecosystem ofIntel Processor Graphics

Discrete GPUs provide massive parallelism to support today’s most interesting high throughput workloads such as deep learning, computational finance, and visual analytics. Intel is making strides in increasing the capability of the GPU on the SoC to support these workloads and there are cases where an integrated GPU can be a compelling solution with a lower total cost of ownership for GPGPU computing. In this talk we will go into the architectural details of the GPGPU Architecture of Intel Processor Graphics and address the question: How do I program the full teraflop GPU integrated with my CPU?

Wednesday, March 29, 2017RMCIC 4th Floor Panther Hollow Room

10:00 - 11:30 amPLEASE NOTE SPECIAL DAY AND TIME

VISITOR HOST: Michael KozuchFor more information or questions:

Karen Lindenfelser, 8-6716, [email protected]://www.pdl.cmu.edu/SDI/

Girish RavunnikuttyGPGPU, Intel

Girish Ravunnikutty is a member of GPGPU architec-ture team at Intel. During his career at Intel, Girish’s major focus has been GPU compute performance analysis and path finding features for future GPU architectures. His analysis and optimizations efforts led to multiple software design wins for Intel Graphics. Girish archi-tected the first OpenCL performance analysis tool from Intel. Before joining Intel, Girish worked with Magma Design Automation and IBM labs. He did his Master’s specializing in GPU Compute at University of Florida, Gainesville, and he worked with Oakridge National Laboratories accelerating Particle in cell algorithm on GPU’s.