SCIPP R&D on the International Linear Collider Detector

SCIPP ReviewNovember 29, 2005

Presenter: Bruce Schumm

R&D Activity is increasing, with studies now on four fronts:

Physics and machine studies for e-e- running

Detector resolution standards from physics simulation

Reconstruction capabilities of all-silicon tracking

Hardware proof-of-principle of low-mass silicon tracking

Current involvements (all very much part time)

3 senior physicists, 1 post-doc (looking for a second), 4 undergraduate thesis students, 1 Engineer, 2 technical staff, one bored spouse of a Silicon Valley engineer.

International Linear Collider: Activity on the e-e- Front

Clem Heusch is the SCIPP participant in e-e- studies

• Leading international effort in the use and application of e-e- beams at the ILC

• Continuing series of workshops hosted by SCIPP; proceedings published in World Scientific

• Heusch is a member of ILC Subcommittee on International Collaboration.

Detector Resolution Standards from Selectron Production

Participants:

Senior Physicist

Bruce Schumm

Undergraduate Thesis Students

Sharon Gerbode, Heath Holguin, Troy Lau*, Paul Moser, Adam Perlstein, Joseph Rose, Matthew Vegas

Community Member (on hold before Grad School)

Ayelet Lorberbaum

*Recipient of two Undergraduate Research Awards; grad school at U. Michigan.

Original Motivation

To explore the effects of limited detector resolution on our ability to measure SUSY parameters in the forward (|

cos()| > .8) region.

SiD Tracker

selectrons

LSP

SPS 1 Spectroscopy:

At Ecm = 1Tev, selectrons and neutralino are

light.

Beam/Brehm:√smin=1 √smax=1000 = .29sz = .11 (mm)

Energy Distribution

0

50

100

150

200

250

300

350

400

450

0 7 14

22

29

36

43

50

58

65

72

79

86

94

101

108

115

122

130

137

144

151

158

166

173

180

187

194

202

209

216

223

230

238

245

252

259

266

274

281

288

Energy GeV

Co

un

ts

• sample electron energy distribution Mselectron = 143.112 (SPS1A)

Lower Endpoint

Upper Endpoint

Electron energy distributionwith beam/bremm/ISR (.16%). No detector effects or beam energy spread.

-0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.91,000

2,000

3,000

4,000

5,000

6,000

7,000

8,000

9,000

10,000

11,000

12,000

13,000

14,000

15,000

16,000

SUSY: Particle cos(theta) (no cuts)

SPS1A at 1 TeVSelectrons vs. cos()

Electrons vs. cos()

Roughly ½ of statistics above |cos()| of 0.8,

but…

The spectrum is weighted towards higher energy at high |cos()|, so there’s more information in the forward region than one might expect.

Error for COSTHETA Ranges

0.0380.046

0.086

0.0730.078

0.194

0.080

0.0900.097

0.1060.111

0.200

0.000

0.050

0.100

0.150

0.200

0.250

-0.01% 0.19% 0.39% 0.59% 0.79% 0.99% 1.19%Beamspread

Err

or

PERFECT 0-1

PERFECT 0-.8

SDMAR01 0-1

SDMAR01 0-.8

Determine the selectron mass accuracy in both the central (0 < |cos| < 1) and full (0 < |cos| < 1) region

Ongoing work:

Fitting simulaneously for selectron and gaugino (0) masses at Ecm = 500 GeV

This is an ILC Physics benchmark process

(Lorberbaum, Schumm, Vegas)

Simulation of SiD Tracking System (and SiD variants)

Participants:

Senior Physicist

Bruce Schumm

Recent Graduate Students

Christian Flacco, Michael Young*

Undergraduate Thesis Student

Eric Wallace

*Supported primarily through department (TA) funds; SLAC paid for ½ of his support this summer.

Three areas of work:

Fast MC Simulation

Billior-based LCDTRK.f (B. Schumm) provides covariance matrices for fast MC simulation and resolution plots.

Pulse Development Simulation

Provides simulation of pulse development and amplification. Will soon be incorporated in international simulation framework (awaiting “hook” from Norman Graf at SLAC)

SiD Tracking Capabilities

Explore tracking performance of SiD tracker and variants

Simulation of SiD Tracking System, continued

LCDTRK.f comparison of SiD options with TESLA (LDC) design, from Snowmass 2005

Pulse Development SimulationLong Shaping-Time Limit: strip sees signal if and only if hole is col- lected onto strip (no electrostatic coupling to neighboring strips)Charge Deposition: Landau distribution (SSSimSide; Gerry Lynch LBNL) in ~20 independent layers through thickness of deviceGeometry: Variable strip pitch, sensor thickness, orientation (2 dimen-sions) and track impact parameter

Lorentz Angle: 18 mrad per Tesla (holes), from measurements

Carrier Diffusion

)(21

exp),(0

2

ttDr

trPq

Hole diffusion distribution given by

Offest t0 reflects instantaneous expansion of hole clouddue to space-charge repulsion. Diffusion constant given by

hq qkT

D

Reference: E. Belau et al., NIM 214, p253 (1983)

sec65.00 nt

h = hole mobility

Result: S/N for 167cm Ladder

Electronics SimulationDetector Noise:

From SPICE simulation, normalized to bench tests with GLAST electronicsAnalog Measurement:

Employs time-over-threshold with variable clock speed; lookup table provides conversions back into analog pulse height (as for actual data)

RMS

Gaussian Fit

Detector Resolution (units of 10m)Essential tool for design of front-end ASIC

Non-normal incidence

Also need to understand performance as a function of various parameters, e.g., angle at entrance to the detector (identify issues for test-beam running)

Pattern Recognition Capabilities of an All-Silicon Central Tracker

Can one do pattern recognition with only five central tracking layers?

Might more layers improve performance to an extent that justifies the extra material?

SiD Tracker

Current code: Nick Sinev, U. Oregon

EVENT/TRACK SELECTION

Choose qqbar events at Ecm= 500 GeV (dense jet cores); Pan/Pythia and GEANT4 generation

Choose events/tracks that should be easily recon-structed (tracks curl up below p= 1 GeV):

Event Selection

|costhrust| < 0.5

Thrust Mag > 0.94

Track Selection

|costrack| < 0.5

p > 5 GeV/c

EFFICIENCIES FOR QQBAR EVENTS

Doesn’t look that spectacular; what might be going on here?

Of course! The requirement of a VXD stub means that you miss anything that originates beyond r ~ 3cm. This

is about 5% of all tracks.

With VXDBasedReco, we won’t see a difference between 5 and 8 layer tracking.

BAD TRACK FITS AND EFFICIENCY

TRACK PARAMETER PERFORMANCE

1. Compare width of Gaussian fit to residuals with two different estimates:

• Error from square root of appropriate diagonal error matrix element

• Error from Billior calculation (LCDTRK program)

2. Only tracks with all DOF (5 VTX and 5 CT layers) are considered.

3. Only gaussian smearing is used, since this is what is assumed for the two estimators.

Qqbar sample extends out to ~100 GeV; use +- sample to get higher energy (200-250 GeV) bin.

CURVATURE ERROR vs. CURVATURE

Standard (Original) Code

CURVATURE ERROR vs. CURVATURE

“NEW” CODE WITH MODIFIED FITTER

RESULTS FOR (LOWEST BIN)

Residuals (Gaussian smear): = 3.40x10-7

Error Matrix: = 3.12x10-7

LCDTRK: = 3.26x10-7

Actual momentum resolution is about 9% worse than LCDTRK expectation

Residuals (realistic CCD): = 3.29x10-7

Apparently, “realistic” CCD resolution is better than assumed value of 5m

Getting close to ramped-up again with senior thesis student Eric Wallace.

Port our code into new simulation framework (making forward progress!)

Incorporate realistic pulse-development simulation (reconstruction efficiency in jet core) when ready

Validate “ported” version of code.

Combine with new stand-alone central tracker code (Tim Nelson, SLAC) and optimize.

Explore different tracker configurations (8 layers).

Simulation Study Goals

Faculty/Senior

Alex GrilloHartmut Sadrozinski

Bruce SchummAbe Seiden

Post-Docs

[Gavin Nesom*]Jurgen

Kroseberg

Students

Michael YoungKunal Arya

(Com-puter Eng.

The SCIPP/UCSC ILC HARDWARE GROUP

Lead Engineer: Ned Spencer

Technical Staff: Max Wilder, Forest Martinez-McKinney

*Recently lured away by the sirens of Silicon Valley

The Gossamer Tracker

Ideas:• Low noise readout Long ladders substantially limit electronics readout and support (alternatively, improved res-olution for shorter ladders)• Thin inner detector layers• Exploit duty cycle eliminate need for active cooling Competitive with gaseous

track-ing over full range of momentaAlso: forward region…

THE LSTFE-2 CHIP

Long shaping-time front end suppresses 1/f noise, allowing for long-ladder readout

Power cycling should reduce IR heating by close to x100

Analog measurement via time-over-threshold (TOT) from low-threshold “readout” comparator.

Redesigned relative to LSTFE-1 to accommodate long pulse train and exploit more relaxed (5 Hz) duty cycle.

Submitted to TSMC 0.25m mixed-signal RF process; received August 11 (5 weeks late)

3 s shaping time; analog readout it Time-Over-Thres-hold with 400 nsec clock

1/4 mip

1 mip

128 mip

Operating point threshold

Readout threshold

RMS

Gaussian Fit

Efficiency and Occupancy as a function of high threshold

Resolution as a function of low threshold

SIMULATED PERFORMANCE FOR 167cm LADDER

1 mip

Expected analog gain of 140 mV/fC confirmed

Transition to log-arithmic response (TOT) at ~ 1.5 mip

INITIAL RESULTS

DIGITAL ARCHITECTURE: FPGADEVELOPMENT

Digital logic should perform basic zero suppression (intrinsic data rate for entire tracker would be approximately 50 GHz), but must retain nearest-neighbor information for accurate centroid.

Status of Back-End Architecture Development

• First-pass digital strategy worked out

• FPGA code developed for 8-channel system

• Simulated data stream (including noise and detector background) injected and processed in simulation

• Data rates estimated

FIF

O (L

eadin

g and

trailin

g transition

s)Low Comparator Leading-Edge-Enable Domain

Li

Hi

Hi+4

Hi+1

Hi+2

Hi+3

Hi+5

Hi+6

Li+1

Li+2

Li+3

Li+4

Li+5

Li+6

Proposed LSTFE Back-End Architecture

Clock Period = 400 nsec

EventTime

8:1 Multi-

plexing (clock = 50 ns)

Master F

IFO

Per 128 Channel Chip:

1 Master FIFO reads out 32 local

FIFO’s

Store in Master FIFO essentially

complete by end of ~1ms beam spill

Controller

FIFO

FIFO

FIFO

FIFO

FIFO

FIFO

Proposed LSTFE Back-End Architecture (cont’d)

DIGITAL ARCHITECTURE VERIFICATION

ModelSim package permits realistic simulation of FPGA code (for now, up to signal propagation delay)

Simulate detector background and noise rates for 500 GeV running, as a function of read-out threshold.

Per 128 channel chip ~ 7 kbit per spill 35 kbit/second

For entire long shaping-time tracker ~ 0.5 GHz data rate (x100 data rate suppression)

NominalReadoutThreshold

LONG LADDER CONSTRUCTION

SUMMARY

Progress on key fronts:

• Front-end electronics developmentLSTFE-2 chip (cold-rf optimization) designed and testing underway

• Digital architectureProposed back-end architecture developed and verified; raw data rates acceptable (0.5 GHz)

• Ladder construction underway

Substantial work remains in all these areas; working towards testbeam run in late 2006