21
Scheduler-based Defenses against Cross- VM Side-channels Venkat(anathan) Varadarajan, Thomas Ristenpart, and Michael Swift 1 DEPARTMENT OF COMPUTER SCIENCES

Scheduler-based Defenses against Cross-VM Side- channels Venkat(anathan) Varadarajan, Thomas Ristenpart, and Michael Swift 1 D EPARTMENT OF C OMPUTER S

Embed Size (px)

Citation preview

Page 1: Scheduler-based Defenses against Cross-VM Side- channels Venkat(anathan) Varadarajan, Thomas Ristenpart, and Michael Swift 1 D EPARTMENT OF C OMPUTER S

1

Scheduler-based Defenses against Cross-VM Side-

channels

Venkat(anathan) Varadarajan,Thomas Ristenpart,

and Michael Swift

DEPARTMENT OF COMPUTER SCIENCES

Page 2: Scheduler-based Defenses against Cross-VM Side- channels Venkat(anathan) Varadarajan, Thomas Ristenpart, and Michael Swift 1 D EPARTMENT OF C OMPUTER S

2

VM M

Public Clouds (EC2, Azure, Rackspace, …)

Interface

VM

Multi-tenancyDifferent customers’ virtual machines (VMs) share same server

VM

VM

VM M

VM M

VMVM M

VM

VM M

VM

VM

VM

Benefits:1. High resource utilization, 2. Low service cost

VM

Page 3: Scheduler-based Defenses against Cross-VM Side- channels Venkat(anathan) Varadarajan, Thomas Ristenpart, and Michael Swift 1 D EPARTMENT OF C OMPUTER S

3

CorePrivate Caches

Branch Predictor

Shared Resources and Isolation

VM(m-VCPUs)

Hypervisor

CorePrivate Caches

Branch Predictor

VM(m-VCPUs)

VM(m-VCPUs)

VM(m-VCPUs)

VM(m-VCPUs)

VM(m-VCPUs)

System shared resources (LLC, memory, disk, n/w etc.)

via per-core sharing [Zhang et al’12, Ristenpart al’09]

via system-level sharing [Yarom & Falkner’14, Varadarajan et al’12]

CorePrivate Caches

Branch Predictor

Page 4: Scheduler-based Defenses against Cross-VM Side- channels Venkat(anathan) Varadarajan, Thomas Ristenpart, and Michael Swift 1 D EPARTMENT OF C OMPUTER S

4

Problem: Cache-based Side-channels*

VM

VM

Time

Core: A V

cache sets

cache ways

Prime

A

Probe

Attacker Timing Profile

Extract secret information

CRYPTO_FUNCTION(s):s secret bit

if (s = 0) { OPERATION_A}if (s = 1) { OPERATION_B}

Secret

*Zhang, Juels, Reiter, Ristenpart, “Cross-VM Side-channels …”, CCS’12

I-cache

Page 5: Scheduler-based Defenses against Cross-VM Side- channels Venkat(anathan) Varadarajan, Thomas Ristenpart, and Michael Swift 1 D EPARTMENT OF C OMPUTER S

5

Requirements for Successful Side-channel

VM

VM

Time

Core: A V

cache sets

cache ways

Prime

A

Probe

Attacker Timing Profile

Extract secret information

CRYPTO_FUNCTION(s):s secret bit

if (s = 0) { OPERATION_A}if (s = 1) { OPERATION_B}

Secret

*Zhang, Juels, Reiter, Ristenpart, “Cross-VM Side-channels …”, CCS’12

I-cachequick preemption

shared resource

high-precision timer

Page 6: Scheduler-based Defenses against Cross-VM Side- channels Venkat(anathan) Varadarajan, Thomas Ristenpart, and Michael Swift 1 D EPARTMENT OF C OMPUTER S

6

Defenses against Side-channels1. Sharing

– Resource Partitioning [NoHype’10]

– Specialized Hardware [RPcache’07]

– Software-based partitioning [StealthMem’12]

2. Access to high-resolution timers– Reduce resolution [TimeWarp’12]

– Removing timing channel [StopWatch’13]

3. Quick cross-VM preemptions– No prior work!

No countermeasures deployed by providers!

Page 7: Scheduler-based Defenses against Cross-VM Side- channels Venkat(anathan) Varadarajan, Thomas Ristenpart, and Michael Swift 1 D EPARTMENT OF C OMPUTER S

7

Our Solution: Soft Isolation

Allow sharing but limit frequency of dangerous VM interactions

Goals: 1. Secure: Controlled information leakage

2. Commodity: Easy to adopt

3. Efficient: Allow sharing, low overhead

… with simple changes to Hypervisor’s CPU scheduler

Core

(per core state)

Private Caches

VM

VM

Hypervisor

Page 8: Scheduler-based Defenses against Cross-VM Side- channels Venkat(anathan) Varadarajan, Thomas Ristenpart, and Michael Swift 1 D EPARTMENT OF C OMPUTER S

8

Rest of the talk …

1. Background: Quick Preemptions & Schedulers

2. Soft-Isolation: Scheduler-based defense

3. Evaluation: Security and Performance

Page 9: Scheduler-based Defenses against Cross-VM Side- channels Venkat(anathan) Varadarajan, Thomas Ristenpart, and Michael Swift 1 D EPARTMENT OF C OMPUTER S

9

Requirement for Quick Preemptions

VM

VM

V

Time

Core: A

cache sets

Prime

A

Probe

cache ways

Preemption Interval

V V

Rate of preemption > Rate of event to measure

CRYPTO_FUNCTION(s):s secret bit

if (s = 0) { OPERATION_A}if (s = 1) { OPERATION_B}

Next subsequent code/taskexecution … (or noise)

Page 10: Scheduler-based Defenses against Cross-VM Side- channels Venkat(anathan) Varadarajan, Thomas Ristenpart, and Michael Swift 1 D EPARTMENT OF C OMPUTER S

10

Why do schedulers allow quick preemptions?

Prime-probe attacker:Abuses BOOST priority, using interrupts.

Throughput-oriented:Benefits from longer scheduler timeslices

Latency-oriented:Benefits from quick wakeups , BOOST priority

State-of-art CPU schedulers

V

Time

Core: A V A

< 10µs

Batch VMs Interactive VMs

Malicious VM

Page 11: Scheduler-based Defenses against Cross-VM Side- channels Venkat(anathan) Varadarajan, Thomas Ristenpart, and Michael Swift 1 D EPARTMENT OF C OMPUTER S

11

V

Time

AA

Min. runtime(scheduler parameter)

Interrupt(boosted)

V V

Soft-Isolation: Ratelimit Preemptions

VM

VM

Core:

Available in Xen (and KVM)• ratelimit_us (and sched_min_granularity_ns)• Reduces VM-switches Boosts batch-workload’s performance

Minimum RunTime (MRT) guarantee soft-isolation

Page 12: Scheduler-based Defenses against Cross-VM Side- channels Venkat(anathan) Varadarajan, Thomas Ristenpart, and Michael Swift 1 D EPARTMENT OF C OMPUTER S

12

MRT Guarantee and Open Questions

TimeCore: AV V

1. Can MRT defend against Cross-VM Side-channels?(security evaluation)

delay

2. Trade-off between securityand performance?(performance overhead)

MRT value

Page 13: Scheduler-based Defenses against Cross-VM Side- channels Venkat(anathan) Varadarajan, Thomas Ristenpart, and Michael Swift 1 D EPARTMENT OF C OMPUTER S

13

Xen Version 4.2.1

Scheduler Credit Scheduler 1Configuration

(Non-work conserving)40% cap on DomU VCPUs

with equal weight# VMs 6

# VCPUs per VM 2

Experimental Methodology

Two VMs:1. Attacker2. Victim

Machine Intel Xeon E5645, 2.4GHz, 6 cores, single package

Memory Hierarchy

Private 32KB L1 (I- and D-Cache), 256KB unified L2, 12MB shared L3 & 16GB

DDR3 RAM.

Machine ConfigurationXen Configuration

Core

VM

VM

Hypervisor

Setting similar to public clouds (e.g. EC2)

Page 14: Scheduler-based Defenses against Cross-VM Side- channels Venkat(anathan) Varadarajan, Thomas Ristenpart, and Michael Swift 1 D EPARTMENT OF C OMPUTER S

14

Security Evaluation : Prime-Probe Timing Profile

Idle Victim VM Simple Victim VM Under Zero-MRT

Alternating usage patterni-cache access timing

Page 15: Scheduler-based Defenses against Cross-VM Side- channels Venkat(anathan) Varadarajan, Thomas Ristenpart, and Michael Swift 1 D EPARTMENT OF C OMPUTER S

15

Security Evaluation : Prime-Probe Timing Profile

Simple Victim VM Under Zero-MRT

Simple Victim VM Under 1ms MRT

Side-channel not discernible Alternating usage pattern

Page 16: Scheduler-based Defenses against Cross-VM Side- channels Venkat(anathan) Varadarajan, Thomas Ristenpart, and Michael Swift 1 D EPARTMENT OF C OMPUTER S

16

Security Evaluation: ElGamal Victim

0 0.1 0.5 1 2 5 100

100

200

300

400

500

600

700

800

0 4 3268

155

386

728

Minimum number of iterations per preemption

Xen MRT (ms)

Avg: 0.096 ops

SQUAREMULT(x, e, N):Let en , ..., e1 be the bits of ey ← 1for i = n down to 1 do y ← SQUARE(y) y ← MODREDUCE(y, N) if ei = 1 then y ← MULT(y, x) y ← MODREDUCE(y, N) end ifend forreturn y

ElGamal Side-channel require multiple preemptions within single iteration for noise-reduction [Zhang et al’12]

Page 17: Scheduler-based Defenses against Cross-VM Side- channels Venkat(anathan) Varadarajan, Thomas Ristenpart, and Michael Swift 1 D EPARTMENT OF C OMPUTER S

17

MRT Guarantee and Open Questions

TimeCore: AV V

1. Can MRT defend against Cross-VM Side-channels?(security evaluation)

delay

2. Trade-off between securityand performance?(performance overhead)

Page 18: Scheduler-based Defenses against Cross-VM Side- channels Venkat(anathan) Varadarajan, Thomas Ristenpart, and Michael Swift 1 D EPARTMENT OF C OMPUTER S

18

Performance Evaluation:Overall System Performance

CoreCore

Core Core

VCPU

VCPU

VCPUVCPU

VCPU VCPU

Hypervisor

workload-mixMeasured workload:1. Interactive memcached,

cassandra, etc. and2. Batch graph500, specJBB, etc.

Competing workloads:microbenchmarks highly cache-thrashing + (interactive or batch)

Page 19: Scheduler-based Defenses against Cross-VM Side- channels Venkat(anathan) Varadarajan, Thomas Ristenpart, and Michael Swift 1 D EPARTMENT OF C OMPUTER S

19

Performance Evaluation:Overall System Performance

ping

memcach

ed

cassa

ndra mcf

specjb

b

graph500

00.20.40.60.8

11.21.41.61.8

2

All-Batch All-InteractiveInteractive-Batch Idle

Nor

mal

ized

to Z

ero-

MRT

Avg. 95th Percentile Latency(interactive workloads)

Avg. Runtime (batch workloads)

At 5ms MRT< 7% overhead

Page 20: Scheduler-based Defenses against Cross-VM Side- channels Venkat(anathan) Varadarajan, Thomas Ristenpart, and Michael Swift 1 D EPARTMENT OF C OMPUTER S

20

More details in the paper …

• Per-core State-Cleansing– Interactive VMs may still leak information– MRT + State-cleansing incur low overhead

• Detailed Performance and Security Analysis – 20+ graphs in the paper

It is cheap and easy to deploy!

Page 21: Scheduler-based Defenses against Cross-VM Side- channels Venkat(anathan) Varadarajan, Thomas Ristenpart, and Michael Swift 1 D EPARTMENT OF C OMPUTER S

21

Conclusion

5ms MRT + selective state-cleansing- known attacks no longer work- negligible overhead- easy to adoptIntroduce new scheduler principle- soft-isolation = allow sharing + limit dangerous

cross-VM interactions

https://bitbucket.org/vvaradarajan/robsched

contact: [email protected]