IEEE TRANSACTIONS ON COMMUNICATIONS, VOL. 44, NO. 1, JANUARY 1996 I

Scarce-State-Transition Syndrome-Former Error-Trellis Decoding of (n, n - 1) Convolutional Codes

L. H. Charles Lee, David J.

Abstract- A novel scarce-state-transition (SST) type trellis decoding system for (n, n - 1) convolutional codes with coherent BPSK signals is proposed. The new system retains the same number of binary comparisons as the syndrome-former trellis decoding technique. Like the original SST-type encoder trellis technique, the proposed system is also suitable for CMOS VLSI implementation. A combination of the two techniques results in a less complex and low power consumption decoding system.

I. INTRODUCTION N VITERBI decoding of (n, I C ) convolutional codes, the I decoder carries out (ak - 1)-ary comparisons at each node of

the encoder trellis [l], [2]. The implementation of the Viterbi decoder becomes impractical for high-rate, powerful codes. In a 1983 paper, Yamada et aZ. [3] proposed a maximum- likelihood decoding system for rate-(n - l) /n convolutional codes. The decoding system applies the Viterbi algorithm to the syndrome-former trellis of the code. Apparently, the number of trellis states is doubled, but the number of com- parisons at each node is reduced to a binary comparison. Recently, Kubota et al. [4] and others [5]-[7] proposed scarce- state-transition (SST) register-exchange (information bits are associated with surviving paths) Viterbi decoding system for convolutional codes, implemented on CMOS VLSI chips. At an information rate of 25 Mb/s and a bit-error-rate (BER) of 0.0001, a power consumption reduction of 40% can be achieved by the system when compared with a hypothetical register-exchange type Viterbi decoder. The measured power consumption with increasing channel noise was also reported in [7].

In this paper, we propose a new SST-type trellis decod- ing system for rate-(n - l ) / n systematic or nonsystematic convolutional codes, called the SST-type syndrome-former error-trellis decoding system.' The new system is similar to the SST-type Viterbi decoding system [4] in that it has the advantage of drawing less power when implemented on CMOS chips and operated in a low BER condition. Like the Yamada decoding system [3], the new system has also retained

Paper approved by T. Aulin, the Editor for Coding and Communications Theory of the IEEE Communications Society. Manuscript received June 23, 1994; revised December 20, 1994, and March 28, 1995. This paper was presented in part at the Intemational Symposium on Information Theory and its Applications, Sydney, Australia, November 20-24, 1994.

L. H. C. Lee is with the School of Mathematics, Physics, Computing and Electronics, Macquarie University, Sydney, NSW 2109, Australia.

D. J. Tait and P. G. Farrell are with the Department of Electrical Engineer- ing, The Umversity, Manchester, M13 9PL, U.K.

Publisher Item Identifier S 0090-6778(96)00S00-8. As observed by a reviewer, the SST-type syndrome-former error-trelhs

decoding system is a maximum-likelihood decoding system. The error per- formance of the proposed decoding system is identical to the conventional Viterbi decoding system.

Tait, and Patrick G. Farrell

a binary comparison at each trellis node and significantly reduces the decoding complexity. A combination of the two techniques results a less complex and low power consumption decoding system. The implementation complexity of the new decoding system is compared with the SST-type register- exchange Viterbi decoding system. In all cases, minimal encoder [8] is assumed.

11. ENCODER AND SYNDROME-FORMER TRELLISES

An (n, n - 1) binary convolutional code of total encoder memory M [2] and constraint length v [2] can be described by a 2M-state encoder trellis with 2"-l transitions between any pair of trellis nodes. At time I , let the input and output sequences of the code be represented by the (n - 1)-component vector Xl = [XI') xi') x Y - ~ ] and the n-component vector Yl = [g;" gi2) . . . gp)] with elements 0 and 1, respectively. The entire encoding operation can be formulated as Y(D) = X(D)G(D) , where X ( D ) and Y(D) are the input and output sequences in polynomial matrix form, respectively. G(D) is the (n - 1) x n generator matrix of the (n, n - 1) convolutional code.

An (n, n - 1) linear convolutional encoder can also be described by its 1 x n parity-check matrix H ( D ) = [ H ( l ) ( D ) H( ' ) (D) . H(")(D)] . Consider the syndrome- former H ~ ( D ) for an (n, n - 1) minimal convolutional code, where H t ( D ) is the transpose of H ( D ) . This can be realized as a linear circuit which consists of M memory elements and M + 1 modulo-2 adders [3]. Based on the state transitions of the circuit, a 2"+l-state trellis can be determined [3]. Here, the trellis corresponding to the code vector Yl consists of n stages. The state of the trellis at depth f is expressed by a ( M + 1)-component binary vector df) = [sif) s(~) 1 . . . sg ) ] for 0 5 f 5 n. Figs. 1 and 2 show the encoder and syndrome-former trellises for a rate-3/4 convolutional code with

G ( D ) = 1 D 0 1 (1) [; b : :I and H ( D ) = [I 1 + D 1 + 0' 1 + D + D2], respectively.

111. SST-TYPE VITEREH DECODING SYSTEM [4]-[7] In what follows, all sequencedmatrices can be expressed in

a similar way as sequences/matrices described in Section 11. In the presence of a channel error sequence E(D), the hard- decision SST-type Viterbi decoding system differs from the conventional Viterbi decoding system in that the received

0090-6778/96$05.00 0 1996 IEEE

8 IEEE TRANSACTIONS ON COMMUNICATIONS, VOL. 44, NO. 1, JANUARY 1996

Fig. 1. Encoder trellis representation of (1).

110 101 100 01 1 010 001

110 101 100 01 1 010 001

Fig. 2. Syndrome-former trellis representation of H ( D ) = [l 1 + D 1 + D 2 1 + D + D 2 ] .

sequence R(D) = Y ( D ) + E ( D ) is first predecoded to give the predecoded sequence U ( D ) = X ( D ) + A(D), where A ( D ) = E(D)G-'(D) and G - l ( D ) is the right-inverse of the matrix G(D) [8]. U(D) is re-encoded to give the re- encoded sequence V ( D ) = Y ( D ) + A(D)G(D). V ( D ) is then added (modulo-2 addition) to R(D) to give a received error sequence C ( D ) = B ( D ) + E ( D ) , where B ( D ) = A(D)G(D) . Comparing B ( D ) = A(D)G(D) with Y ( D ) = X ( D ) G ( D ) , it is clear that one can draw a 2M-state error- trellis with input Ai and output Bz. The decoder now operates on the error sequence C ( D ) and the error-trellis by means of the Viterbi algorithm. The estimated sequence {a,} is then added (modulo-2 addition) to the delayed (corresponding to the decoder search length) version of the predecoded sequence to give the estimated information sequence { X Z } .

It has been shown that the SST-type Viterbi decoder can be implemented on CMOS VLSI chips [4], [5], [7]. With almost error free transmission, the received error sequence @ ( D ) to the input of the Viterbi decoder contains a large number of zeros. The decoder therefore picks the all-zero error path with high probability and there is rarely any state change

3-bit quantiser

oc A

X D )

w decoder

Fig. 3. Model of an eight-level soft-decision SST-type syndrome-former error-trek decodmg system.

from the all-zero sequence trellis state during decoding. The CMOS ON/OFF gates scarcely switch. As a result, the power consumption is significantly reduced by 40% when compared with that of the conventional Viterbi decoder, operating at an information rate of 25 Mb/s and a bit error rate of 0.0001 [7].

W . SST-TYPE SYNDROME-FORMER ERROR-TRELLIS DECODING SYSTEM

The SST-type syndrome-former error-trellis decoding sys- tem is a development of the SST-type Viterbi decoding system. The system model is shown in Fig. 3 . Here, the discrete noisy channel composes a binary phase-shift-keying (BPSK) modulator, a transmission path and a coherent demodulator, where additive white Gaussian noise (AWGN) with zero mean and variance C? = No/2 is added to the transmitted waveforms at the output of the transmission path. No/2 is the two-sided power spectral density of the noise. There is no difference between the hard-decision SST Viterbi decoding system described in Section I11 and the new decoding system up to the received error sequence C( D ) . Based on the received error sequence G(D) and the syndrome-former H t ( D ) , one can draw a 2M+1-state syndrome-former error-trellis with input Bz. Again, the syndrome-former error-trellis has the same form as the syndrome-former trellis of the code with Y E replaced by Bz. This trellis is also composed of re- encoded errors Bt only. The decoder now operates on the error sequence C ( D ) and the syndrome-former error-trellis by means of the Viterbi algorithm. Following a? inverse operation that assigns to the estimated sequence {Bl} the estimated sequence {Al}. {Az} is then added (modulo-2 addition) to the delayed version of the predecoded sequence to give the estimated information sequence { X l } .

In the SST-type Viterbi decoding system, the decoder holds 2" surviving paths and performs (2n-1 - 1)-ary comparisons per trellis state. The total number of binary comparisons is 2"(2"p1 - 1). In the SST-type syndrome-former error- trellis decoding system, the decoder holds 2M+1 surviving paths and performs, at most, one binary comparison per trellis

IEEE TRANSACTIONS ON COMMUNICATIONS, VOL. 44, NO. 1, JANUARY 1996 9

node. The total number of binary comparisons is less than 2M+1 per trellis interval. For an n-stage syndrome-former error-trellis, the total number of binary comparisons is less than 2 M f 1 ( n - 1). Hence, the proposed decoding system reduces the total number of binary comparisons but doubles the storage requirement when compared with the SST-type Viterbi decoding system.

It is clear that the SST-type syndrome-former error-trellis decoder can also be implemented on CMOS VLSI chips. At low bit error rate (<1 in lo3), it has the advantage of consum- ing similar degree of power as that of the original SST-type Viterbi decoder reported in [7] and discussed in Section 111. Furthermore, the system can easily be accomplished with soft-decision decoding. A possible eight-level soft-decision decoding arrangement of the SST-type syndrome-former error- trellis decoding system is shown in Fig. 3, with the highlighted signal paths corresponding to the hard-decision decoding case. The received signal and the re-encoded signal are quantized (natural binary quantization) to eight-level by 3-bit quantizers. They are then subtracted (bit-by-bit modulo-2 addition) and the modified signal is decoded by the soft-decision decoder.

Fig. 4 shows the error performance of the proposed decoding system in AWGN with the rate-3/4 convolutional code of (1). Eb is the average transmitted bit energy and the decoding search length, $, is fixed to be six times the constraint length of the code. Furthermore, perfect timing and carrier synchronization are assumed.

V. DISCUSSION In a practical implementation, the SST-type Viterbi decoder

holds 2”(n - l)$-component storage vectors and carries out 2M (2n-1 - 1) binary comparisons. Each vector, corresponding to a surviving path, stores the information error symbols along with the associated metric, and the storage requirement increases exponentially with M . For the SST-type syndrome- former error-trellis decoding system, the decoder has 2M+1 n. $-component storage vectors which hold the channel error symbols. However, the syndrome-former error-trellis has only one or two paths entering a state. The total number of binary comparisons in the new system is less than 2M+1(n - 1) and the storage requirement now increases exponentially with M + 1. For an example, the rate-3/4 convolutional code of (1) has four encoder trellis states, eight paths entering a node and requires 28 binary comparisons. Its syndrome- former trellis has eight states, one or two paths entering a node and only requires 12 binary comparisons. Clearly, the decoding complexity of the SST-type syndrome-former error-trellis decoding system is much more simpler than the SST-type Viterbi decoding system.

VI. CONCLUSIONS In this paper, a new SST-type trellis decoding system for

high-rate (n, n - 1) convolutional codes has been described. The new decoding system achieves a considerable reduction in the number of binary operations per received vector and can also be implemented on CMOS VLSI chips, operated with low power consumption and soft-decision decoding. The sim-

loo --

10-1 I w I

b . ’ 2 I \h\ - I 2 10- 1 - - . x I.

L I

6 I . t I I

I \ \ I \ I \

I \ \ I I \ l\ - I I \

-D- uncoded coherent BPSK -C hard-decision decoding + 8-level soft-decision decoding

Fig. 4. Error performance of SST-type syndrome-former error-trellis decod- ing system in AWGN channel (search length = 6v).

plicity and low power consumption of the proposed decoding technique makes it desirable, from a practical viewpoint, for high-rate convolutional codes.

ACKNOWLEDGMENT

The authors would like to thank the reviewers for their valuable comments. In particular, one of the reviewers pointed out that the proposed decoding system described in Section IV is a maximum-likelihood decoding system.

REFERENCES

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Englewood Cliffs, N J Prentice-Hall, 1983.