Scaling Si to 10nm

8/6/2019 Scaling Si to 10nm

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Silicon Device Scaling to theSub-10-nm Regime

Meikei Ieong,1* Bruce Doris,2 Jakub Kedzierski,1 Ken Rim,1 Min Yang1

In the next decade, advances in complementary metal-oxide semiconductor fabricationwill lead to devices with gate lengths (the region in the device that switches the currentflow on and off) below 10 nanometers (nm), as compared with current gate lengths inchips that are now about 50 nm. However, conventional scaling will no longer besufficient to continue device performance by creating smaller transistors. Alternativesthat are being pursued include new device geometries such as ultrathin channel struc-tures to control capacitive losses and multiple gates to better control leakage pathways.Improvement in device speed by enhancing the mobility of charge carriers may be ob-tained with strain engineering and the use of different crystal orientations. Here, wediscuss challenges and possible solutions for continued silicon device performance trendsdown to the sub-10-nm gate regimes.

The steady reduction in the minimumfeature size in integrated circuits has

helped the microelectronic industry to

produce products with spectacular increase in

computational capability and integration den-

sity at lower cost. Smaller transistors operate

faster than larger ones, and for a given chip

technology, the cost

of a chip decreases

with area rather than

with the number of

transistors.

The exponential

scaling trend surely

will eventually hitfundamental limits,

but the many predic-

tions of a near-term

end of device scaling

have proven too pes-

simistic. With the

introduction of the

production of 90-nm

node technology in

2004, the semicon-

ductor industry is en-

tering the Bnano[ era

(1) . ( T he B90-nm

node[

refers to thesmallest half-pitch metal lines available in the

technology. The actual gate lengths of the de-

vices are about 50 nm.) In the next decade,

device gate lengths will be scaled to below

10 nm (1). We discuss below the challengesin device scaling and possible solutions in

maintaining the performance trend.

MOSFETs: The Building Blocks

The MOSFET, or metal oxide semiconductor

field-effect transistor, is a fundamental

switching device in very-large-scale integrat-

ed (VLSI) circuits. A MOSFET (Fig. 1A)

has at least three terminals, which are des-

ignated as gate, source, and drain. The gate

electrode is separated electrically from the

source and the drain by a thin dielectric film,

usually silicon dioxide. The source and the

drain are doped with impurities that are op-

posite in polarity to the substrate, which is

doped with boron for N-channel transistors

and with arsenic or phosphorous for P-

channel transistors. This source, substrat

and drain doping effectively produces tw

back-to-back junction diodes from the sourc

terminal to the drain terminal. When a su

ficiently large positive voltage is applied t

the gate of an N-channel transistor (whic

creates an electric field, hence the field e

fect), the silicon surface is ‘‘inverted’’—th

conduction band is populated and forms

narrow conducting layer between the sourc

and the drain. If there is a voltage differenc

between the source and the drain, an electr

current can flow between them. When th

gate voltage is removed or set at zero volage, the surface region under the gate

depleted with electric carriers and there is n

current flow between the source and th

drain. We can therefore see that the curren

flowing through the structure can be regula

ed by applying voltage to the gate electrod

A MOSFET can be used either as an ele

trical switch or as an amplifier. The majorit

of MOSFETs on an integrated circuit toda

are used as electrical switches. How fast

MOSFET can be switched on and off

therefore a critical figure of merit to dete

mine the competitiveness of the technology

The two major factors that control the spee

of MOSFETs are the channel length from

the source to the drain and the speed at whic

channel charge carriers travel from the sourc

REVIEW

1IBM Semiconductor Research and DevelopmentCenter, T. J. Watson Research Center, YorktownHeights, NY 10598, USA. 2IBM Semiconductor Re-search and Development Center, MicroelectronicDivision, Hopewell Junction, NY 12533, USA.

*To whom correspondence should be addressed.E-mail: [email protected]

A Scaled Device

SCALING

Voltage: V/ αOxide: tox / α

Gate Length: L/ αDiffusion: xd / αSubstrate: α*NA

Voltage, V/ α

L/ α

n+ source n+ drain

p substrate, doping α*NA

G a t e d e l a y

I n c r e a s

e s p

e e d

R e d u c e P s t a n d b y

R e d u c e P

a c t i v

e

Vt

V t

Vdd Vdd

tox / α

xd / α

B C

GATE

Fig. 1. (A) Schematic of MOSFET indicating various relevant device scaling parameters. ( B) Complementary metal-oxidsemiconductor (CMOS) inverter gate delay as a function of power-supply voltage ( Vdd ). Gate delay rapidly increases as Vdapproaches the threshold voltage (Vt ). (C) Design space for supply and threshold voltages for optimum performance anpower dissipation. Technology scaling diminishes this design space.

www.sciencemag.org SCIENCE VOL 306 17 DECEMBER 2004



to the drain. We will discuss these two fac-

tors in more detail below.

Shrinking the Transistor

Shrinking transistors not only packs more

devices into a given area but also shortens the

distance between source and drain, or the gate

length, which can improve the switching

speed. The two challenges in

decreasing MOSFET size are

fabrication and maintaining

performance. The backboneof MOSFET fabrication is a

process called lithography,

which resembles the printing

of a photograph by shining

light through a negative onto

a photosensitive surface. Li-

thography allows complex

patterns to be created through

a series of printing and etch-

ing steps. The ability to print

ever-smaller fine lines is

mandatory for continued de-

vice scaling. Advanced photo-

lithography techniques haveenabled the industry to keep

pace with the demand im-

posed by increasingly smaller

structures. However, the

smallest feature size is re-

lated to the fundamental

limit of wavelength used in

conventional optical lithog-

raphy. Alternative technol-

ogies capable of writing

features far smaller than

those produced by conven-

tional optics have also been

demonstrated and includethe use of extreme ultravio-

let (EUV) radiation, x-rays,

and electron beams. Re-

cently, the self-assembly

process has attracted much

attention because of its po-

tential in producing nano-

scale patterns. The concern

is whether any of these al-

ternatives can be scaled up

to meet the throughput, con-

trol, and cost requirements

for manufacturing.

Given the ability to cre-ate smaller device features,

to what extent can the gate length be re-

duced before the MOSFET ceases to func-

tion as a switch? The gate terminal can lose

the control of channel electric carriers when

the source and the drain are brought into

proximity without scaling other device pa-

rameters. Eventually, the gate terminal can-

not turn off the devices, and transistor action

can no longer be observed. This phenom-

enon is the so-called short-channel effect

(SCE). According to the scaling theory of

Dennard (2), the vertical dimensions (gate-

oxide thickness, junction depth, and depletion

width) must be scaled down with the lateral

dimensions such as gate length. This theory

guarantees appropriate electrostatic character-

istics when a larger device is scaled down to

a smaller one (Fig. 1A). The industry has

been by and large following this scaling

guideline for shrinking MOSFETs to gain

higher density and speed without degrading

reliability and power.

The accelerated gate-length scaling in the

past decade has pushed many vertical device

parameters to their fundamental or techno-

logical limits. For example, gate oxide now

consists of only a few atomic layers; alterna-

tive gate materials with a higher dielectric

constant are needed. It is also difficult to p

duce an extremely shallow and abrupt junct

without increasing the external resistan

(Junction resistance is inversely proportio

to junction depth.)

Ion implantation has been the domin

process for the creation of shallow junctions

high-temperature annealing process is need

to repair the damage to

single crystal and to activ

the dopant atoms. During t

step, diffusion and redistribtion of dopant atoms occur

high-temperature, short ti

scale annealing process

more desirable to produ

shallow and abrupt junctio

A near-zero thermal-bud

junction technology, such

millisecond flash-lamp and

ser annealing, will be requir

Finally, the increase

channel doping needed

SCE control will substanti

ly increase the junction c

pacitance and leakage. Allthese changes degrade d

vice performance. The pro

lem is exacerbated by

‘‘nonscaling’’ factors th

arise when the traditio

MOSFET design is scaled

Nonscaling Factors

As pointed out above, se

eral factors do not scale

we shrink MOSFETs. T

subthreshold nonscaling is

is the most fundamental o

(3). A MOSFET is turned when a sufficiently high vo

age is applied to the ga

The voltage above which

MOSFET is turned on

loosely defined as thresh

voltage. The leakage curr

in the off state depends e

ponentially on the thresh

voltage. Ideally, one wou

keep the threshold volta

high to minimize the pow

consumed when the dev

is off (the stand-by pow

and to ensure an appropate noise margin. The su

ply voltage is usually reduced in dev

scaling to keep the active power manageab

and to ensure reliability. However, high

device performance will require as mu

gate overdrive (the excess voltage appli

above the threshold) as possible, becau

higher driving voltages lead to faster switc

ing. Figure 1B shows the circuit delay

a function of supply voltage, Vdd . Perfor

ance can only be maintained by keep

Fig. 2. Device schematics and cross sections for (A) SOI MOSFET, (B) UTSOIMOSFET, and (C) FinFET double-gate MOSFET.

Fig. 3. Device cross sections for (A) strained silicon on insulator (SGOI), (B) strainedsilicon directly on insulator (SSDOI), and (C) hybrid-orientation technology (HOT).

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threshold voltages low, but the threshold

voltage cannot be scaled down much without

causing a substantial increase in leakage cur-

rent in the off state. The proper choice of

Vdd and threshold voltage for best per-

formance and power tradeoff depends on the

application. The design window rapidly dimin-

ishes as technology is scaled down (Fig. 1C).

In addition, the aggressive reduction in gate

dielectric has also caused exponential in-

crease in gate leakage.

Together, these effects have caused the so-called power crisis in the silicon

chip industry. Power management has

now become the number one issue in

any high-performance and low-power

application. Currently, there is a con-

sensus that maintaining the device

performance trend with conventional

device scaling technique is extremely

challenging, if possible at all. New

device structures and materials will be

needed to sustain the current rate of

progress in device technology.

Possible Solutions for Device Scaling

Circuit performance can be improved

by building conventional MOSFETs on

a silicon-on-insulator (SOI) substrate

(Fig. 2A). The insulator layer can be

created by implanting oxygen ions and

then annealing the layer to form an

oxide. The addition of an oxide layer

below the transistor junction SOI layer

can effectively reduce the junction

capacitance and leakage current. It

also eliminates the so-called ‘‘reverse

body effect’’ (4) in stacked circuits. As

a result, SOI technology offers a faster circuit and consumes less power.

Ultrathin SOI (UTSOI) MOSFET is

an attractive option for device scaling,

because it can effectively reduce the SCE

and eliminate most of the leakage

paths (5–7 ). For thicker SOI channels,

the drain field could easily penetrate to

the source side through the channel or

buried oxide when the gate length is

reduced. However, a thin SOI channel

can resolve this problem. Based on this

concept, a functional transistor with a

gate length of 6 nm was demonstrated

(Fig. 2B) by using an ultrathin channelof 4 to 8 nm and aggressive ‘‘halo’’ (8) im-

plantation (6 ). This extremely small silicon

MOSFET was functional, but its device drive

current suffered from channel mobility degra-

dation and high external resistance.

The integration of ultrathin SOI channels

into the conventional MOSFET process is

quite challenging. The gate and spacer mod-

ules must be carefully designed to prevent

substantial silicon consumption. The ion im-

plantation process for the source/drain ex-

tension should be designed to minimize loss

of dopant dose and to avoid complete amor-

phization of the silicon layer by the ion im-

plantation process. A thin gate spacer coupled

with the raised-source-drain process has been

shown to be effective in minimizing external

resistance without compromising parasitic

capacitance. With this new process scheme,

improved drive currents were realized (9).

Setting and controlling the threshold volt-

age in devices with such thin SOI layers is also

quite challenging. Conventional doping schemes

may not be effective as a result of doping

fluctuation. One attractive process option is

to completely ‘‘silicide’’ the polycrystalline-

silicon gate stack by converting the polysili-

con to a metal silicide. The gate work function

can be adjusted over a substantial range by

alloyed silicide and ion implantation to the

gate before silicidation (7 ). Although the ex-

ternal resistance can be reduced by process

improvement, the mobility degradation in thin

SOI channels could be a fundamental issu

The channel mobility is substantially reduced

SOI thicknesses below 10 nm. This decreas

may be caused by a ‘‘surface roughness’’–lik

scattering mechanism that results from th

perturbation of band potential by variatio

in the SOI layer thickness (10).

The ultrathin SOI thickness requirement fo

SCE control in single-gate FETs can be relaxe

by using a more complex ‘‘double-gate’’ FE

that offers improved electrostatic gate contro

of the body. There are many review aticles on double-gate devices (11–13

The symmetric nature in a double-ga

FET reduces the depletion width by 50%

compared with that of a single-ga

structure. In addition, there is no drain

to-body fringing field through the burie

oxide (BOX) (Fig. 2A) in a double-ga

structure. Numerical simulations indica

that scalability for double-gate FET

improves by a factor of 2.5 to 3 (5). B

cause the double-gate device operate

at much lower vertical electric field

the mobility requirement in double-ga

devices can be lower than that of conventional planar MOSFETs (14).

Double-gate FETs can be fabricate

in planar (14, 15), vertical (16 ), an

finlike (17–19) structures. Of all th

double-gate device structures, the FinFE

is the simplest to implement. The bod

of a FinFET device consists of a vertic

crystalline silicon wall (Fig. 2C). Th

gate wraps around both sides of the fi

and creates a channel on each side o

the fin. In a FinFET, the two channe

are perpendicular to the wafer surfac

and the current direction is parallel t

the wafer surface. High current has beedemonstrated when the FinFET stru

ture is combined with a raised-source

drain process.

Enhanced Mobility: MakingCarriers Travel Faster

Mobility enhancement is an attractiv

option, because it can potentially im

prove device performance beyond an

of the benefits from device scalin

The two main approaches being pursue

are strain engineering (both proces

induced and substrate-induced) and or

entation effects (Fig. 3).Strain engineering. Strain effects induce

during the fabrication process can increase th

channel mobility. Both tensile and compre

sive stresses can be introduced in any one o

the three dimensions by process techniqu

(20–27 ). The electron and hole mobility r

spond differently to uniaxial stresses (Fig. 4

The most effective way to introduce hig

tensile strain to the channel is to epitaxiall

grow strained silicon on a relaxed silicon ge

manium (SiGe) layer. Because of the lattic

Conduction band Unstr. Si

Bulk Si

Strained Si

Strained Si

ml

Ec

EE

k

out-of-plane

mt

mt < ml

Valence band

∆2 valleys

∆4 valleys

HH

LH

Spin-orbit

∆6

∆ E 38meV

10%Ge

∆4

∆2

mt

mt

ml

k

Fig. 5. Biaxial stress effects on the conduction and valencebands of strained silicon.

Longitudinal

Drain

STI

Source

T r a n s v e r s e

G a t e

DrainSource

G a t e

Desired Stress:

Tran. Long. Z

T

Z

C T

T

pFET

T: Tensile stressC: Compressive stress

nFET T C

Fig. 4. Possible directions of uniaxial stresses and their effectson N-channel and P-channel MOSFETs.

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mismatch between silicon and SiGe, the lat-

tice of the silicon layer is stretched (strained)

in the plane of the interface. This deformation

breaks the symmetry of the energy-band struc-

ture and results in band splitting (Fig. 5). The

reduced interband/intervalley scattering and

effective masses result in enhanced carrier

transport in the strained-silicon layer that is

used as the channel of the MOSFET. En-

hanced drive currents of 15 to 25% have been

demonstrated on sub-100-nm bulk strained-

silicon MOSFETs (20). The performance ben-efit of combining strained silicon with an

SOI substrate has also been demonstrated in a

60-nm gate length, N-channel MOSFET with

ultrathin thermally mixed strained silicon/

SiGe on insulator substrate (28). The presence

of the SiGe layer in strained-silicon substrate

leads to several challenges related to materials

and integration, such as a high density of

defects in strained silicon on relaxed SiGe

induced by the strain relaxation in SiGe and a

substantial difference in doping diffusion

property in SiGe. (Boron diffusion is retarded,

whereas arsenic diffusion is enhanced as com-

pared with the diffusion in silicon.) Suchchallenges require additional efforts in junc-

tion engineering to control SCEs and to set

the MOSFET threshold voltages to the desired

values. Substantial device self-heating is also

observed in strained silicon/SiGe devices

because of the lower thermal conductivity in

SiGe. Recently, Rim et al . (29) demonstrated

transistors using ultrathin strained silicon

directly on insulator (SSDOI) structures that

eliminate the SiGe layer before transistor fab-

rication, thereby providing higher mobility

while mitigating the SiGe-induced material

and process integration problems.

An SSDOI structure is fabricated by alayer-transfer or ‘‘wafer-bonding’’ technique.

First, an ultrathin layer of strained silicon is

formed epitaxially on a relaxed SiGe layer,

and an oxide layer is formed on top. After

hydrogen is implanted into the SiGe layer, the

wafer is flipped and bonded to a handle

substrate. A high-temperature process splits

away most of the original wafer and leaves

the strained-silicon and SiGe layers on top of

the oxide layer. The SiGe is then selectively

removed and transistors are fabricated on the

remaining ultrathin strained-silicon. A fabri-

cated SSDOI device structure is shown in

Fig. 3A. Both electron and hole mobilityenhancement have been observed, which indi-

cates that strain is retained after the device-

processing steps have been completed (29).

Crystal orientation effects. The carrier

mobility of inversion layers depends on surface

orientations and current flow directions. For P-

channel MOSFETs, hole mobility is 2.5 times

as high on (110) surface orientation as on a

standard wafer with (100) surface orientation

(30). However, electron mobility is highest on

(100) substrates. To fully realize the advan-

tage of the carrier mobility dependence on

surface orientation, a new technology has been

developed to fabricate complementary metal-

oxide semiconductor (CMOS) on hybrid sub-

strates with different crystal orientations, with

NFETs on silicon of (100) surface orientation

and PFETs on (110) surface orientation (31).

In this hybrid-orientation technology (HOT),

layer-transfer process, block-level trench etch,

and epitaxial regrowth were performed before

the conventional CMOS device process. A

cross section of CMOS on hybrid substrate isshown in Fig. 3C, with NFET on (100) SOI

and PFET on (110) silicon epitaxial layer. The

hybrid substrate was formed by layer-transfer

technique through wafer bonding. First, hy-

drogen was implanted into an oxidized silicon

substrate. The wafer was then flip-bonded to a

handle wafer with different surface orienta-

tion. A two-phase heat treatment was then

carried out to split the hydrogen-implanted

wafer and strengthen the bonding. Finally, the

top SOI layer was polished and thinned down

to the desired thickness. A substantial PFET

performance enhancement was demonstrated

on 90-nm-node CMOS devices.Threshold voltage roll-off behavior, junc-

tion leakage current, overlap, and junction

capacitances are all very similar between

(110) and (100) substrates, which indicates

similar dopant diffusion characteristics for

these orientations. The HOT technology is

clearly an attractive option to improve device

performance without introducing new mate-

rial. However, the impact on circuit perform-

ance of mixing SOI and bulk devices on the

same chip will require more detailed analysis.

Viability: The Crucial Issues

The 2003 version of the International Road-map for Semiconductors (1) projected that, by

2016, sub-10-nm gate-length MOSFETs will

be in production with equivalent oxide thick-

nesses of 5 A and junction depths below 10 nm.

Although functional MOSFETs with sub-10-

nm gate lengths have been demonstrated using

UTSOI substrate, manufacturability problems

of sub-10-nm gate devices remain to be re-

solved. First, gate stacks with higher dielectric

constants and metal gate electrodes are needed

to mitigate the gate leakage problem. Second,

alternative doping techniques are required to

produce shallow and abrupt junction profiles

without severely increasing the external re-sistance. Third, alternative device structures

such as UTSOI and double-gate structures will

likely be needed for sub-10-nm gate devices.

Additional sources of performance gain are

also needed to compensate for any degradation

from the subthreshold nonscaling phenomenon.

Mobility-enhancement technique is attractive,

because it provides performance enhancement

in addition to any benefits derived from device

scaling alone. Straining the silicon crystal and

building N-type and P-type MOSFETs on differ-

ent crystal orientations are promising metho

for mobility enhancement. In fact, some fo

of strained-silicon techniques are already bei

used in silicon integrated-circuit manufact

ing. Some scaling and mobility-enhancem

options can be combined for even higher p

formance gains. One example that integra

both UTSOI and FinFET devices on the sa

wafer and that enables hybrid orientation w

reported by Doris et al . (32).

The growing power density and the dimini

ing process margin of sub-10-nm gate-lenMOSFETs cannot be dealt with by process te

nology alone. Overall system performance g

will require optimization among the techn

ogy, circuit, packaging, and architecture leve

References and Notes1. Semiconductor Industry Association, Internatio

Technology Roadmap for Semiconductors (20available at http://public.itrs.net.

2. R. H. Dennard et al., IEEE J. Solid-State Circuits 9, (1974).

3. Y. Taur, IEEE Spectrum 36, 25 (1999).4. The performance of bulk MOSFETs is often degra

in a stack configuration. This is known as the revebody effect. In SOI technology, the body is isolafrom other terminals; therefore, the reverse beffect can be avoided.

5. M. Ieong, J. Kedzierski, Z. Ren, B. Doris, T. Kanarsky, HP. Wong, Extended Abstract of the 2002 InternatiConference on Solid State Devices and Materials (SSDNagoya, Japan, 17 to 19 September 2002, pp. 136–1

6. B. Doris et al., International Electron Device Mee(IEDM) Tech. Dig. 2002, 267 (2002).

7. J. Kedzierski et al., IEDM Tech. Dig. 2002, 247 (208. A halo implant is an ion implantation technique

places impurity dopants next to the junction tipprevent SCEs without substantially increasing total amount of impurity dopants in the chanBecause of the halo implant, devices can be scaledshorter gate lengths before notable SCE sets in.

9. B. Doris et al., IEDM Tech. Dig. 2003, 631 (200310. Z. Ren et al., IEDM Tech. Dig. 2002, 51 (2002).11. H.-S. P. Wong, IBM J. Res. Dev. 46, 133 (2002).12. M. Ieong, H.-S. P. Wong, E. Nowak, J. Kedzierski, E. Jo

Proc. Third International Symposium on Quality ElectroDesign (ISQED) (2002), pp. 492–495.13. L. Chang et al., Proc. IEEE 91, 1860 (2003).14. M. Ieong et al., IEDM Tech. Dig. 2001, 441 (20015. K. W. Guarini et al., IEDM Tech. Dig. 2001, 425 (2016. J. M. Hergenrother et al., IEDM Tech. Dig. 1999, 75 (1917. J. Kedzierski et al., IEDM Tech. Dig. 2001, 437 (2018. D. Hisamoto, T. Kaga, Y. Kawamoto, E. Takeda, IE

Tech. Dig. 1989, 833 (1989).19. X. Huang et al., IEDM Tech. Dig. 1999, 67 (199920. K. Rim et al., Symposium on VLSI Technology , Hono

HI, 11 to 15 June 2002, pp. 12–13.21. A. Lochtefeld, D. Antoniadis, IEEE Electron Device L

22, 591 (2001).22. S. Ito et al., IEDM Tech. Dig. 2000, 247 (2000).23. G. Scott, J. Lutze, M. Rubin, F. Nouri, M. Manley, IE

Tech. Dig. 1999, 827 (1999).24. T. Ghani et al., IEDM Tech. Dig. 2003, 631 (200325. C.-H. Ge et al., IEDM Tech. Dig. 2003, 73 (2003)

26. V. Chan et al., IEDM Tech. Dig. 2003, 77 (2003).27. K. Goto et al., IEDM Tech. Dig. 2003, 623 (200328. B.-H. Lee et al., IEDM Tech. Dig. 2002, 946 (20029. K. Rim et al., IEDM Tech. Dig. 2003, 49 (2003).30. M. Yang, IEEE Electron Devices Lett. 24, 339 (200331. M. Yang et al., IEDM Tech. Dig. 2003, 453 (200332. B. Doris et al., Symposium on VLSI Technology , Hono

HI, 15 to 19 June 2004, pp. 86–87.33. The authors are grateful to their IBM colleag

Fabrication support by the Advanced SemiconducTechnology Center of IBM Microelectronic Divisand the Advanced Semiconductor Technology Laratory of IBM Research are very much appreciate

10.1126/science.1100731

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Scaling Si to 10nm