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TF5000CI
Service Manual
31 Jan, 2004
Topfield Co., Ltd
2
IMPORTANT Note : The design of the satellite receiver is subject to continuous development and improvement. Consequently, this receiver may incorporate minor changes in detail from the information contained in this manual. Warning : These servicing instructions are for use by qualified personnel only. To reduce the risk of electric shock, do not perform any servicing other than that specified in the operating instructions unless you are fully qualified to do so.
3
TABLE OF CONTENTS Page IMPORTANT........................................................................................................................2
1. Safety Instructions .........................................................................................................5
2. List and Description of The Major Parts.........................................................................6
2.1. Main Board ................................................................................................................................. 6
2.2. Front Board................................................................................................................................. 7
3. Block Diagram of The IRD.............................................................................................8
4. Block Diagram of The Main Board.................................................................................9
5. Test and Repair ...........................................................................................................10
5.1. Visual Test ................................................................................................................................ 10
5.2. Basic Function Test....................................................................................................................11
5.2.1. No LED and 7-segment is turned on .................................................................................................................... 11
5.2.2. Some LED and 7-segment have problems........................................................................................................... 11
5.2.3. Remote Control Unit (RCU) does not work. ......................................................................................................... 11
5.2.4. Key of the front panel have problems................................................................................................................... 11
5.2.5. No System ID is displayed.................................................................................................................................... 11
5.2.6. Receiver acts like the key of the Front Board or RCU is pressed. .......................................................................12
5.2.7. No picture but the OSD works. .............................................................................................................................12
5.2.8. No picture (and no OSD) and No sound...............................................................................................................13
5.2.9. No sound and good picture ..................................................................................................................................13
5.2.10. No picture(and no OSD) and good sound ............................................................................................................13
5.2.11. No sound and / or no picture on the RF modulator (Cinch works well) ................................................................13
5.2.12. No LNB power at all of the vertical and horizontal................................................................................................13
5.2.13. Incorrect LNB power.............................................................................................................................................14
5.3. The Advanced Test of Main Board............................................................................................ 15
5.3.1. Voltages on important point ..................................................................................................................................15
5.3.2. Power on Test sequence ......................................................................................................................................15
5.3.3. Reset ....................................................................................................................................................................16
5.3.4. System Clock........................................................................................................................................................17
5.3.5. RS232 Data Port (Program download port) and Program download ...................................................................17
5.3.6. LNB power............................................................................................................................................................18
5.3.7. RF modulator........................................................................................................................................................19
5.3.8. Video.....................................................................................................................................................................19
5.3.9. Audio ....................................................................................................................................................................19
5.3.10. SCART bypass .....................................................................................................................................................19
5.4. The Advanced Test of Front Board. .......................................................................................... 20
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5.4.1. Key .......................................................................................................................................................................20
5.4.2. Remote control .....................................................................................................................................................20
5.4.3. Display..................................................................................................................................................................20
5.4.4. Nothing works on Front Board..............................................................................................................................20
5.5. The Advanced Test of SMPS.................................................................................................... 21
5.5.1. Check the damaged parts.....................................................................................................................................21
5.5.2. Test the diodes. ....................................................................................................................................................21
5.5.3. Check the 3.3V regulator......................................................................................................................................21
5.5.4. Check the Shunt regulator....................................................................................................................................21
5.5.5. Check the Photo coupler IC..................................................................................................................................21
5.5.6. Check the Fuse. ...................................................................................................................................................21
6. PIN description of The Major Parts..............................................................................22
6.1. Main Board ............................................................................................................................... 22
6.2. Front Board............................................................................................................................... 22
6.3. SMPS : ORTP-826 (HDAD30W701) ........................................................................................ 22
7. Schematic Diagrams ...................................................................................................23
7.1. Schematic diagram of Front Board........................................................................................... 23
7.2. Schematic diagram of Main Board ........................................................................................... 24
7.3. Schematic diagram of SMPS (power supply)........................................................................... 25
A. 1 Pin description Section ...............................................................................................26
A. 2 Schematic Diagram Section < Front Board > .............................................................27
A. 3 Schematic Diagram Section < Main Board >..............................................................28
A. 4 Schematic Diagram Section < SMPS > ......................................................................29
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1. Safety Instructions Read this chapter carefully before servicing the IRD.
1.1 The IRD must be disconnected from the mains plug before it is opened. 1.2 The capacitor inside the SMPS (power supply) can hold charge even if the IRD has been disconnected
from the mains plug. To handle SMPS, wait until the capacitor is discharged. 1.3 Only the same screw should be used to assemble the IRD.
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2. List and Description of The Major Parts
2.1. Main Board
Page Part
Name
Location
Number Part number Function Comment
Tuner Module U1 TBMU24311IPP Channel tuning.
Analog to Digital Conversion.
QPSK demodulation.
Or, equivalent part
Regulator U2 LM7805
(with Heat sink)
Regulates Tuner 5V Or, equivalent part
LNB Power
Switching IC
U3 LNBP20PD Regulates and switching LNB power
(Horizontal 18V, Vertical 13V)
22KHz tone On/Off
LNB Power Bypass
1
Poly Switch U4 RXE065 Over current protection of
LNB power.
3 CPU, Demux
and Decoder
U5 IBM39STB02500 Main CPU of IRD
MPEG Demux and Decoder
Flash Memory U7 SST39VF800A Saves program and constant Or, equivalent part 4
EEPROM U8 24LC02B-SN Saves some parameters Or, equivalent part
5 SDRAM U9 K4S641632D Main system memory Or, equivalent part
ASIC U10 TF301SC10 CI interface, System control 6
Reset IC U11 ELM9727NBA
Power level detection,
Resets the system.
Only one IC is used
Regulator U12 LD1117ADT18 Regulates internal 1.8V Or, equivalent part
Regulator U13 MIC39100-2.5BS Regulates internal 2.5V.
Regulator U14 78L12 Regulates internal 12V.
7
Connector JP2 5267-12A Power input connector from SMPS
RS232 Driver U15 MAX232 Rs232 level conversion Or, equivalent part 8
Connector JP3 5267-3A Connector for RS232 sub board
TTL U17, … 74 series Buffer and mux for CI Or, equivalent part
FET U16 IRF7303 CI Power On/Off Or, equivalent part
9, 10
Connector U20 PIS2B1382 PCMCIA connector for CI
11 Audio DAC U31 UDA1334TS Audio Digital to Analog Converter
A/V Switch U33 STV6412A A/V switch for SCART and Cinch
SCART SCART1 2203-42STA SCART connector
12
Cinch J1 RCA – 3pin Cinch connector for A/V
Regulator U34 LM7805
(without Heat sink )
Regulates 5V for RF-modulator Or, equivalent part 13
RF Modulator U35 RMUP74055AB RF Modulator
Connector JP9 5267-7A Front Board Interface 15
TTL U37 74LVC14 Front Board Interface Or, equivalent part
16 Connector JP10 mini Din Jack S-Video Connector
17 Connector JP7 5267-10A Smart Card Sub board connector Embedded CAS, Optional
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2.2. Front Board page Part
Name
Location
Number
Part number Function Comment
7-Segment U1 A-3C4G Displays Messages Or, equivalent part
Remocon Sensor U2 TSOP4838 Receives RCU signal Or, equivalent part
TTL U3, U4 74HCT164 Interface front board with
main board
Or, equivalent part
1
Connector J1 5267-7A Front board and main board
interface
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3. Block Diagram of The IRD
Fron
t Boa
rd
Mai
n Bo
ard
Com
mon
Inte
rfac
eSl
ot
Cin
ch
RF
MO
DU
LATO
RSC
AR
TPO
RG
RA
MD
OW
NLO
AD
POR
T
+5V
, Con
trol s
igna
l
TUN
ER
+30V
, +22
V, +
17V
, +15
V, +
8V,
+5V
, +3.
3V, G
ND
RS2
32 b
oard
Pow
er S
uppl
y(S
MPS
)
S-V
ideo
SPD
IF
9
4. Block Diagram of The Main Board
DRA
M fo
r TS
Buffe
r & S
yste
m
IBM39STB02500
(VULCAN)
FLA
SH M
emor
y Fr
ont B
oard
I/F
Prog
ram
Dow
nloa
d Po
rt (R
S232
)
EEPR
OM
(24L
C02
)TUNER
VC
XO
Con
nect
or fo
r Man
ufac
ture
Cin
chou
tput
SCA
RT
Syst
em C
ontro
l &C
I ASI
C(T
F301
SC10
)A
VM
atrix
Switc
h(S
TV64
12)
RFm
odul
ator
CI c
onne
ctor
CI c
ontro
l buf
fer
Vid
eo O
utpu
t
LNB
pow
er,
22kh
zge
nera
tor
Des
cram
bled
Cha
nnel
Dat
a
Scrambled Channel Data
IIC
bus
for R
F m
odul
ator
IIC
CI C
ontro
l Sig
nal
Aud
io D
AC
(UD
A13
34)
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5. Test and Repair 5.1. Visual Test
- Check whether all the connectors are plugged well. ‘JP2’ of Main Board : Power connector. ‘JP3’ of Main Board : Internal RS232 connector. ‘JP5’ of Main Board : SPDIF connector. ‘JP7’ of Main Board : Connector for SMART Card sub-Board interface (optional) ‘JP9’ of Main Board : Connector for Front Board interface
- Check whether the SMPS(power supply) has any damage. - Check whether the Main Board has any damage. - Check whether the Front Board has any damage. - Check whether the RS232 Sub board has any damage.
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5.2. Basic Function Test 5.2.1. No LED and 7-segment is turned on Possible Cause How to Check How to repair 1 Front Board Problem Replace the Front Board with
new one which works well in other IRD
If it works, repair the Front Board. Otherwise, check the Main Board and SMPS.
5.2.2. Some LED and 7-segment have problems Possible Cause How to Check How to repair 1 Front Board Problem Check the Front Board according to
the advanced function test. 5.2.3. Remote Control Unit (RCU) does not work. Possible Cause How to Check How to repair 1 Remote Controller may
have some problem. If some keys of RCU do not work, it may be RCU problem.
Replace the RCU with new one.
2 Sensor of the Front Board may have problem
If key, LED and 7-segment work, And only the Remote control does not work, it is sensor problem.
Check the PCB pattern of Front Board. Check the power of U2(sensor). Replace the sensor.
5.2.4. Key of the front panel have problems Possible Cause How to Check How to repair 1 If some of the key does
not work, it is the Front Board problem. Pattern or broken tact switch can be a problem
If one of the key or RCU work, it is the problem of the switch or PCB pattern of the Front Board.
Check the switch and the PCB patterns of Front Board.
2 If sometime RCU work, but the key of the front panel does not work, then one of the key may be pressed always.
Check J1.3 in Front Board or Jp9.3 in main board. This pin should be “HIGH” when no key is pressed.
Replace the tact switch. Check the PCB and remove the short to the GND. Check the Front board resistors
5.2.5. No System ID is displayed Possible Cause How to Check How to repair
1 Main Board problem. Communication problem between the Front Board and the Main Board.
Replace the Front Board with new one which works well in the other IRD
If it works, repair the Front Board. If it does not work, repair the Main Board.
2 Main Board fails to boot. The 7-segment on the Front Board displays only the time with brighter display when the power key is pressed.
Repair the Main Board. Check the powers of Main Board.
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REF) System ID : When the power is turned on, 7-segment on the Front panel displays it. Ex) ‘L5.01’ is displayed : its System ID is 501 5.2.6. Receiver acts like the key of the Front Board or RCU is pressed. Possible Cause How to Check How to repair 1 The key of the Front
Board is pressed always. Replace the Front Board and check it. Check J1.3 in Front Board or Jp9.3 in main board. This pin should be “HIGH” when no key is pressed.
Replace the broken key with new one. Check the Front PCB. Replace the tact switch. Check the PCB and remove the short to the GND. Check the Front board resistors
5.2.7. No picture but the OSD works. Possible Cause How to Check How to repair 1 Tuner problem If the signal level of the tuner is
very low, it may be a problem of the tuner, antenna cable or antenna.
Check the antenna signal. Check the tuner part.
2 No or bad LNB power No or bad 22khz signal.
Check the LNB power and 22khz signal on LNB in of the tuner.
See LNB section of this manual.
3 The power of the tuner has some problem.
If the signal level of the tuner is very low, check the voltage of the U1.7 (tuner). It should be about 30V.
If not, check the SMPS and the power path (include series bead(L5) and capacitors (C9, C7)
4 CPU (IBM39STB02500) problem
If all the other things work except the picture and sound, it may be the problem MPEG decoding. In this case, the signal level and signal quality of the information bar will be good.
5 Channel Data path problem. (include CI interface Circuit )
There is good RF signal level, and good signal quality, but no broadcasting is scanned. In this case, it may be a channel data path problem.
Check the channel data path of the Main Board.
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5.2.8. No picture (and no OSD) and No sound Possible Cause How to Check How to repair 1 CPU (IBM39STB02500)
problem. In this case, the OSD have some problems.
Check SMPS and Main Part of main board voltage
2 A/V switch problem If the front works well and nothing is appear on TV, it can be an A/V switch problem.
Repair the Main Board according to the advanced function test.
3 SMPS problem. Check the all the power of power connector on Main Board.
Repair the power according to the advanced function test .
5.2.9. No sound and good picture Possible Cause How to Check How to repair
1 Audio DAC problem Test the Main Board according to the advanced function test.
Repair the Main Board according to the advanced function test.
2 A/V switch problem Test the Main Board according to the advanced function test.
Repair the Main Board according to the advanced function test.
5.2.10. No picture(and no OSD) and good sound Possible Cause How to Check How to repair
1 CPU (IBM39STB02500) problem
Test the Main Board according to the advanced function test.
2 A/V switch problem Test the Main Board according to the advanced function test.
Repair the Main Board according to the advanced function test.
5.2.11. No sound and / or no picture on the RF modulator (Cinch works well) Possible Cause How to Check How to repair 1 RF channel is selected
incorrectly. Check the RF channel selection.
Select the correct channel.
2 RF modulator has problem.
Replace the RF modulator with new one. If it works well, it is the problem of RF modulator.
Replace it with new one.
3. Problem of Audio or Video line on the board.
Replace the RF modulator with new one. It will have the same problem.
Repair the Main Board.
5.2.12. No LNB power at all of the vertical and horizontal. Possible Cause How to Check How to repair 1 ‘LNB power OFF‘ is
selected in the menu. Check the LNB menu. Set the LNB power to ON.
2 U3(LNBP20PD)or related circuit has problem.
Test the Main Board according to the advanced function test.
Repair the Main Board according to the advanced function test.
4 SMPS has problem. Check the SMPS Replace the SMPS.
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5.2.13. Incorrect LNB power Possible Cause How to Check How to repair
1 If only the 18V is very low, it can be a SMPS problem.
Check the SMPS(or JP2.2). It should be higher than 20V.
If not, replace SMPS.
2 Both the 18V and 13V are too low or too high.
Test the Main Board according to the advanced function test.
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5.3. The Advanced Test of Main Board. 5.3.1. Voltages on important point
- Voltage at JP2 in page 7 (of a schematic diagram)
Pin number Minimum
voltage
Nominal
voltage
Maximum
voltage
Comment
1 +28V +30V +32V
2 +20V +22V +23V
3 +16V +17V +18V
5 +7.6V +8V +8.4V
7 +4.75V +5V +5.25V
9 +3.22V +3.3V +3.38V In standby mode, it can be higher than maximum voltage
11 +14V +15V +17V
4,6,8,10,12 GND GND GND
- Voltage at check points in standby mode.
check
points
page Nominal
voltage
Comment
JP9.1 15 +5V Power is supplied to the Front Board even if standby mode
U14.3 7 +12V Power is supplied to SCART Circuit even if standby mode
C50 12 +5V Power is supplied to SCART Circuit even if standby mode
- Voltage at check points in normal mode.
check
points
page Nominal
voltage
Comment
JP9.1 15 +5V Power is supplied to the Front Board even if standby mode
U14.3 7 +12V Power is supplied to SCART Circuit even if standby mode
C50 12 +5V Power is supplied to SCART Circuit even if standby mode
* important : Be careful not to short the signals while checking the signals. It may damage the other part of Main Board.
5.3.2. Power on Test sequence - Check point 1 -
JP9.1 is the power supply pin of the Front Board. It should be 5V. If it is not 5V, remove the Front Board from the JP9. And, check JP9.1 again. If it is 5V, the Front Board have problem. Otherwise, the Main Board or SMPS have problem.
- Check point 2 – Replace the Front Board with new one. If it does not work, it is the problem of Main Board. Check the voltages of some
16
points according to ‘Voltages on important point’ section.
5.3.3. Reset After power on by the Front Board, reset circuit works. Schematic page 6.
U11 is a voltage detector. If the voltage of 3.3V is lower than 2.7V its output goes to low. The ‘nRESETIN’ signal should go high after power up ( when the IRD goes to Normal state from Standby state.) The reset signal is delayed and reconstructed in U10(TF301SC10). The reset output of U10.51 is provided to all the system. - Check point 1 -
In normal state, the ‘nRESETIN’ signal is 3.3V. If it is about 0V, U11 has problem. - Check point 2 -
U10.50 and U10.51 should be 3.3V. If only U10.50 is 3.3V, check the system clock.
17
5.3.4. System Clock Schematic page 3
VCXO1 generates the system clock. The ‘SCLK’ signal is 27.000MHz clock signal. If the color of the picture disappears, the ‘SCLK’ signal may be different from 27.000MHz or the VCXO1 have bad quality. In this case, replace VCXO1 with new one. - Check point 1 -
Check the input and output of ‘F1’. All of them should have 27MHz clock signal. If F1.3 have not 27MHz clock signal, it may the problem of VCXO1.
- Check point 2 - If the video output of receiver has not color, It may the problem of VCXO1.
5.3.5. RS232 Data Port (Program download port) and Program download Connect a PC with a download cable (Female – Female cross cable). If it fails program download and nothing happens in the receiver, check the download cable and the PC. The pin2 and pin3 of the download cable should be crossed.
Not Populated Parts
18
- Check point 1 -
Check the download cable and the PC with a new receiver.
- Check point 2 -
Check the error code on the display of the Front Board. Some message is displayed on the Front panel
when the new program is downloaded. The message and error code is as follows.
Display Description
dn## Data is being downloaded. (‘##’: the number of remained data block)
LP## Loader program is being saved.
(‘##’ : the number of remained flash block to write the loader program.)
AP## Application program is being saved.
(‘##’ : the number of remained flash block to write the application program.)
Fd## Flash data program is being saved.
(‘##’ : the number of remained flash block to write the flash data.)
Ed## EEPROM data is being saved.
(‘##’ : the number of remained EEPROM block to write the EEPROM data.)
E-01 The CRC error of Header/Data block.
E-02 The CRC error of Application program.
E-03 UART communication error.
E-04 Error while Flash writing.
E-05 Memory overflow
E-06 Different system ID. -> The model of the receiver and the program(or data) to be
downloaded is not matched.
E-07 Not supported TFD version.
E-08 Not supported data type.
E-09 EEPROM read error.
E-10 EEPROM write error.
E-11 Not supported Flash memory.
E-12 Error while TFDM writing.
5.3.6. LNB power U3.5 is the control signal for selecting vertical or horizontal. At vertical, level of this pin is logical “LOW”, about 0. And at horizontal, logical “HIGH”, about 3V. U3.4 is the output voltage for tuner (LNB). At vertical, Voltage at this pin is about 13V and at horizontal, about 18V. - Check Point 1 -
If the voltage of U3.2 has below 15V, check the voltage of SMPS according to ‘ Voltages on important point’ section. If the voltage of U3.3 has below 20V, check the voltage of SMPS according to ‘ Voltages on important point’ section.
19
Set the LNB voltage to Vertical.
- Check Point – Check level of U3.5 whether logically ‘LOW’ ( about 0V ). If logically ‘HIGH’ ( over 2V) then check the line from U5 (IBM39STB02500) and U3.5. Check level of U3.6 whether logically ‘HIGH’ ( about 3V ). If logically ‘LOW’ ( about 0V) then check the line from U5 (IBM39STB02500) and U3.6. Check the voltage of U3.4. That value must be about 13V. Voltage of U3.4 is under 12V, then check soldering status of U3.
Set the LNB voltage to Horizontal - Check Point –
Check level of U3.5 whether logically ‘HIGH’ ( about 3V ). If logically ‘LOW’ ( about 0V) then check the line from U5 (IBM39STB02500 ) and U3.5. Check level of U3.6 whether logically ‘HIGH’ ( about 3V ). If logically ‘LOW’ ( about 0V) then check the line from U5 (IBM39STB02500) and U3.6. Check the voltage of U3.4. That value must be over 20V. Voltage of U3.4 is under 20V, then check soldering status of U3.
5.3.7. RF modulator - Check point 1 -
Check the power input of RF modulator (U35, schematic page 13) - Check point 2 -
Check the IIC line.(the signal name is SDA5V, SCL5V).
5.3.8. Video
For CVBS
- Check point 1 - Check L16 and its related circuit (CVBS), L17 and its related circuit (RED), L19 and its related circuit (GREEN) and L21 and its related circuit (BLUE). At this point all the signal should be work. If it works well, U33 or its related circuit has problem. If it does not work well, the IBM39STB02500 (U5) may have problem.
For S-VIDEO
- Check point 1 - Check JP5 S-Video connector and its related circuit.
5.3.9. Audio - Check point 1 -
Check U31(UDA1334TS) and its related circuits from schematic page 11. And check C60, C63 and U33 from schematic page 12. All these this has no problem, then check SCART Connector (SCART1) and Cinch Jack(J1).
5.3.10. SCART bypass - Check point 1 -
If SCART bypass has problem, check U33 and its related circuit.
20
5.4. The Advanced Test of Front Board. * Applicable Front Board : TFCB-7KEY, SIRIUS-5KEY. 5.4.1. Key
If any key pressed, J1.3 in Front board goes low and high repeatedly. If level of this pin never goes to “LOW”, main board problem,
5.4.2. Remote control U5 is the sensor for remote control. - Check point 1 – Check the Remote control unit with other receiver. If it does not work, the Remote control unit may have problem. If the key and display work and only the remote control does not work, U5 (sensor) may have problem. Check the power of the sensor (U5.3). It should 5V. If not, check the R10 and the PCB. - Check point 2 – If you can not find any problem with the U5.3, replace it with new one.
5.4.3. Display - Check point 1 – If one of the digit is brighter than the other, and the digit displays wrong character, then check resistors and transistors in front board. If there is no wrong value or parts, then replace transistor with new one. - Check point 2 – If one of the digit is not displayed, replace the transistor Q1 to Q5 as follows. First Digit -> Q1 2nd Digit -> Q2 3rd Digit -> Q3 4th Digit -> Q4
dots and LED on the display -> Q5 - Check point 2 –
If one of the segments in one digit is not displayed, replace the display module. - Check point 3 –
If one of the segments of all digit is not displayed, check the resistors (R1, R2, R3, R4, R5, R7, R8, R9) and the PCB pattern.
5.4.4. Nothing works on Front Board.
- Check point 1 – The power of Front board (J1.1), U2.3, U3.14, U4.14
21
5.5. The Advanced Test of SMPS. * There are two kinds of SMPS. : ORTP-826, HDAD30W701.*
-------------------------------------- Caution ------------------------------------------- I. The SMPS must be disconnected from the mains plug to test. II. The capacitor inside the SMPS (power supply) can hold charge even if
the IRD has been disconnected from the mains plug. To handle SMPS, wait until the capacitor is discharged.
III. Very high voltage is generated in SMPS.
5.5.1. Check the damaged parts. - Check point 1 –
Check whether there is broken part by visual test.
5.5.2. Test the diodes. Check point 1 –
Check whether the diodes has crack. If there is a crack, replace it with new one.
Same part should be replaced.
- Check point 2 –
Check the resistance of all the diodes. If the resistance is too low (lower than 10ohm), it is the problem.
Replace it with new one. Same part should be replaced. Diodes is named as Dxx or ZDxx.(ex: D1,
ZD1)
To measure the resistance, you must remove the mains plug.
5.5.3. Check the 3.3V regulator - Check point 1 –
If only the 3.3V has problem, check the U3.VI. If it is about 4V, check the shunt regulator.
5.5.4. Check the Shunt regulator - Check point 1 –
Check the voltage of U2 -cathode. It should higher than 3V. If not, remove U2 and check it again.
If it is higher than 3V, replace U2 with new one.
- Check point 2 –
If U2 -cathode is higher than 3V, the voltage at U2 -ref should 2.5V. If not, replace U2 with new one.
5.5.5. Check the Photo coupler IC - Check point 1 –
Check the photo coupler PC1. Check the resistance of diode part and photo Transistor part.
If its resistance is about 0 or very low, replace it with new one.
Check if it has damages. And replace it with new one.
5.5.6. Check the Fuse. - Check point 1 –
Check the fuse. Before replacing the fuse, check the other problem which can exist.
The same kind and rated fuse should be replaced..
22
6. PIN description of The Major Parts
6.1. Main Board Tuner Module U1 TBMU24311IPP
Regulator U2 LM7805
LNB Power Switching IC U3 LNBP20PD
CPU, Demux and Decoder U5 IBM39STB02500
Flash Memory U7 SST39VF800A
EEPROM U8 24LC02B-SN
SDRAM U9 K4S641632D
Reset IC U11 ELM9727NBA
Regulator U12 LD1117ADT18
Regulator U13 MIC39100-2.5BS
Regulator U14 78L12
RS232 Driver U15 MAX232
FET U16 IRF7303
Audio DAC U31 UDA1334TS
AV Switch U33 STV6412
RF Modulator U35 RMUP74055AB
- See the Pin description Section -- A. 1
6.2. Front Board Part
Name
Location
Number
Part number
Remocon Sensor U2 TSOP4838
TTL U3, U4 74HCT164
- See the Pin description Section -- A. 1
6.3. SMPS : ORTP-826 (HDAD30W701) Part
Name
Location
Number
Part number
Shunt regulator U2 KA431A (AZ431BZ-B)
SPS U1 KA1M0380R (KA5M0365R)
3.3V regulator U3 KA278R33
- See the Pin description Section -- A. 1
23
7. Schematic Diagrams 7.1. Schematic diagram of Front Board
- See the Schematic Diagram Section < Front Board > -- A. 2
24
7.2. Schematic diagram of Main Board
- See the Schematic Diagram Section < Main Board > -- A. 3
25
7.3. Schematic diagram of SMPS (power supply)
- See the Schematic Diagram Section < SMPS Board > -- A. 4
26
A. 1 Pin description Section
#$
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*
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&
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*/
,
,
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TL/H/7746
LM
78X
XSerie
sV
olta
ge
Regula
tors
February 1995
LM78XX Series Voltage Regulators
General DescriptionThe LM78XX series of three terminal regulators is available
with several fixed output voltages making them useful in a
wide range of applications. One of these is local on card
regulation, eliminating the distribution problems associated
with single point regulation. The voltages available allow
these regulators to be used in logic systems, instrumenta-
tion, HiFi, and other solid state electronic equipment. Al-
though designed primarily as fixed voltage regulators these
devices can be used with external components to obtain
adjustable voltages and currents.
The LM78XX series is available in an aluminum TO-3 pack-
age which will allow over 1.0A load current if adequate heat
sinking is provided. Current limiting is included to limit the
peak output current to a safe value. Safe area protection for
the output transistor is provided to limit internal power dissi-
pation. If internal power dissipation becomes too high for
the heat sinking provided, the thermal shutdown circuit
takes over preventing the IC from overheating.
Considerable effort was expanded to make the LM78XX se-
ries of regulators easy to use and mininize the number
of external components. It is not necessary to bypass the
output, although this does improve transient response. Input
bypassing is needed only if the regulator is located far from
the filter capacitor of the power supply.
For output voltage other than 5V, 12V and 15V the LM117
series provides an output voltage range from 1.2V to 57V.
FeaturesY Output current in excess of 1AY Internal thermal overload protectionY No external components requiredY Output transistor safe area protectionY Internal short circuit current limitY Available in the aluminum TO-3 package
Voltage RangeLM7805C 5V
LM7812C 12V
LM7815C 15V
Schematic and Connection Diagrams
TL/H/7746–1
Metal Can Package
TO-3 (K)
Aluminum
TL/H/7746–2
Bottom View
Order Number LM7805CK,
LM7812CK or LM7815CK
See NS Package Number KC02A
Plastic Package
TO-220 (T)
TL/H/7746–3
Top View
Order Number LM7805CT,
LM7812CT or LM7815CT
See NS Package Number T03B
C1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.
LNBP10 SERIES - LNBP20
2/18
input pin is available (EXTM). An appropriate DCblocking capacitor must be used to couple themodulating signal source to the EXTM pin. Whenexternal modulation is not used, the relevant pincan be left open.Two pins are dedicated to the overcurrentprotection/monitoring: CEXT and OLF. Theovercurrent protection circuit works dynamically:as soon as an overload is detected in either LNBoutput, the output is shut-down for a time toffdetermined by the capacitor connected betweenCEXT and GND. Simultaneously the OLF pin, thatis an open collector diagnostic output flag, fromHIGH IMPEDANCE state goes LOW.After the time has elapsed, the output is resumedfor a time ton=1/15toff (typ.) and OLF goes in HIGH
IMPEDANCE. If the overload is still present, theprotection circuit will cycle again through toff andton until the overload is removed. Typical ton+toffvalue is 1200ms when a 4.7µF external capacitoris used.This dynamic operation can greatly reduce thepower dissipation in short circuit condition, stillensuring excellent power-on start up even withhighly capacitive loads on LNB outputs.The device is packaged in Multiwatt15 forthru-holes mounting and in PowerSO-20 forsurface mounting. When a limited functionality in asmaller package matches design needs, a rangeof cost-effective PowerSO-10 solutions is alsooffered. All versions have built-in thermalprotection against overheating damage.
(*): External components are needed to comply to level 2.x and above (bidirectiona) DiSEqC bus hardware requirements. DiSEqC is atrademark or EUTELSAT.
ORDERING CODES
(*) Available on request
PIN CONFIGUARATION (top view)
TYPE Multiwatt-15 PowerSO-20 PowerSO-10
LNBP10 LNBP10SP-TR (*)LNBP11 LNBP11SP-TR (*)LNBP12 LNBP12SP-TR (*)LNBP13 LNBP13SP-TR (*)LNBP14 LNBP14SP-TR (*)LNBP15 LNBP15SP-TR (*)LNBP16 LNBP16SP-TR (*)LNBP20 LNBP20CR LNBP20PD-TR
PowerSo-20 PowerSO-10Multiwatt-15
IBM39STBx25xx
Preliminary STBx25xx Digital Set-Top Box Integrated Controllers
Stbx25_Overview.fm.02May 31, 2002- IBM Confidential
Product Overview
Page 43 of 890
1.6.4.10 Real Time Clock / Front Panel Controller
The Real Time Clock (RTC) counts seconds, minutes, hours, and days. Programmable alarms can be set tointerrupt the CPU, allowing the CPU to wake up when required to perform functions such as programming aVCR. The RTC also provides a 3-wire front panel control interface, to drive panel seven-segment displayswith time information or program-generated data.
1.7 Signal and I/O Information
1.7.1 Signals Sorted by Signal Name
Table 1-1. Signals Sorted by Signal Name
I/O Signal Name Ball Number
27MHZ_CLK AA12
AUD_GNDA0 AA8
AUD_GNDA1 AC3
AUD_VDDA0 AC7
AUD_VDDA1 AA5
BI_ADDRESS11 W21
BI_ADDRESS12 Y23
BI_ADDRESS13 V20
BI_ADDRESS14 W22
BI_ADDRESS15 W23
BI_ADDRESS16 V21
BI_ADDRESS17 V22
BI_ADDRESS18 U21
BI_ADDRESS19 U22
BI_ADDRESS20 U23
BI_ADDRESS21 T21
BI_ADDRESS22 P20
BI_ADDRESS23 R23
BI_ADDRESS24 P21
BI_ADDRESS25 P22
BI_ADDRESS26 N21
BI_ADDRESS27 N22
BI_ADDRESS28 N23
BI_ADDRESS29 M21
BI_ADDRESS30 M22
BI_ADDRESS31_WBE1 M23
PL
B
IBM39STBx25xx
STBx25xx Digital Set-Top Box Integrated Controllers Preliminary
Product Overview
Page 44 of 890Stbx25_Overview.fm.02
May 31, 2002- IBM Confidential
BI_CS0 D21
BI_CS1 C22
BI_CS2 B23
BI_CS3 A22
BI_DATA0 L23
BI_DATA1 L22
BI_DATA10 G23
BI_DATA11 G22
BI_DATA12 G21
BI_DATA13 F22
BI_DATA14 E23
BI_DATA15 E22
BI_DATA2 L21
BI_DATA3 K21
BI_DATA4 K20
BI_DATA5 J23
BI_DATA6 J22
BI_DATA7 J21
BI_DATA8 H23
BI_DATA9 H22
BI_OE B20
BI_READY D23
BI_RW E21
BI_WBE0 C23
CI_CLOCK B5
CI_DATA0 B19
CI_DATA1 B18
CI_DATA2 C16
CI_DATA3 A16
CI_DATA4 A12
CI_DATA5 D14
CI_DATA6 B14
CI_DATA7 B12
CI_DATA_ENABLE C6
CLK_GNDA AC9
CLK_VDDA AA11
DAC1_AGND0 B7
Table 1-1. Signals Sorted by Signal Name
I/O Signal Name Ball Number
IBM39STBx25xx
Preliminary STBx25xx Digital Set-Top Box Integrated Controllers
Stbx25_Overview.fm.02May 31, 2002- IBM Confidential
Product Overview
Page 45 of 890
DAC1_AGND1 A8
DAC1_AGND2 C10
DAC1_AVDD0 B6
DAC1_AVDD1 C8
DAC1_AVDD2 A9
DAC1_AVDD3 B11
DAC1_VOUT1 C7
DAC1_CREF_OUT A5
DAC1_VOUT2 B8
DAC1_GREF_OUT A11
DAC1_VOUT3 C11
DAC1_RREF_OUT A7
DAC1_VREF_IN C9
DAC2_AGND0 B17
DAC2_AGND1 B15
DAC2_AGND2 C13
DAC2_AVDD0 C18
DAC2_AVDD1 B16
DAC2_AVDD2 C14
DAC2_AVDD3 A13
DAC2_VOUT1 C17
DAC2_CREF_OUT A19
DAC2_VOUT2 C15
DAC2_GREF_OUT C12
DAC2_VOUT3 B13
DAC2_RREF_OUT A17
DAC2_VREF_IN A15
DA_BIT_CLOCK AA1
DA_LR_CLOCK AA2
DA_OS_CLOCK AB1
DA_SERIAL_DATA Y2
DA_SPDIF F20
EDMAC3_ACK/DMACK V3
EDMAC3_REQ/DMARQ E3
GND A01
GND A06
GND A10
Table 1-1. Signals Sorted by Signal Name
I/O Signal Name Ball Number
IBM39STBx25xx
STBx25xx Digital Set-Top Box Integrated Controllers Preliminary
Product Overview
Page 46 of 890Stbx25_Overview.fm.02
May 31, 2002- IBM Confidential
GND A14
GND A18
GND A23
GND AA3
GND AB2
GND AC1
GND AC6
GND B02
GND B22
GND C03
GND C21
GND D04
GND D08
GND D12
GND D16
GND D20
GND F01
GND F23
GND H04
GND H20
GND K01
GND K23
GND M04
GND M20
GND P01
GND P23
GND T04
GND T20
GND V01
GND V23
GND Y04
GND Y08
GND Y12
GND Y16
GND Y20
GND AA21
GND AA23
Table 1-1. Signals Sorted by Signal Name
I/O Signal Name Ball Number
IBM39STBx25xx
Preliminary STBx25xx Digital Set-Top Box Integrated Controllers
Stbx25_Overview.fm.02May 31, 2002- IBM Confidential
Product Overview
Page 47 of 890
GND AB22
GND AC10
GND AC14
GND AC18
GND AC23
GPIO0 AC2
GPIO1 Y6
GPIO10 R2
GPIO11 V4
GPIO12 W3
GPIO13 B10
GPIO14 D10
GPIO15 B9
GPIO16 D6
GPIO17 C5
GPIO18 A4
GPIO19 B4
GPIO2 AB5
GPIO20 A3
GPIO21 C4
GPIO22 B3
GPIO23 A2
GPIO24 K22
GPIO25 Y22
GPIO26 Y21
GPIO27 AA6
GPIO28 F21
GPIO29 R22
GPIO3 AC5
GPIO30 K4
GPIO31 AB15
GPIO4 C19
GPIO5 B21
GPIO6 A20
GPIO7 D18
GPIO8 M1
GPIO9 N3
Table 1-1. Signals Sorted by Signal Name
I/O Signal Name Ball Number
IBM39STBx25xx
STBx25xx Digital Set-Top Box Integrated Controllers Preliminary
Product Overview
Page 48 of 890Stbx25_Overview.fm.02
May 31, 2002- IBM Confidential
I2C0_SCL T3
I2C0_SDA U3
INT0 C1
INT1 D2
INT2 H21
RW_HALT W2
RW_TCK AB6
RW_TDI AC4
RW_TDO Y1
RW_TMS AB3
RW_TRST Y3
SC0_CLK AA9
SC0_DETECT AB4
SC0_IO AB8
SC0_RESET AC8
SC0_VCC C20
SC1_CLK R21
SC1_DETECT T22
SC1_IO D22
SC1_RESET T23
SC1_VCC A21
SD0_ADDRESS0 M3
SD0_ADDRESS1 M2
SD0_ADDRESS10 T2
SD0_ADDRESS11 U1
SD0_ADDRESS12 U2
SD0_ADDRESS13 V2
SD0_ADDRESS14 W1
SD0_ADDRESS2 N1
SD0_ADDRESS3 N2
SD0_ADDRESS4 P2
SD0_ADDRESS5 P3
SD0_ADDRESS6 P4
SD0_ADDRESS7 R1
SD0_ADDRESS8 R3
SD0_ADDRESS9 T1
SD0_CAS L3
Table 1-1. Signals Sorted by Signal Name
I/O Signal Name Ball Number
IBM39STBx25xx
Preliminary STBx25xx Digital Set-Top Box Integrated Controllers
Stbx25_Overview.fm.02May 31, 2002- IBM Confidential
Product Overview
Page 49 of 890
SD0_CLK J1
SD0_CS0 J2
SD0_DATA0 B1
SD0_DATA1 C2
SD0_DATA10 G2
SD0_DATA11 G1
SD0_DATA12 H3
SD0_DATA13 H2
SD0_DATA14 H1
SD0_DATA15 J3
SD0_DATA2 D3
SD0_DATA3 D1
SD0_DATA4 F4
SD0_DATA5 E2
SD0_DATA6 E1
SD0_DATA7 F3
SD0_DATA8 F2
SD0_DATA9 G3
SD0_DQMH L2
SD0_DQML L1
SD0_RAS K2
SD0_WE K3
SD1_ADDRESS0 AA17
SD1_ADDRESS1 AB18
SD1_ADDRESS10 AA20
SD1_ADDRESS11 AB21
SD1_ADDRESS12 AC22
SD1_ADDRESS13 AB23
SD1_ADDRESS14 AA22
SD1_ADDRESS2 AA18
SD1_ADDRESS3 AC19
SD1_ADDRESS4 AB19
SD1_ADDRESS5 Y18
SD1_ADDRESS6 AA19
SD1_ADDRESS7 AC20
SD1_ADDRESS8 AB20
SD1_ADDRESS9 AC21
Table 1-1. Signals Sorted by Signal Name
I/O Signal Name Ball Number
IBM39STBx25xx
STBx25xx Digital Set-Top Box Integrated Controllers Preliminary
Product Overview
Page 50 of 890Stbx25_Overview.fm.02
May 31, 2002- IBM Confidential
SD1_CAS AA16
SD1_CLK AA15
SD1_CS0 AC15
SD1_DATA0 AA7
SD1_DATA1 AB7
SD1_DATA10 AC13
SD1_DATA11 AB13
SD1_DATA12 AA13
SD1_DATA13 AB14
SD1_DATA14 AA14
SD1_DATA15 Y14
SD1_DATA2 AB9
SD1_DATA3 Y10
SD1_DATA4 AA10
SD1_DATA5 AB10
SD1_DATA6 AB11
SD1_DATA7 AC11
SD1_DATA8 AB12
SD1_DATA9 AC12
SD1_DQMH AC17
SD1_DQML AB17
SD1_RAS AB16
SD1_WE AC16
SYSTEM_RESET AA4
VDD D09
VDD D11
VDD D13
VDD D15
VDD J04
VDD J20
VDD L04
VDD L20
VDD N04
VDD N20
VDD R04
VDD R20
VDD Y09
Table 1-1. Signals Sorted by Signal Name
I/O Signal Name Ball Number
IBM39STBx25xx
Preliminary STBx25xx Digital Set-Top Box Integrated Controllers
Stbx25_Overview.fm.02May 31, 2002- IBM Confidential
Product Overview
Page 51 of 890
VDD Y11
VDD Y13
VDD Y15
VDD2 D05
VDD2 D07
VDD2 D17
VDD2 D19
VDD2 E04
VDD2 E20
VDD2 G04
VDD2 G20
VDD2 U04
VDD2 U20
VDD2 W04
VDD2 W20
VDD2 Y05
VDD2 Y07
VDD2 Y17
VDD2 Y19
Table 1-1. Signals Sorted by Signal Name
I/O Signal Name Ball Number
IBM39STBx25xx
Preliminary STBx25xx Digital Set-Top Box Integrated Controllers
Stbx25_Overview.fm.02May 31, 2002- IBM Confidential
Product Overview
Page 73 of 890
1.10 Mechanical Information
Package Diagram
M
Top of Package (BGA Side Down)
OEM P/N
0.15
C
C
0.25 C
E52PSUBSTRATE
CuSTIFFENER
(304X ∅ 0. 0.15 SOLDER BALL
C
∅ 0.30
∅ 0.10
C A B
M
GLOBTOP
IBM P/N
XXXXXXX
Date Code
IBM39 STBx25xx xxx xxx
PowerPC
Digital Set-Top BoxIntegrated Controller
ZZWWMMMM
Bottom of Package (BGA Side Up)
123456789
1011121314151617181920212223
15.5
A
.050
1.271.1
27.94
1.22
31
.610
12.75 [0,502]
AC
AB
AAYWVUTRPNMLKJHGFEDCBA
E11005L287501
12.75 [0,502]
15.5
B
.050
1.27 1.1
27.94
1.22
31
.610 0. 20/. 008
Cavity
Data Sheet
2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose FlashSST39LF200A / SST39LF400A / SST39LF800ASST39VF200A / SST39VF400A / SST39VF800A
5©2001 Silicon Storage Technology, Inc. S71117-04-000 6/01 360
FIGURE 1: PIN ASSIGNMENTS FOR 48-LEAD TSOP
Y-Decoder
I/O Buffers and Data Latches
360 ILL B1.2
Address Buffer & Latches
X-Decoder
DQ15 - DQ0
Memory Address
OE#
CE#
WE#
SuperFlashMemory
Control Logic
FUNCTIONAL BLOCK DIAGRAM
A15A14A13A12A11A10
A9A8NCNC
WE#NCNCNCNCNCNCA7A6A5A4A3A2A1
123456789101112131415161718192021222324
A16NCVSSDQ15DQ7DQ14DQ6DQ13DQ5DQ12DQ4VDDDQ11DQ3DQ10DQ2DQ9DQ1DQ8DQ0OE#VSSCE#A0
484746454443424140393837363534333231302928272625
360 ILL F01.2
Standard Pinout
Top View
Die Up
SST39LF200A/400A/800ASST39VF200A/400A/800A
SST39LF/VF200A
A15A14A13A12A11A10
A9A8NCNC
WE#NCNCNCNCNC
A17A7A6A5A4A3A2A1
SST39LF/VF400A
A15A14A13A12A11A10
A9A8NCNC
WE#NCNCNCNC
A18A17
A7A6A5A4A3A2A1
SST39LF/VF800A SST39LF/VF200A
A16NCVSSDQ15DQ7DQ14DQ6DQ13DQ5DQ12DQ4VDDDQ11DQ3DQ10DQ2DQ9DQ1DQ8DQ0OE#VSSCE#A0
SST39LF/VF400A
A16NCVSSDQ15DQ7DQ14DQ6DQ13DQ5DQ12DQ4VDDDQ11DQ3DQ10DQ2DQ9DQ1DQ8DQ0OE#VSSCE#A0
SST39LF/VF800A
1
Features• Low-Voltage and Standard-Voltage Operation
– 5.0 (VCC = 4.5V to 5.5V)– 2.7 (VCC = 2.7V to 5.5V)– 2.5 (VCC = 2.5V to 5.5V)– 1.8 (VCC = 1.8V to 5.5V)
• Internally Organized 128 x 8 (1K), 256 x 8 (2K), 512 x 8 (4K),1024 x 8 (8K) or 2048 x 8 (16K)
• 2-Wire Serial Interface• Schmitt Trigger, Filtered Inputs for Noise Suppression• Bidirectional Data Transfer Protocol• 100 kHz (1.8V, 2.5V, 2.7V) and 400 kHz (5V) Compatibility• Write Protect Pin for Hardware Data Protection• 8-Byte Page (1K, 2K), 16-Byte Page (4K, 8K, 16K) Write Modes • Partial Page Writes Are Allowed• Self-Timed Write Cycle (10 ms max)• High Reliability
– Endurance: 1 Million Write Cycles– Data Retention: 100 Years– ESD Protection: >3000V
• Automotive Grade and Extended Temperature Devices Available• 8-Pin and 14-Pin JEDEC SOIC, 8-Pin PDIP, 8-Pin MSOP, and 8-Pin TSSOP Packages
DescriptionThe AT24C01A/02/04/08/16 provides 1024/2048/4096/8192/16384 bits of serial elec-trically erasable and programmable read only memory (EEPROM) organized as128/256/512/1024/2048 words of 8 bits each. The device is optimized for use in manyindustrial and commercial applications where low power and low voltage operation areessential. The AT24C01A/02/04/08/16 is available in space saving 8-pin PDIP,(AT24C01A/02/04/08/16) , 8-P in MSOP (AT24C01A/02) , 8 -Pin TSSOP(AT24C01A/02 /04 /08 /16 ) , and 8 -P in and 14 -P in JEDEC SOIC(AT24C01A/02/04/08/16) packages and is accessed via a 2-wire serial interface. Inaddition, the entire family is available in 5.0V (4.5V to 5.5V), 2.7V (2.7V to 5.5V), 2.5V(2.5V to 5.5V) and 1.8V (1.8V to 5.5V) versions.
2-WireSerial EEPROM1K (128 x 8)
2K (256 x 8)
4K (512 x 8)
8K (1024 x 8)
16K (2048 x 8)
AT24C01AAT24C02AT24C04AT24C08AT24C16
Rev. 0180D–10/98
Pin ConfigurationsPin Name Function
A0 - A2 Address Inputs
SDA Serial Data
SCL Serial Clock Input
WP Write Protect
NC No Connect
14-Pin SOIC
1234567
1413121110
98
NCA0A1NCA2
GNDNC
NCVCCWPNCSCLSDANC
8-Pin SOIC
1234
8765
A0A1A2
GND
VCCWPSCLSDA
8-Pin PDIP
1234
8765
A0A1A2
GND
VCCWPSCLSDA
8-Pin TSSOP
1234
8765
A0A1A2
GND
VCCWPSCLSDA
8-Pin MSOP
1234
8765
A0A1A2
GND
VCCWPSCLSDA
K4S641632D
Rev. 0.3 June 2000
CMOS SDRAM
VDDDQ0
VDDQDQ1DQ2VSSQDQ3DQ4
VDDQDQ5DQ6VSSQDQ7VDD
LDQMWE
CASRAS
CSBA0BA1
A10/APA0A1A2A3
VDD
123456789101112131415161718192021222324252627
545352515049484746454443424140393837363534333231302928
PIN CONFIGURATION (Top view)
VSSDQ15VSSQDQ14DQ13VDDQDQ12DQ11VSSQDQ10DQ9VDDQDQ8VSSN.C/RFUUDQMCLKCKEN.CA11A9A8A7A6A5A4VSS
54Pin TSOP (II)(400mil x 875mil)(0.8 mm Pin pitch)
PIN FUNCTION DESCRIPTION
Pin Name Input Function
CLK System clock Active on the positive going edge to sample all inputs.
CS Chip select Disables or enables device operation by masking or enabling all inputs except CLK, CKE and L(U)DQM
CKE Clock enableMasks system clock to freeze operation from the next clock cycle.CKE should be enabled at least one cycle prior to new command.Disable input buffers for power down in standby.
A0 ~ A11 Address Row/column addresses are multiplexed on the same pins.Row address : RA0 ~ RA11, Column address : CA0 ~ CA7
BA0 ~ BA1 Bank select address Selects bank to be activated during row address latch time.Selects bank for read/write during column address latch time.
RAS Row address strobe Latches row addresses on the positive going edge of the CLK with RAS low.Enables row access & precharge.
CAS Column address strobe Latches column addresses on the positive going edge of the CLK with CAS low.Enables column access.
WE Write enable Enables write operation and row precharge.Latches data in starting from CAS, WE active.
L(U)DQM Data input/output mask Makes data output Hi-Z, tSHZ after the clock and masks the output.Blocks data input when L(U)DQM active.
DQ0 ~ 15 Data input/output Data inputs/outputs are multiplexed on the same pins.
VDD/VSS Power supply/ground Power and ground for the input buffers and the core logic.
VDDQ/VSSQ Data output power/ground Isolated power supply and ground for the output buffers to provide improved noise immunity.
N.C/RFU No connection/reserved for future use
This pin is recommended to be left No Connection on the device.
LD1117 SERIES
3/24
CONNECTION DIAGRAM (top view)
NOTE: The TAB is connected to the VOUT.
ORDERING CODES
SOT-223 SO-8 DPAK TO-220 TO-220FM OUTPUTVOLTAGE
LD1117S12 LD1117D12 (*) LD1117DT12 LD1117V12 (*) LD1117F12 (*) 1.2 V
LD1117S18 LD1117D18 LD1117DT18 LD1117V18 LD1117F18 1.8 VLD1117S18C LD1117D18C LD1117DT18C LD1117V18C LD1117F18C 1.8 VLD1117S25 LD1117D25 LD1117DT25 LD1117V25 LD1117F25 2.5 V
LD1117S25C LD1117D25C LD1117DT25C LD1117V25C LD1117F25C 2.5 VLD1117S28 LD1117D28 LD1117DT28 LD1117V28 LD1117F28 2.85 VLD1117S30 LD1117D30 LD1117DT30 LD1117V30 LD1117F30 3 V
LD1117S30C LD1117D30C LD1117DT30C LD1117V30C LD1117F30C 3 VLD1117S33 LD1117D33 LD1117DT33 LD1117V33 LD1117F33 3.3 V
LD1117S33C LD1117D33C LD1117DT33C LD1117V33C LD1117F33C 3.3 VLD1117S50 LD1117D50 LD1117DT50 LD1117V50 LD1117F50 5 V
LD1117S50C LD1117D50C LD1117DT50C LD1117V50C LD1117F50C 5 V
LD1117S LD1117D LD1117DT LD1117V LD1117F ADJUSTABLEFROM 1.25 TO
15VLD1117SC LD1117DC LD1117DTC LD1117VC LD1117FC ADJUSTABLE
FROM 1.25 TO15V
SOT-223 SO-8
TO-220FM
DPAK
TO-220
MIC39100/39101/39102 Micrel
MIC39100/39101/39102 2 June 2000
Pin Configuration
IN OUTGND1 32
TAB
GND
MIC39100-x.xFixed
SOT-223 (S)
1EN
IN
OUT
FLG
8 GND
GND
GND
GND
7
6
5
2
3
4
MIC39101-x.xFixed
SOP-8 (M)
1EN
IN
OUT
ADJ
8 GND
GND
GND
GND
7
6
5
2
3
4
MIC39102AdjustableSOP-8 (M)
Pin DescriptionPin No. Pin No. Pin No. Pin Name Pin Function
MIC39100 MIC39101 MIC39102
1 1 1 EN Enable (Input): CMOS-compatible control input. Logic high = enable, logiclow or open = shutdown.
2 2 IN Supply (Input)
3 3 3 OUT Regulator Output
4 FLG Flag (Output): Open-collector error flag output. Active low = output under-voltage.
4 ADJ Adjustment Input: Feedback input. Connect to resitive voltage-dividernetwork.
2, TAB 5–8 5–8 GND Ground
CONNECTION DIAGRAM AND ORDERING NUMBERS (top view)
ORDERING NUMBERSType SO-8 TO-92 SOT-89 (T&R) Output Voltage
L78L33ACL78L33ABL78L05CL78L05ACL78L05ABL78L06CL78L06ACL78L06ABL78L08CL78L08ACL78L08ABL78L09CL78L09ACL78L09ABL78L12CL78L12ACL78L12ABL78L15CL78L15ACL78L15ABL78L18CL78L18ACL78L18ABL78L24CL78L24ACL78L24AB
L78L33ACDL78L33ABDL78L05CDL78L05ACDL78L05ABDL78L06CDL78L06ACDL78L06ABDL78L08CDL78L08ACDL78L08ABDL78L09CDL78L09ACDL78L09ABDL78L12CDL78L12ACDL78L12ABDL78L15CDL78L15ACDL78L15ABDL78L18CDL78L18ACDL78L18ABDL78L24CDL78L24ACDL78L24ABD
L78L33ACZL78L33ABZL78L05CZL78L05ACZL78L05ABZL78L06CZL78L06ACZL78L06ABZL78L08CZL78L08ACZL78L08ABZL78L09CZL78L09ACZL78L09ABZL78L12CZL78L12ACZL78L12ABZL78L15CZL78L15ACZL78L15ABZL78L18CZL78L18ACZL78L18ABZL78L24CZL78L24ACZL78L24ABZ
L78L33ACUTRL78L33ABUTR
L78L05ACUTRL78L05ABUTR
L78L06ACUTRL78L06ABUTR
L78L08ACUTRL78L08ABUTR
L78L09ACUTRL78L09ABUTR
L78L12ACUTRL78L12ABUTR
L78L15ACUTRL78L15ABUTR
L78L18ACUTRL78L18ABUTR
L78L24ACUTRL78L24ABUTR
3.3 V3.3 V5 V5 V5 V6 V6 V6 V8 V8 V8 V9 V9 V9 V
12 V12 V12 V15 V15 V15 V18 V18 V18 V24 V24 V24 V
SO-8 TO-92
pin 1 = VOUT
pin 2 = GNDpin 3 = VIN
BOTTOM VIEW
SOT-89
L78L00
3/19
MA
X2
20
–MA
X2
49
+5V-Powered, Multichannel RS-232Drivers/Receivers
______________________________________________________________________________________ 17
TOP VIEW
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
VCC
GND
T1OUT
R1INC2+
C1-
V+
C1+
MAX220MAX232
MAX232A R1OUT
T1IN
T2IN
R2OUTR2IN
T2OUT
V-
C2-
DIP/SO
V+
V-
2 +10VC1+C1
C2
1
34
5
11
10
12
9
6
14
7
13
8
T1IN
R1OUT
T2IN
R2OUT
T1OUT
R1IN
T2OUT
R2IN
+5V INPUT
C2+ -10V
C4
RS-232OUTPUTS
RS-232INPUTS
TTL/CMOSINPUTS
TTL/CMOSOUTPUTS
GND15
5k
5k
400k
400k+5V
+5V
+10V TO -10VVOLTAGE INVERTER
+5V TO +10VVOLTAGE DOUBLER
16
C3
C5
CAPACITANCE (µF)DEVICEMAX220MAX232MAX232A
C14.71.00.1
C24.71.00.1
C3101.00.1
C4101.00.1
C54.71.00.1
C2-
C1-
VCC
5k
DIP/SO
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
SHDN
VCC
GND
T1OUTC1-
V+
C1+
(N.C.) EN
R1IN
R1OUT
T1IN
T2INT2OUT
V-
C2-
C2+
109 R2OUTR2IN
MAX222MAX242
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
SHDN
VCC
GND
T1OUTC1-
V+
C1+
(N.C.) EN
N.C.
R1IN
R1OUT
N.C.T2OUT
V-
C2-
C2+
12
11
9
10
T1IN
T2INR2OUT
R2IN
MAX222MAX242
SSOP
( ) ARE FOR MAX222 ONLY.PIN NUMBERS IN TYPICAL OPERATING CIRCUIT ARE FOR DIP/SO PACKAGES ONLY.
V+
V-
3 +10VC1
C2
2
45
6
12
11
13
7
15
8
14
9
T1IN
R1OUT
T2IN
R2OUT
T1OUT
R1IN
T2OUT
R2IN
+5V INPUT
C2+ -10V
C4
RS-232OUTPUTS
RS-232INPUTS
TTL/CMOSINPUTS
TTL/CMOSOUTPUTS
GND16
5k
400k
400k+5V
+5V
+10V TO -10VVOLTAGE INVERTER
VCC+5V TO +10V
VOLTAGE DOUBLER
17
C3
C5
1
10
18SHDN
EN(N.C.)
ALL CAPACITORS = 0.1µF
C2-
C1+C1-
TOP VIEW
Figure 5. MAX220/MAX232/MAX232A Pin Configuration and Typical Operating Circuit
Figure 6. MAX222/MAX242 Pin Configurations and Typical Operating Circuit
HEXFET® Power MOSFET
PD - 9.1239D
l Generation V Technologyl Ultra Low On-Resistancel Dual N-Channel Mosfetl Surface Mountl Available in Tape & Reell Dynamic dv/dt Ratingl Fast SwitchingDescriptionFifth Generation HEXFETs from International Rectifierutilize advanced processing techniques to achievethe lowest possible on-resistance per silicon area.This benefit, combined with the fast switching speedand ruggedized device design that HEXFET PowerMOSFETs are well known for, provides the designerwith an extremely efficient device for use in a widevariety of applications.
The SO-8 has been modified through a customizedleadframe for enhanced thermal characteristics andmultiple-die capability making it ideal in a variety ofpower applications. With these improvements,multiple devices can be used in an application withdramatically reduced board space. The package isdesigned for vapor phase, infra red, or wave solderingtechniques. Power dissipation of greater than 0.8Wis possible in a typical PCB mount application.
IRF7303
SO-8
D1
D 1
D2
D 2
G 1
S 2
G 2
S 1
Top View
81
2
3
4 5
6
7
Parameter Max. UnitsID @ TA = 25°C 10 Sec. Pulsed Drain Current, VGS @ 10V 5.3ID @ TA = 25°C Continuous Drain Current, VGS @ 10V 4.9ID @ TA = 70°C Continuous Drain Current, VGS @ 10V 3.9IDM Pulsed Drain Current 20PD @TA = 25°C Power Dissipation 2.0 W
Linear Derating Factor 0.016 W/°CVGS Gate-to-Source Voltage ± 20 Vdv/dt Peak Diode Recovery dv/dt 5.0 V/nsTJ, TSTG Junction and Storage Temperature Range -55 to + 150 °C
Absolute Maximum Ratings
A
VDSS = 30V
RDS(on) = 0.050Ω
8/25/97
Thermal Resistance RatingsParameter Typ. Max. Units
RθJA Maximum Junction-to-Ambient ––– 62.5 °C/W
1999 Nov 11 6
Philips Semiconductors Preliminary specification
Low power audio DAC UDA1334TS
7 PINNING
Notes
1. 5 V tolerant is only supported if the power supply voltage is between 2.7 and 3.6 V. For lower power supply voltagesthis is maximum 3.3 V tolerant.
2. Because of test issues these pads are not 5 V tolerant and they should be at power supply voltage level or at amaximum of 0.5 V above that level.
SYMBOL PIN PAD TYPE DESCRIPTION
BCK 1 5 V tolerant digital input pad; note 1 bit clock input
WS 2 5 V tolerant digital input pad; note 1 word select input
DATAI 3 5 V tolerant digital input pad; note 1 serial data input
VDDD 4 digital supply pad digital supply voltage
VSSD 5 digital ground pad digital ground
SYSCLK 6 5 V tolerant digital input pad; note 1 system clock input
SFOR1 7 5 V tolerant digital input pad; note 1 serial format select 1
MUTE 8 5 V tolerant digital input pad; note 1 mute control
DEEM 9 5 V tolerant digital input pad; note 1 de-emphasis control
PCS 10 3-level input pad; note 2 power control and sampling frequency select
SFOR0 11 digital input pad; note 2 serial format select 0
Vref(DAC) 12 analog pad DAC reference voltage
VDDA 13 analog supply pad DAC analog supply voltage
VOUTL 14 analog output pad DAC output left
VSSA 15 analog ground pad DAC analog ground
VOUTR 16 analog output pad DAC output right
handbook, halfpage
UDA1334TS
MGL878
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VOUTRBCK
VSSAWS
VOUTLDATAI
VDDAVDDD
Vref(DAC)VSSD
SFOR0SYSCLK
PCSSFOR1
DEEMMUTE
Fig.2 Pin configuration.
PIN LIST
Pin Number Symbol Description1 VCC +5V Supply2 CVBSIN_AUX CVBS Input, from Aux3 DEC Decoupling Capacitor4 Y/CVBSIN_ENC Y/CVBS Input, from Encoder5 GND Ground6 YIN_ENC Y Input, from Encoder7 RIN_AUX Audio Right Input, from Aux8 CIN_ENC Chroma Input, from Encoder9 LIN_AUX Audio Left, Input from Aux10 R/CIN_ENC Red/Chroma Input, from Encoder11 RIN_ENC Audio Right, Input from Encoder12 GIN_ENC Green Input, from Encoder13 LIN_ENC Audio Left, Input from Encoder14 BIN_ENC Blue Input, from Encoder15 NC Not Connected16 VREF Reference Voltage Decoupling
6412
-01.
TBL
CONFIDENTIAL
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
3216151413121110987654321
33343536373839404142434445464748GND
LOU
T_T
V
CV
BS
IN_A
UX
VC
C
DE
C
Y/C
VB
SIN
_EN
C
GN
D
YIN
_EN
C
RIN
_AU
X
C_E
NC
LIN_A
UX
R/C
IN_E
NC
RIN
_EN
C
GIN
_EN
C
LIN_E
NC
BIN
_EN
C
NC
VR
EF
GNDA
VCCA
NC
ROUT_CINCH
LOUT_CINCH
ROUT_VCR
LOUT_VCR
RIN_TV
LIN_TV
CVBSIN_TV
RIN_VCR
LIN_VCR
Y/CVBSIN_VCR
VCCAO
ROUT_TVF
ILTE
R
AO
UT
_RF
VO
UT
_RF
VC
CB
5
BO
UT
_TV
VC
CB
4
GO
UT
_TV
GN
DB
R/C
OU
T_T
V
VC
CB
3
VC
CB
2
VC
CB
1
Y/C
VB
SO
UT
_TV
CO
UT
_VC
R
Y/C
VB
SO
UT
_VC
R
FBIN_ENC
C_GATE
VDD
ADD
SCL
SDA
GND
IT_OUT
SLB_TV
R/C_VCR
SLB_VCR
G_VCR
VCC12
B_VCR
FBOUT_TV
FBIN_VCR
6412
-01.
EP
S
PIN CONNECTIONS
STV6412
2/16
CONFIDENTIAL
Pin Number Symbol Description17 GND Ground18 Y/CVBSIN_VCR Y/CVBS Input, from VCR scart19 LIN_VCR Audio Left, Input from VCR scart20 RIN_VCR Audio Right, Input from VCR scart21 CVBSIN_TV CVBS Input, from TV scart22 LIN_TV Audio Left, Input from TV scart23 RIN_TV Audio Right, Input from TV scart24 VCCA Audio Supply Voltage - or - Audio Supply Decoupling25 GNDA Audio Ground26 NC Not Connected27 ROUT_CINCH Audio Right Output, to Cinch28 LOUT_CINCH Audio Left Output, to Cinch29 ROUT_VCR Audio Right Output, to VCR scart30 LOUT_VCR Audio Left Output, to VCR scart31 VCCAO Audio Outputs Supply Voltage - or - Main Audio Supply Voltage32 ROUT_TV Audio Right Output, to TV scart33 LOUT_TV Audio Left Output, to TV scart34 FILTER Chroma Trap Filter35 AOUT_RF Audio(L+R) Output to RF Modulator36 VOUT_RF CVBS Video Output to RF Modulator37 VCCB5 Video Output Buffers Supply Pin38 BOUT_TV Blue Output, to TV scart39 VCCB4 Video Output Buffers Supply Pin40 GOUT_TV Green Output, to TV scart41 GNDB Video Buffers Ground42 R/COUT_TV Red/Chroma Output, to TV scart43 VCCB3 Video Output Buffers Supply Pin44 Y/CVBSOUT_TV Y/CVBS Output, to TV scart45 VCCB2 Video Output Buffers Supply Pin46 COUT_VCR Chroma Output, to VCR scart47 VCCB1 Video Output Buffers Supply Pin48 Y/CVBSOUT_VCR Y/CVBS Output, to VCR scart49 FBOUT_TV Fast Blanking Output, to TV scart50 FBIN_VCR Fast Blanking Input, from VCR scart51 FBIN_ENC Fast Blanking Input, from Encoder52 C_GATE External Mos Command for C_VCR bidirectional mode53 VDD +5V I2C Supply54 ADD I2C Address Selection55 SCL I2C Bus Clock56 SDA I2C Bus Data57 GND Ground Digital58 IT_OUT Interrupt Output59 SLB_TV Slow Blanking Input/Output, from TV scart60 R/CIN_VCR Red Input (or C Input), from VCR scart61 SLB_VCR Slow Blanking Input/Output, from VCR scart62 GIN_VCR Green Input, from VCR scart63 VCC12 +12V Supply64 BIN_VCR Blue Input, from VCR scart
6412
-01.
TB
L
PIN LIST (continued)
STV6412
3/16
TSOP48..SB1Vishay Telefunken
1 (7)Rev. 6, 29-Mar-01www.vishay.comDocument Number 82108
Photo Modules for PCM Remote Control Systems
Available types for different carrier frequencies Type fo Type fo
TSOP4830SB1 30 kHz TSOP4833SB1 33 kHz
TSOP4836SB1 36 kHz TSOP4837SB1 36.7 kHz
TSOP4838SB1 38 kHz TSOP4840SB1 40 kHz
TSOP4856SB1 56 kHz
DescriptionThe TSOP48..SB1 – series are miniaturized receiversfor infrared remote control systems. PIN diode andpreamplifier are assembled on lead frame, the epoxypackage is designed as IR filter. The demodulated output signal can directly be de-coded by a microprocessor. TSOP48..SB1 is thestandard IR remote control receiver series, supportingall major transmission codes.
16123
Features Photo detector and preamplifier in one package
Internal filter for PCM frequency
Improved shielding against electrical fielddisturbance
TTL and CMOS compatibility
Output active low
Low power consumption
High immunity against ambient light
Continuous data transmission possible (800 bit/s)
Suitable burst length ≥10 cycles/burst
Block Diagram
9612226
PIN
Input
AGC
ControlCircuit
BandPass
Demodu-lator
30 k
2
3
1
VS
OUT
GND
TSOP48..SB1Vishay Telefunken
Rev. 6, 29-Mar-01www.vishay.com Document Number 821086 (7)
Dimensions in mm
16777
1
Data sheet acquired from Harris SemiconductorSCHS155A
Features• Buffered Inputs
• Asynchronous Master Reset
• Typical f MAX = 50MHz at VCC = 5V, CL = 15pF,TA = 25oC
• Fanout (Over Temperature Range)- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55 oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTLLogic ICs
• HC Types- 2V to 6V Operation- High Noise Immunity: N IL = 30%, NIH = 30% of VCC
at VCC = 5V
• HCT Types- 4.5V to 5.5V Operation- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)- CMOS Input Compatibility, I l ≤ 1µA at VOL, VOH
DescriptionThe ’HC164 and ’HCT164 are 8-bit serial-in parallel-out shiftregisters with asynchronous reset. Data is shifted on thepositive edge of Clock (CP). A LOW on the Master Reset(MR) pin resets the shift register and all outputs go to theLOW state regardless of the input conditions. Two SerialData inputs (DS1 and DS2) are provided, either one can beused as a Data Enable control.
PinoutCD54HC164, CD54HCT164
(CERDIP)CD74HC164, CD74HCT164
(PDIP, SOIC)TOP VIEW
Ordering Information
PART NUMBERTEMP. RANGE
(oC) PACKAGE
CD54HC164F -55 to 125 14 Ld CERDIP
CD54HC164F3A -55 to 125 14 Ld CERDIP
CD74HC164E -55 to 125 14 Ld PDIP
CD74HC164M -55 to 125 14 Ld SOIC
CD54HCT164F3A -55 to 125 14 Ld CERDIP
CD74HCT164E -55 to 125 14 Ld PDIP
CD74HCT164M -55 to 125 14 Ld SOIC
NOTE:
1. When ordering, use the entire part number. Add the suffix 96 toobtain the variant in the tape and reel.
2. Wafer and die is available which meets all electricalspecifications. Please contact your local TI sales office orcustomer service for ordering information.
DS1
DS2
Q0
Q1
Q2
Q3
GND
VCC
Q7
Q6
Q5
Q4
MR
CP
1
2
3
4
5
6
7
14
13
12
11
10
9
8
October 1997 - Revised May 2000
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2000, Texas Instruments Incorporated
CD54/74HC164,CD54/74HCT164
High Speed CMOS Logic8-Bit Serial-In/Parallel-Out Shift Register
[ /Title(CD74HC164,CD74HCT164)/Sub-ject(HighSpeedCMOSLogic8-BitSerial-In/Par-allel-
©2001 Fairchild Semiconductor Corporation
www.fairchildsemi.com
Rev. 1.0.4
Features• Programmable output voltage to 36 volts• Low dynamic output impedance 0.20 typical• Sink current capability of 1.0 to 100mA• Equivalent full-range temperature coefficient of 50ppm/
°C typical• Temperature compensated for operation over full rated
operating temperature range• Low output noise voltage• Fast turn-on response
DescriptionThe KA431/KA431A/KA431L are three-terminal adjustableregulator series with a guaranteed thermal stability overapplicable temperature ranges. The output voltage may beset to any value between VREF (approximately 2.5 volts)and 36 volts with two external resistors These devices have atypical dynamic output impedance of 0.2W Active outputcircuitry provides a very sharp turn on characteristic,making these devices excellent replacement for zener diodesin many applications.
TO-92
8-DIP 8-SOP
1. Ref 2. Anode 3. Cathode1
1 1
SOT-23F
1 2
3
1. Cathode 2. Ref 3. Anode
1.Cathode 2.3.6.7.Anode 4.5.NC 8.Ref
1.Cathode 2.3.4.5.7.NC 6.Anode 8.Ref
Internal Block Diagram
KA431/KA431A/KA431LProgrammable Shunt Regulator
©2001 Fairchild Semiconductor Corporation
www.fairchildsemi.com
Rev.1.0.2
Features• Precision fixed operating frequency • KA1L0380B/KA1L0380RB (50KHz) • KA1M0380RB (67KHz)• KA1H0380RB (100KHz)• Pulse by pulse over current limiting• Over load protection• Over voltage protection (Min. 23V) • Internal thermal shutdown function• Under voltage lockout• Internal high voltage sense FET• Auto restart (KA1L0380RB/KA1M0380RB/KA1H0380RB)
DescriptionThe Fairchild Power Switch(FPS) product family is speciallydesigned for an off line SMPS with minimal external components. The Fairchild Power Switch(FPS) consist of highvoltage power SenseFET and current mode PWM controller IC.PWM controller features integrated fixed oscillator, under voltage lock out, leading edge blanking, optimized gate turn-on/turn-off driver, thermal shut down protection, over voltage protection, temperature compensated precision current sourcesfor loop compensation and fault protection circuit. compared todiscrete MOSFET and controller or RCC switching convertersolution, a Fairchild Power Switch(FPS) can reduce total component count, design size, weight and at the same timeincrease & efficiency, productivity, and system reliability. It hasa basic platform well suited for cost effective design in either aflyback converter or a forward converter.
TO-220F-4L
1. GND 2. DRAIN 3. VCC 4. FB
1
Internal Block Diagram
#3 VCC
32V
5µA
9V
2.5R1R
1mA
0.1V+
−
OVER VOLTAGE S/D
+
−
7.5V
25V
Thermal S/D
S
RQ
Power on reset
+
−L.E.B
S
RQ
OSC
5VVref
Internalbias
Goodlogic
SFET#2 DRAIN
#1 GND
#4 FB
KA1L0380B/KA1L0380RB/KA1M0380RB/KA1H0380RBFairchild Power Switch(FPS)
©2001 Fairchild Semiconductor Corporation
www.fairchildsemi.com
Rev.1.0.1
Features• 2A / 3.3V Output low dropout voltage regulator• TO220 Full-Mold package (4PIN)• Overcurrent protection, Thermal shutdown• Overvoltage protection, Short-Circuit protection• With output disable function
DescriptionThe KA278R33 is a low-dropout voltage regulator suitable for various electronic equipments. It provides constant volt-age power source with TO-220 4 lead full mold package. Dropout voltage of KA278R33 is below 0.5V in full rated current(2A). This regulator has various function such as peak current protection, thermal shut down, overvoltage pro-tection and output disable function.
TO-220F-4L
1. Vin 2. Vo 3. GND 4. Vdis
1
Internal Block Diagram
THERMAL SHUTDOWN
BANDGAP REFERENCE
OVERVOLTAGEPROTECTION
SOA PROTECTION
SHORTCIRCUIT PROTECTION
1
4
3
2Vin
Vdis
Vo
GND
HIGH / LOW OUTPUTON / OFF
Q1
R1
R2
-+
-+
1.4VSHORT-CIRCUIT
KA278R33Low Dropout Voltage Regulator
27
A. 2 Schematic Diagram Section < Front Board >
A A
B B
C C
D D
E E
44
33
22
11
KEY1
: PO
WER
ON
KEY2
: C
H U
PKE
Y3 :
CH
DO
WN
KEY4
: VO
L U
PKE
Y5 :
VOL
DO
WN
KEY6
: M
ENU
KEY7
: O
K
CMOS, max. 25mA IOL
FOR SMD, USE min. 150 ohm
STANDBY
REMOTE
TV/SET
FRO
NT
1.0
TFC
B-7K
EY
B
11
Frid
ay, D
ecem
ber 0
5, 2
003
Title
Size
Doc
umen
t Num
ber
Rev
Dat
e:Sh
eet
of
FND
0LE
D0
LED
1LE
D2
LED
3
SEG
0
SEG
6
SEG
4
SEG
1
FND
0
SEG
7
FND
3
SEG
3
FND
2FN
D3
SEG
2
FND
2
FND
1
FND
1
FND
4
SEG
5
L1L6L0 L3 L4 L7L5
FND
4
LED
4
FND
4L3
FND
4L4
L2
FND
4L7
REM
OC
ON
KEY
L2 L3 L4 L5 L6L0 L1
SDAT
A
SCLK
1
SEG
0SE
G1
SEG
2SE
G3
SEG
4SE
G5
SEG
6SE
G7
SDAT
A
SCLK
2
LED
0LE
D1
LED
2LE
D3
LED
4
REM
OC
ON
KEY
SDAT
A
SCLK
1SC
LK2
+5V
+5V
+5V
+5V
+5V
+5V
+5V
R11
10K/
2012
R12
2.2K
/201
2
R10
330/
2012
R13
2.2K
/201
2R
142.
2K/2
012
R15
2.2K
/201
2
U4
74H
CT1
64/D
IP
1 2 8 9
3 4 5 6 10 11 12 1314 7
A B CLK
CLR
QA
QB
QC
QD
QE
QF
QG
QH
VCC
GN
D
R16
2.2K
/201
2
BC3
0.1u
F/20
12
S7 TAC
TJ1 52
67-7
A
1 2 3 4 5 6 7
S4 TAC
T
Q2
KST4
403
2
1 3
Q3
KST4
403
2
1 3
Q4
KST4
403
2
1 3
S5 TAC
T
Q5
KST4
403
2
1 3
R3
150/
2012
BC1
0.1u
F/20
12
R8
150/
2012
R5
150/
2012
R9
150/
2012
R7
150/
2012
U2
TSO
P483
8
1 2 3
OU
T
GN
D
VCC
U1
A-3C
4G
123456789
10111213141516 S1
S2DLES3DPS4NC
NCF
NCCAGB
+C
1
220u
F/6.
3V
R4
150/
2012
R1
150/
2012
R2
150/
2012
Q1
KST4
403
2
1 3
S1 TAC
T
D3
LED
(Y)
21
S2 TAC
T
U3
74H
CT1
64/D
IP
1 2 8 9
3 4 5 6 10 11 12 1314 7
A B CLK
CLR
QA
QB
QC
QD
QE
QF
QG
QH
VCC
GN
D
S3 TAC
T
D1
LED
(R)
21
D2
LED
(G)
21
BC2
0.1u
F/20
12
+C
24.
7uF/
10V
R6
3.3K
/201
2
S6 TAC
T
28
A. 3 Schematic Diagram Section < Main Board >
A A
B B
C C
D D
E E
44
33
22
11
TUN
ER
1.4
TF50
00C
I
117
, 1 3
1, 2
004
토요일
월
Title
Size
Doc
umen
t Num
ber
Rev
Dat
e:S
heet
of
CO
[0..7
]
CD
CLK
OU
T
CD
STA
RT
CD
EN
TUN
ER
RS
T
CD
CLK
OU
T
CO
7
CO
4C
O3
F22K
LNB
PLT
CO
1C
O2
CO
6C
O5
CO
0
TUN
ER
RS
T
CD
STA
RT
CD
EN
LNB
PW
R
LNB
PW
R
F22K
LNB
PLT
+5V
VD
DV
CC
+3.3
V+5
VS
+5V_
LT
+5VT
+5V_
LT
+30V
T
+1.8
VT
+30V
+30V
T
+8V
+5VT
LNB
P17
VLN
BP
24V
+1.8
V
+1.8
VT
+3.3
VT
+3.3
VT
R8
X(4
.7K)
L3
BE
AD
-601
BC
1
0.1u
F
C3
5600
pF/X
7R/2
5V
+
C4
100u
F/16
V
L1C
B20
12P
A60
0L2
CB
2012
PA
600
+C
11
4.7u
F
R5
100
BC
4
0.1u
F
R6
100
U4
PO
LYS
W-R
XE
065
12
U2
LM78
05 w
ith H
eat s
ink
1
2
3
4
VI
GND
VO
HSL5
BE
AD
-601
R1
X(4
.7K
/AX
IAL/
0.25
Wat
t)
+
C10
100u
F/16
VR
410
0
BC
5
0.1u
F
C9
0.1u
F/50
V/2
012
+
C12
X(1
0uF/
16V
(SM
D/3
216)
)
R3
100U
1
SA
MS
UN
G T
BM
U24
311I
PP1 2 3 4 5 7 27 288 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
29 30
6
LNB
A IN
LNB
B O
UT
5V(R
F)A
GC
MO
NIT
OR
5VA VT
IIC D
ATA
IIC C
LK
I Q 5V3.
3V F22
1.8V
RE
SE
TE
RR
OR
OU
TFS
TAR
TV
AIL
DB
CLK D
0
D1
D2
D3
D4
D5
D6
D7
GN
D0
GN
D1
GN
D
L6
BE
AD
-601
/201
2/50
0mA
BC
2
0.1u
F
C6
100p
F
R2
47
+
C5
470u
F/6.
3V
+
C7
47uF
/50V
C1
100p
F
D2
15M
Q04
0N/R
B06
0L-4
0
12
L4
BE
AD
-601
/201
2/50
0mA
R7
X(1K
)
U3 LN
BP
20P
D
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
GN
D0
VC
C1
VC
C2
LNB
AV
SE
LE
NO
SE
LN
C0
NC
1G
ND
1
GN
D3
LNB
B MI
OLF
LLC
EX
TMC
EX
TE
NT
NC
2G
ND
2
R9
X(51
)
BC
30.
1uF
+C
822
0uF/
6.3V
D1
P6K
E30
12
C2
5600
pF/X
7R/2
5V
CO
[0..7
]
CD
EN
CD
STA
RT
TUN
ER
_RS
T
CD
CLK
AS
DA
AS
CLK
LNB
PV
SE
LLN
BP
EN
LNB
PLL
CO
LNB
PE
NT
A A
B B
C C
D D
E E
44
33
22
11
TEST
1.4
TF50
00C
I
B
217
, 1 3
1, 2
004
토요일
월
Title
Size
Doc
umen
t Num
ber
Rev
Dat
e:Sh
eet
of
MD
13
MD
[0..1
5]
MD
10
MA1
2
MD
15
MA6
MD
9
MA9
MA2
MD
6
MA1
8
MD
0
MA1
5
MD
3
MD
12
MA1
4
MA8
MA1
1
MD
14
MD
5
MA2
0
MA5
MD
8
MD
2
MA4
MA1
MD
11
MA1
7
MA[
1..2
1]
MA1
0
MD
7
MA1
3
MA7
MD
1
MA1
6
MD
4
MA1
9
MA3
MO
DEL
_ID
0M
OD
EL_I
D1
MO
DEL
_ID
2
MD
1M
D2
MD
4M
D3
GPI
O[0
..31]
GPI
O0
GPI
O1
GPI
O3
GPI
O17
GPI
O18
GPI
O5
GPI
O24
GPI
O7
GPI
O25
GPI
O10
GPI
O19
GPI
O16
GPI
O23
GPI
O12
GPI
O11
GPI
O6
GPI
O4
GPI
O30
GPI
O27
GPI
O2
+3.3
V
+3.3
V
+3.3
V
+3.3
V
+3.3
V+5
V
R33
2.2K
PR1
2.2K
X4
18
27
36
45
R18
2.2K
R14
2.2K
R19
2.2K
R15
10K
R12
2.2K
R21
2.2K
R17
2.2K
R20
2.2K
R16
10K
R13
2.2K
R27
2.2K
R23
10K
R29
2.2K
R22
10K
R11
2.2K
R28
2.2K
R24
2.2K
R26
10K
R25
10K
JP1
X(52
368-
0401
)
12
34
56
78
910
1112
1314
1516
1718
1920
2122
2324
2526
2728
2930
3132
3334
3536
3738
3940
R30
4.7K
R10
2.2K
R31
2.2K
R36
X(10
0)
R32
2.2K
R34
X(10
0)R
35X(
100)
MA[
1..2
1]
MD
[0..1
5]
RO
MBD
INM
ON
CS
MO
DEL
_ID
0M
OD
EL_I
D1
MO
DEL
_ID
2
GPI
O[0
..31]
A A
B B
C C
D D
E E
44
33
22
11
JUN
O1.
4
TF50
00C
I
C
317
, 1 3
1, 2
004
토요일
월
Title
Size
Doc
umen
t Num
ber
Rev
Dat
e:Sh
eet
of
SD_A
D[0
..14]
SD_D
T[0.
.15]
MA[
1..2
1]
MD
[0..1
5]
SD_D
T15
SD_D
T14
SD_D
T13
SD_D
T12
SD_D
T11
SD_D
T10
SD_D
T9SD
_DT8
SD_D
T7SD
_DT6
SD_D
T5SD
_DT4
SD_D
T3SD
_DT2
SD_D
T1SD
_DT0
SCLK
PWM
GPI
O16
GPI
O17
GPI
O4
GPI
O5
RES
ET
MA2
0M
A19
MA1
8M
A17
MA1
6M
A15
MA1
3M
A14
MA1
2M
A11
MA9
MA1
0
MA5
MA6
MA7
MA8
MA3
MA2
MA1
MA4
MD
14M
D13
MD
12
MD
15
MD
10M
D9
MD
8
MD
11
MD
6M
D5
MD
4
MD
7
MD
2M
D1
MD
0
MD
3
CI2CD3CI2CD4CI2CD5
CI2CD7
CI2
CD
[0..7
]
SD_A
D13
SD_A
D12
SD_A
D11
SD_A
D10
SD_A
D9
SD_A
D8
SD_A
D7
SD_A
D6
SD_A
D5
SD_A
D4
SD_A
D3
SD_A
D2
SD_A
D1
SD_A
D0
CI2CD0CI2CD1CI2CD2
CI2CD6
GPI
O0
GPI
O1
GPI
O2
GPI
O3
GPI
O7
GPI
O10
GPI
O11
GPI
O12
GPI
O14
GPI
O19
GPI
O20
GPI
O21
GPI
O25
GPI
O8
GPI
O27
GPI
O28
GPI
O30
GPI
O31
MA2
1
GPI
O24
GPI
O23
GPI
O22
GPI
O18
GPI
O15
GPI
O6
GPI
O13
GPI
O9
SD_A
D14
GPI
O[0
..31]
XTN
XTN
PWM
SCLK
RESET
+1.8
V+3
.3V
+2.5
V+1.8
V
+1.8
V
+3.3
V
+3.3
V+1
.8V
+3.3
V
+3.3
V+1
.8V
+3.3
V
+3.3
V
+3.3
V
+3.3
V
+3.3
V
BC19
0.1u
F
R56
100K
R39
2.2K
L9 BEAD
-601
R51
47
BC25
0.1u
F
R45
47
BC26
0.1u
F
R46
47
BC24
0.1u
F
R37
47
BC22
0.1u
FBC
180.
1uF
+C
23
220u
F/6.
3V
+C
15
47uF
/16V
BC23
0.1u
F
R57
10K
R47
47
R53
787(
1%)
U5
IBM
39ST
B025
0xPB
A05C
D21
C22 B23
A22
W21 Y2
3V2
0W
22W
23 V21
V22
U21
U22
U23 T21
P20
R23 P21
P22
N21
N22
N23
M21
M22
M23 L23
L22
L21
K21
K20
J23
J22
J21
H23
H22
G23
G22
G21 F22
E23
E22
B5C6B19B18C16A16A12D14B14B12
L3 J1 J2 L2 L1 K2 K3 M3
M2
N1
N2 P2 P3 P4 R1
R3 T1 T2 U1
U2 V2 B1 C2
D3
D1 F4 E2 E1 F3 F2 G3
G2
G1
H3
H2
H1 J3
AB5
AC5
C19
B21
A20
D18
M1
N3
R2
V4 W3
B10
D10
B9 D6
C5
A4 B4 A3 C4
B3 A2 K22
Y22
Y21
AA6
F21
R22
K4 AB15
Y6
AC23AC18
V23Y4Y8Y12Y16Y20AA21AA23AB22AC10AC14
A1A6A10A14A18A23AA3AB2AC1AC6B2B22C3C21D4D8D12D16D20F1F23H4H20K1K23M4M20P1P23T4T20V1
D9D11D13D15J4J20L4L20N4N20R4R20Y9Y11Y13Y15
D5D7D17D19E4E20G4G20U4U20W4W20Y5Y7Y17
AA12
AA4
T3 U3
C1D2H21
AA1
F20
AA2
AB1
Y2 C11
A5 B8A11
C7
C9
A7B6 C8
A9 B11
B7 A8 C10
B13
A19
C15
C12
C17
A17
A15
C18
B16
C14
A13
B17
B15
C13
AA8
AC3
AA9AB4AB8AC8C20
AC7
AA5
B20
D23 E21
C23
AA11
AC9
R21T22D22T23A21
W1
AA16
AA15AC15
AC17AB17
AB16AC16
AA17AB18AA18AC19AB19Y18AA19AC20AB20AC21AA20AB21AC22AB23AA22
AA7AB7AB9Y10AA10AB10AB11AC11AB12AC12AC13AB13AA13AB14AA14Y14
Y19
AC2
V3E3
W2AB6AC4Y1AB3Y3
nBI_
CS0
nBI_
CS1
nBI_
CS2
nBI_
CS3
BI_A
DD
RES
S11
BI_A
DD
RES
S12
BI_A
DD
RES
S13
BI_A
DD
RES
S14
BI_A
DD
RES
S15
BI_A
DD
RES
S16
BI_A
DD
RES
S17
BI_A
DD
RES
S18
BI_A
DD
RES
S19
BI_A
DD
RES
S20
BI_A
DD
RES
S21
BI_A
DD
RES
S22
BI_A
DD
RES
S23
BI_A
DD
RES
S24
BI_A
DD
RES
S25
BI_A
DD
RES
S26
BI_A
DD
RES
S27
BI_A
DD
RES
S28
BI_A
DD
RES
S29
BI_A
DD
RES
S30
BI_A
DD
RES
S31_
WBE
1
BI_D
ATA0
BI_D
ATA1
BI_D
ATA2
BI_D
ATA3
BI_D
ATA4
BI_D
ATA5
BI_D
ATA6
BI_D
ATA7
BI_D
ATA8
BI_D
ATA9
BI_D
ATA1
0BI
_DAT
A11
BI_D
ATA1
2BI
_DAT
A13
BI_D
ATA1
4BI
_DAT
A15
CI_CLOCKCI_DATA_ENABLE
CI_DATA0CI_DATA1CI_DATA2CI_DATA3CI_DATA4CI_DATA5CI_DATA6CI_DATA7
nSD
0_C
ASSD
0_C
LKnS
D0_
CS0
SD0_
DQ
MH
SD0_
DQ
ML
nSD
0_R
ASnS
D0_
WE
SD0_
ADD
RES
S0(M
SB)
SD0_
ADD
RES
S1SD
0_AD
DR
ESS2
SD0_
ADD
RES
S3SD
0_AD
DR
ESS4
SD0_
ADD
RES
S5SD
0_AD
DR
ESS6
SD0_
ADD
RES
S7SD
0_AD
DR
ESS8
SD0_
ADD
RES
S9SD
0_AD
DR
ESS1
0SD
0_AD
DR
ESS1
1SD
0_AD
DR
ESS1
2SD
0_AD
DR
ESS1
3
SD0_
DAT
A0SD
0_D
ATA1
SD0_
DAT
A2SD
0_D
ATA3
SD0_
DAT
A4SD
0_D
ATA5
SD0_
DAT
A6SD
0_D
ATA7
SD0_
DAT
A8SD
0_D
ATA9
SD0_
DAT
A10
SD0_
DAT
A11
SD0_
DAT
A12
SD0_
DAT
A13
SD0_
DAT
A14
SD0_
DAT
A15
GPI
O_2
GPI
O_3
GPI
O_4
GPI
O_5
GPI
O_6
GPI
O_7
GPI
O_8
GPI
O_9
GPI
O_1
0G
PIO
_11
GPI
O_1
2G
PIO
_13
GPI
O_1
4G
PIO
_15
GPI
O_1
6G
PIO
_17
GPI
O_1
8G
PIO
_19
GPI
O_2
0G
PIO
_21
GPI
O_2
2G
PIO
_23
GPI
O_2
4G
PIO
_25
GPI
O_2
6G
PIO
_27
GPI
O_2
8G
PIO
_29
GPI
O_3
0G
PIO
_31
GPI
O_1
GND44GND43
GND32GND33GND34GND35GND36GND37GND38GND39GND40GND41GND42
GND0GND1GND2GND3GND4GND5GND6GND7GND8GND9GND10GND11GND12GND13GND14GND15GND16GND17GND18GND19GND20GND21GND22GND23GND24GND25GND26GND27GND28GND29GND30GND31
VDD18_0VDD18_1VDD18_2VDD18_3VDD18_4VDD18_5VDD18_6VDD18_7VDD18_8VDD18_9VDD18_10VDD18_11VDD18_12VDD18_13VDD18_14VDD18_15
VDD33_0VDD33_1VDD33_2VDD33_3VDD33_4VDD33_5VDD33_6VDD33_7VDD33_8VDD33_9VDD33_10VDD33_11VDD33_12VDD33_13VDD33_14
27M
HZ_
CLK
nSYS
TEM
_RES
ET
I2C
0_SC
LI2
C0_
SDA
nINT0nINT1nINT2
DA_
BIT_
CLO
CK
DA_
SPD
IFD
A_LR
_CLO
CK
DA_
OS_
CLO
CK
DA_
SER
IAL_
DAT
A
DAC
1_VO
UT3
DAC
1_C
REF
_OU
T
DAC
1_VO
UT2
DAC
1_G
REF
_OU
T
DAC
1_VO
UT1
DAC
1_VR
EF_I
N
DAC
1_R
REF
_OU
T
DAC
1_AV
DD
0D
AC1_
AVD
D1
DAC
1_AV
DD
2D
AC1_
AVD
D3
DAC
1_AG
ND
0D
AC1_
AGN
D1
DAC
1_AG
ND
2
DAC
2_VO
UT3
DAC
2_C
REF
_OU
T
DAC
2_VO
UT2
DAC
2_G
REF
_OU
T
DAC
2_VO
UT1
DAC
2_R
REF
_OU
T
DAC
2_VR
EF_I
N
DAC
2_AV
DD
0D
AC2_
AVD
D1
DAC
2_AV
DD
2D
AC2_
AVD
D3
DAC
2_AG
ND
0D
AC2_
AGN
D1
DAC
2_AG
ND
2
AUD
_GN
DA0
AUD
_GN
DA1
SC0_CLKSC0_DETECT
SC0_IOSC0_RESET
SC0_VCC
AUD
_VD
DA0
AUD
_VD
DA1
nBI_
OE
BI_R
EAD
YBI
_RW
nBI_
WBE
0
CLK
_VD
DA
CLK
_GN
DA
SC1_CLKSC1_DETECT
SC1_IOSC1_RESET
SC1_VCC
SD0_
ADD
RES
S14
nSD1_CAS
SD1_CLKnSD1_CS0
SD1_DQMHSD1_DQML
nSD1_RASnSD1_WE
SD1_ADDRESS0(MSB)SD1_ADDRESS1SD1_ADDRESS2SD1_ADDRESS3SD1_ADDRESS4SD1_ADDRESS5SD1_ADDRESS6SD1_ADDRESS7SD1_ADDRESS8SD1_ADDRESS9
SD1_ADDRESS10SD1_ADDRESS11SD1_ADDRESS12SD1_ADDRESS13SD1_ADDRESS14
SD1_DATA0SD1_DATA1SD1_DATA2SD1_DATA3SD1_DATA4SD1_DATA5SD1_DATA6SD1_DATA7SD1_DATA8SD1_DATA9
SD1_DATA10SD1_DATA11SD1_DATA12SD1_DATA13SD1_DATA14SD1_DATA15
VDD33_15GPI
O_0
nEDMAC3_ACKnEDMAC3_REQ
nRW_HALTRW_TCKRW_TDI
RW_TDORW_TMS
nRW_TRST
R48
47
R50
47
R42
47
C18
1nF
BC11
0.1u
F
C19
1nF
U6
X(KA
5SD
KAS0
1TSN
)
8 7 6 5
1 2 3 4
XOU
TVS
S1 NC
CLK
XIN
VDD
XTU
NE
VSS0
R43
CB1
608G
M12
1
+C
14
47uF
/16V
BC7
0.1u
F
L8 BEAD
-601
F1 0/20
121
3
2
SS G
R52
1KVC
XO1
27M
Hz
2
4
13
GND
VCC
VIN
CLK
BC6
0.1u
F
BC20
0.1u
F
BC10
0.1u
F
BC21
0.1u
F
BC8
0.1u
F
R44
47
R55
24
BC9
0.1u
F
+C
13
1uF/
16V
R54
787(
1%)
Y1X(
27M
Hz)
L7 BEAD
-601
BC27
0.1u
FBC
280.
1uF
BC12
0.1u
F
+C
22
220u
F/6.
3V
C16 1n
F
R49
2.2K
BC16
0.1u
F
R41
2K
BC17
0.1u
F
R58
5.1K
C17 1n
F
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29 31 33 35 38 40 42 44 30 32 34 36 39 41 43 45 47
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O9
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O12
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VPP
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NC
NC
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SD_A
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123456789101112
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U19
74H
CT2
57
24
3 57
6 119
10 1412
13 1 15
16 8
1A1Y
1B 2A2Y
2B 3A3Y
3B 4A4Y
4B A/B
G
VCC
GN
D
U23
74H
CT2
45
2 3 4 5 6 7 8 9 19 1
18 17 16 15 14 13 12 11 20 10
A1 A2 A3 A4 A5 A6 A7 A8 GD
IR
B1 B2 B3 B4 B5 B6 B7 B8 VCC
GN
D
U21
74H
CT2
45
2 3 4 5 6 7 8 9 19 1
18 17 16 15 14 13 12 11 20 10
A1 A2 A3 A4 A5 A6 A7 A8 GD
IR
B1 B2 B3 B4 B5 B6 B7 B8 VCC
GN
D
U18
74H
CT2
45
2 3 4 5 6 7 8 9 19 1
18 17 16 15 14 13 12 11 20 10
A1 A2 A3 A4 A5 A6 A7 A8 GD
IR
B1 B2 B3 B4 B5 B6 B7 B8 VCC
GN
D
R89 4.7K
PR7
10KX
4
18
27
36
45
U16
A
IRF7
303
8 71 2
D1
D1
S1 G1
U17
A
74H
CT2
44
2 4 6 8
18 16 14 12
1
A1 A2 A3 A4
Y1 Y2 Y3 Y4
GBC50
0.1u
F
PR5
47X4
18
27
36
45
PR6
47X4
18
27
36
45
R87
47
R88
47
U22
74H
CT2
57
24
3 57
6 119
10 1412
13 1 15
16 8
1A1Y
1B 2A2Y
2B 3A3Y
3B 4A4Y
4B A/B
G
VCC
GN
D
R10
010
K
R10
110
K
BC55
0.1u
F
BC53
0.1u
F
BC54
0.1u
F
BC57
0.1u
F
U24
74H
CT2
57
24
3 57
6 119
10 1412
13 1 15
16 8
1A1Y
1B 2A2Y
2B 3A3Y
3B 4A4Y
4B A/B
G
VCC
GN
DR
9510
K
BC52
0.1u
F
BC56
0.1u
F
R94
10K
R92
10K
U20
-1
P1S2
B138
2_14
00-1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68
GN
DD
3D
4D
5D
6D
7C
E1A1
0O
EA1
1A9 A8 A1
3A1
4W
EIR
EQVC
CVP
P1M
IVAL
MC
LKI
A12
A7 A6 A5 A4 A3 A2 A1 A0 D0
D1
D2
IOIS
16G
ND
GN
DC
D1
MD
03M
D04
MD
05M
D06
MD
07C
E2 VS1
IOR
DIO
WR
MIS
TRT
MD
I0M
DI1
MD
I2M
DI3
VCC
VPP2
MD
I4M
DI5
MD
I6M
DI7
MC
LKO
RES
ETW
AIT
INPA
CK
REG
MO
VAL
MO
STR
TM
DO
0M
DO
1M
DO
2C
D2
GN
D
R96
10K
R97
10K
R98
10K
R99
10K
R85
47
R84
150/
3216
C46
0.01
uF/X
7R
R83
10K
R10
210
K
CI1
MD
[0..7
]
MA[
1..2
0]
CAS
1STA
RT
CAS
1CD
CLK
CAS
1PW
REN
CI1
CD
[0..7
]
CAS
1BYP
ASS
CO
[0..7
]
nCI1
INS1
nCI1
INS2
nCAS
1CBE
NnC
I1W
AIT
CAS
1RES
ET
CD
STAR
T
CD
CLK
CD
EN
nCAS
1IO
RD
nCAS
1OE
nCAS
1WE
nCAS
1CS
nCAS
1IO
WR
CAS
1CD
EN
A A
B B
C C
D D
E E
44
33
22
11
CI2
1.4
TF50
00C
I
1017
, 1 3
1, 2
004
토요일
월
Title
Size
Doc
umen
t Num
ber
Rev
Dat
e:Sh
eet
of
CI2
MD
3C
I2M
D4
CI2
MD
7
CI2
MD
0C
I2M
D1
CI2
MD
2
CI2
MD
5C
I2M
D6
CI2
MA1
1
CI2
MA1
2C
I2M
A10
CI2
MA9
CI2
MA1
4C
I2M
A15
CI2
MA1
3C
I2M
A8C
I2M
A7C
I2M
A6C
I2M
A5C
I2M
A4C
I2M
A3C
I2M
A2C
I2M
A1
CI2
DO
5C
I2D
O6
CI2
DO
7
CAS
1STA
RT
CAS
1CD
ENC
AS1C
DC
LK
CAS
2CLK
IA
CAS
2STA
RTI
CI2
DO
0
CI2
DO
0
CI2
DO
7
CI2
DO
6
CI2
DO
5
nCI2
INS1
nCI2
INS2
CAS
2EN
I
CAS
2CLK
IA
CAS
2STA
RTI
CAS
2EN
I
CAS
2EN
O
CAS
2CLK
O
nCAS
2CBE
N
nCAS
2CBE
N
nCAS
2CBE
N
CAS
2CLK
OA
CAS
2EN
O
LCI2
IO16
nCAS
2OE
nCAS
2WE
nCAS
2IO
RD
nCAS
2IO
WR
CAS
2RES
ETnC
I2W
AIT
CI2
REG
LCI2
GAT
E
nCAS
2CS
MA4
MA3
MA2
MA7
MA1
MA6
MA5
MA1
6
MA1
3M
A15
MA9
MA8
MA1
1
MA1
4
MA1
2M
A10
CI2
MA1
CI2
MA2
CI2
MA3
CI2
MA4
CI2
MA5
CI2
MA6
CI2
MA7
CI2
MA8
CI2
MA9
CI2
MA1
0
CI2
MA1
1C
I2M
A12
CI2
MA1
3C
I2M
A15
CI2
MA1
4
CI2
REG
CAS
1CD
EN
CAS
1CD
CLK
CI1
CD
7
CI1
CD
4
CI1
CD
6
CI1
CD
5
CI1
CD
3
CI1
CD
0
CI2
DO
6C
I2D
O5
CI2
DO
4
CI2
DO
4
CI2
DO
4
CI2
DO
3
CI2
DO
3
CI2
DO
3
CI2
DO
0
CI2
DO
7C
AS2E
NO
CAS
2CLK
O
nCI2
INS1
nCI2
INS2
nCAS
2CBE
NnC
I2W
AIT
CI1
CD
3
CI1
CD
7
CI1
CD
1
CI1
CD
1
CI1
CD
2
CI1
CD
0
CI1
CD
4
CI1
CD
6C
I1C
D5
CI1
CD
2
CI2
DO
2
CI2
DO
2
CI2
DO
1
CI2
DO
2
CI2
DO
1
CI2
DO
1
CAS
2RES
ET
nCAS
2CBE
N
LCI2
D0
LCI2
D1
LCI2
D2
LCI2
D3
LCI2
D4
LCI2
D5
LCI2
D7
LCI2
D6
CI2
DI1
CI2
DI5
CI2
DI1
CI2
DI4
CI2
DI2
CI2
DI3
CI2
DI0
CI2
DI2
CI2
DI6
CI2
DI7
CI2
DI4
CI2
DI6
CI2
DI0
CI2
DI5
CI2
DI7
CI2
DI3
LCI2
CLK
LCI2
EN
LCI2
SRT
CAS
2CLK
OA
CAS
2CLK
O
LCI2
CE2
CI2
MD
[0..7
]
MA[
1..2
0]
CI2
CD
[0..7
]
CI1
CD
[0..7
]
nCAS
2CS
nCAS
2WE
nCAS
2CS
nCAS
2IO
WR
nCAS
2IO
RD
nCAS
2OE
CI2
CD
3
CI2
CD
5C
I2C
D6
CI2
CD
4
CI2
CD
7
CI2
CD
0
CI2
CD
1
CI2
CD
2
+5V
+5V
+5V
+5VC
I2+5
VCI2
+15V
S
+5V
+5VC
I2
+5V
+5V
+5V
+5V
+5VC
I2
+5VC
I2
+5VC
I2
+5VC
I2
+3.3
V
+3.3
V
+3.3
V
PR9
47X4
18
27
36
45
R10
747
R10
847
R12
510
K
R12
610
K
U20
-2
P1S2
B138
2_14
00-1
69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
GN
DD
3D
4D
5D
6D
7C
E1A1
0O
EA1
1A9 A8 A1
3A1
4W
EIR
EQVC
CVP
P1M
IVAL
MC
LKI
A12
A7 A6 A5 A4 A3 A2 A1 A0 D0
D1
D2
IOIS
16G
ND
GN
DC
D1
MD
03M
D04
MD
05M
D06
MD
07C
E2 VS1
IOR
DIO
WR
MIS
TRT
MD
I0M
DI1
MD
I2M
DI3
VCC
VPP2
MD
I4M
DI5
MD
I6M
DI7
MC
LKO
RES
ETW
AIT
INPA
CK
REG
MO
VAL
MO
STR
TM
DO
0M
DO
1M
DO
2C
D2
GN
D
R10
647
R12
047
C47
0.01
uF/X
7R
R10
415
0/32
16
R10
310
K
BC62
0.1u
F
R11
610
K
R11
347
R11
747
R11
947
R12
247
R11
447
R11
847
U27
74H
CT2
45
2 3 4 5 6 7 8 9 19 1
18 17 16 15 14 13 12 11 20 10
A1 A2 A3 A4 A5 A6 A7 A8 GD
IR
B1 B2 B3 B4 B5 B6 B7 B8 VCC
GN
D
U29
74H
CT2
45
2 3 4 5 6 7 8 9 19 1
18 17 16 15 14 13 12 11 20 10
A1 A2 A3 A4 A5 A6 A7 A8 GD
IR
B1 B2 B3 B4 B5 B6 B7 B8 VCC
GN
D
U26
74LV
C25
7
24
3 57
6 119
10 1412
13 1 15
16 8
1A1Y
1B 2A2Y
2B 3A3Y
3B 4A4Y
4B A/B
G
VCC
GN
D
U28
74LV
C25
7
24
3 57
6 119
10 1412
13 1 15
16 8
1A1Y
1B 2A2Y
2B 3A3Y
3B 4A4Y
4B A/B
G
VCC
GN
D
R12
410
K
R12
110
K
Q2
KST4
401
2
13
R11
247
R11
547
R11
04.
7K
BC58
0.1u
FR
105
4.7K
U25
74H
CT2
45
2 3 4 5 6 7 8 9 19 1
18 17 16 15 14 13 12 11 20 10
A1 A2 A3 A4 A5 A6 A7 A8 GD
IR
B1 B2 B3 B4 B5 B6 B7 B8 VCC
GN
D
PR10
10KX
4
18
27
36
45
PR11
10KX
4
18
27
36
45
R11
147
BC59
0.1u
F
BC60
0.1u
F
BC63
0.1u
F
BC61
0.1u
F
R12
347
BC64
0.1u
F
U16
B
IRF7
303
6 53 4
D1
D1
S1 G1
R10
94.
7K
U30
74LV
C25
7
24
3 57
6 119
10 1412
13 1 15
16 8
1A1Y
1B 2A2Y
2B 3A3Y
3B 4A4Y
4B A/B
G
VCC
GN
D
U17
B
74H
CT2
44
11 13 15 17
9 7 5 3
19
A1 A2 A3 A4
Y1 Y2 Y3 Y4
G
PR8
47X4
18
27
36
45
CI2
MD
[0..7
]
MA[
1..2
0]
CI1
CD
[0..7
]
CI2
CD
[0..7
]
CAS
2BYP
ASS
CAS
2CD
ENC
AS2C
DC
LK
CAS
1CD
ENC
AS1C
DC
LK
CAS
1STA
RT
CAS
2PW
REN
nCI2
INS1
nCI2
INS2
nCAS
2CBE
NnC
I2W
AIT
CAS
2RES
ET
nCAS
2WE
nCAS
2CS
nCAS
2OE
nCAS
2IO
RD
nCAS
2IO
WR
A A
B B
C C
D D
E E
44
33
22
11
AUD
IO D
AC1.
4
TF50
00C
I
1117
, 1 3
1, 2
004
토요일
월
Title
Size
Doc
umen
t Num
ber
Rev
Dat
e:Sh
eet
of
DAC
BCLK
DAC
WC
LKD
ACD
ATA
DAC
CLK
DAC
_VR
EF
DAC
_RIG
HT
DAC
_LEF
T
DAC
MU
TE
DAC
BCLK
DAC
DAT
AD
ACW
CLK
DAC
CLK
DAC
_VR
EFD
AC_R
IGH
TD
AC_L
EFT
DAC
MU
TE
+3.3
V
+3.3
V
+5V
U31
UD
A133
4TS
9101112131415161 2 3 4 5 6 7 8
L3M
OD
EL3
CLK
TEST
VREF
VDD
AVO
LVS
SAVO
RBC
KW
SD
ATAI
VDD
DVS
SDSY
SCLK
APPS
ELL3
DAT
A
BC65
0.1u
F
BC67
0.1u
F
U32
X(PC
M17
25U
/PC
M17
33U
)
8910111213141 2 3 4 5 6 7
VCC
VOL
NC
1N
C2
DM
FOR
MAT
SCKI
LRC
IND
INBC
KIN
NC
0C
APVO
RG
ND
R12
747
0
+C
4847
uF/1
6V
BC68
X(0.
1uF)
BC66
0.1u
F
L13
BEAD
-601
R12
847
0
L14
X
AUD
IOR
AUD
IOL
DAC
DAT
A
DAC
BCLK
DAC
WC
LK
DAC
CLK
DAC
MU
TE
A A
B B
C C
D D
E E
44
33
22
11
TV S
CART
*AUD
IO G
ND
*VID
EO O
UT G
ND*V
IDEO
IN
GND
*RED
(CHR
OMA)
*RED
GND
*GRE
EN
*GRE
EN G
ND
*BLU
E
*BLU
E RE
TURN
*FAS
T BL
ANKI
NG
*FAS
T BL
ANK
GND
*AUD
IO R
IGHT
OUT
*AUD
IO R
IGHT
IN
*AUD
IO L
EFT
IN
*AUD
IO L
EFT
OUT
*NC
*NC
*SHI
ELD
*VID
EO O
UT(Y
)*V
IDEO
IN
*FUN
CITO
N SW
VCR
SCAR
T
*AUD
IO G
ND
*VID
EO O
UT G
ND*V
IDEO
IN
GND
*RED
(CHR
OMA)
*RED
GND
*GRE
EN
*GRE
EN G
ND
*BLU
E
*BLU
E RE
TURN
*FAS
T BL
ANKI
NG
*FAS
T BL
ANK
GND
*AUD
IO R
IGHT
OUT
*AUD
IO R
IGHT
IN
*AUD
IO L
EFT
IN
*AUD
IO L
EFT
OUT
*NC
*NC
*SHI
ELD
*VID
EO O
UT(Y
)*V
IDEO
IN
*FUN
CITO
N SW
AV O
UTP
UT
1.4
TF50
00C
I
1217
, 1 3
1, 2
004
토요일
월
Title
Size
Doc
umen
t Num
ber
Rev
Dat
e:Sh
eet
of
TALO
UT
TAR
OU
T
TFSW
TCVB
SO
TRED
TBLA
NK
VAR
OU
TVA
RIN
VALO
UT
VALI
N
VFSW
VCVB
SOVC
VBSI
VBLA
NK
VRED
TGR
EEN
TBLU
E
VBLU
E
VGR
EEN
RFV
IDEO
CIN
CH
CVB
S
CIN
CH
CVB
S
CIN
CH
LC
INC
HR
RFV
IDEO
CIN
CH
R
CIN
CH
L
VAR
OU
T
VALO
UT
VFSW
TBLU
E
TAR
OU
T
TFSW
TGR
EEN
TRED
TBLA
NK
VRED
RED
BLU
E
VBLU
E
VGR
EEN
GR
EEN
TCVB
SO
CVB
S
VCVB
SO
CH
RO
MA
LUM
A
VALI
N
VAR
IN
VCVB
SI
VBLA
NK
LUM
A
CH
RO
MA
CVB
S
BLU
E
RED
GR
EEN
TALO
UT
VCR
CN
TLW
R
VCR
CN
TLR
D
+5V
+5VA
S
+5VA
S+1
2VAS
+5VA
S
+5VA
S
+5V
+12V
+12V
AS
+5V
+5VA
S
+3.3
V
+5V
BC73
0.1u
F
C91
270p
F
+
C65
10uF
/16V
R13
447
K
C87
22pF
R15
975
C62
100p
F
BC75
0.1u
F
C93
22pF
C88
22pF
R13
747
0
R13
875
C89
270p
F
+C
51
47uF
/16V
C96
270p
F
+
C66
10uF
/16V
C64
0.04
7uF
L18
1.8u
H
BC77
0.1u
F
L20
1.8u
H
R13
947
0
R13
047
K
C90
150p
F
C53
0.04
7uF
BC69
0.1u
F
C97
150p
F
R14
122
0
C83
270p
F
BC72
0.1u
F
R14
775
L16
1.8u
H
C70
100p
F
Q4
X(KS
R11
01)
2
13
+C
4910
0uF/
25V
R16
275
R14
875
C84
150p
F
R16
0X(
5.6K
)
R15
075
R14
975
R16
175
+
C75
10uF
/16V
BC70
0.1u
F
R16
775R
158
75
SCAR
T1-1
2203
-42S
TA
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 43
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 SGN
D
R15
147
0
SCAR
T1-2
2203
-42S
TA
22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 44
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 SGN
D
R16
668
R13
315
0
R15
72.
2K
+
C57
10uF
/16V
+
C76
10uF
/16V
D6
KDS2
26
23
1
+
C61
10uF
/16V
R15
247
0
C69
100p
F
R16
391
0
R13
147
0
BC74
0.1u
F
R15
5
560
C86
150p
F
R12
947
0
C73
0.04
7uF
+C
5022
0uF/
6.3V
R15
4
1K
L17
1.8u
H
U33
STV6
412
51 5014 6412 62108 602 4 18 216 13 22199 11 23207 55 56
49 38404236 34 4448 46 596128 27 30 2935 33 32415753631 5 1654 31517
24 25
26
31 3739434547 5258
FBIN
_EN
C
FBIN
_VC
R
BIN
_EN
C
BIN
_VC
R
GIN
_EN
C
GIN
_VC
R
RC
IN_E
NC
CIN
_EN
C
RC
IN_V
CR
CVB
SIN
_AU
X
YCVB
SIN
_EN
C
YCVB
SIN
_VC
R
CVB
SIN
_TV
YIN
_EN
C
LeftI
N_E
NC
LeftI
N_T
V
LeftI
N_V
CR
LeftI
N_A
UX
Rig
htIN
_EN
C
Rig
htIN
_TV
Rig
htIN
_VC
R
Rig
htIN
_AU
X
SCL
SDA
FBO
UT_
TV
BOU
T_TV
GO
UT_
TV
RC
OU
T_TV
VOU
T_R
F
FILT
ER
YCVB
SOU
T_TV
YCVB
SOU
T_VC
R
CO
UT_
VCR
SLB_
TV
SLB_
VCR
LOU
T_C
INC
H
RO
UT_
CIN
CH
LeftO
UT_
VCR
Rig
htO
UT_
VCR
AOU
T_R
F
LeftO
UT_
TV
Rig
htO
UT_
TV
GN
DB
GN
DVD
D
VCC
12VC
C
GN
D
VREF
ADD
DEC
NC
GN
DVC
CA
GN
DA
NC
VCC
AO
VCC
B5VC
CB4
VCC
B3VC
CB2
VCC
B1
C_G
ATE
IT_O
UT
C55
0.04
7uF
C52
0.04
7uF
C85
270p
F
C77
0.04
7uF
C56
0.04
7uF
C82
22pF
C74
0.04
7uF
R16
875
R16
956
0
C58
0.04
7uF
C99
150p
F
L15
BEAD
-601
R16
530
0
L21
1.8u
H
R14
315
0
BC71
0.1u
F
C98
270p
F
+
C60
4.7u
F/16
V
Q5
KST4
403
2
1 3
R14
047
0
C94
22pF
C71
470p
F
R16
430
0
C59
100p
F
+
C63
4.7u
F/16
V
+
C95
470u
F/6.
3V
R14
247
0
C81
22pF
Q3
X(KS
R11
01)
2
13
C67
470p
F
+
C68
4.7u
F/16
V
J1 RC
A3PI
N(J
W-1
606S
)
1 2 3 4 5
1 2 3 4 5
+C
8047
uF/1
6VR
156
X(1K
)
R15
375
R14
415
0
+
C72
4.7u
F/16
V
BC78
0.1u
F
C79
100p
F
R14
675
R14
568
R13
215
0
C92
150p
F
R13
522
0
C54
0.04
7uF
C78
100p
F
BC76
0.1u
F
L19
1.8u
H
R13
675
RFV
OU
T
ASC
LKAS
DA
AUD
IOR
AUD
IOL
RFA
OU
T
LUM
ANL
CH
RO
MAN
L
SLU
MA_
NB
SCH
RO
MA_
NB
CVB
SNL
BLU
ENL
GR
EEN
NL
RED
NL
RTS
0
DC
D0
A A
B B
C C
D D
E E
44
33
22
11
RF
MO
DU
LATO
R1.
4
TF50
00C
I
B
1317
, 1 3
1, 2
004
토요일
월
Title
Size
Doc
umen
t Num
ber
Rev
Dat
e:Sh
eet
of
SCL5
V
SCL5
V
+8VS
U35 RM
UP7
4055
AB
3 2 5
1
6
7 8 94 10
AUD
IO
VID
EO
SDA
MB+
SCL
GN
D0
GN
D1
GN
D2
BB+
GN
D3
U34
LM78
051
2
3IN
GNDOU
T
+
C10
010
0uF/
16V
R17
10
BC79
0.1u
FR17
2X
R17
039
K
RFA
OU
T
RFV
OU
T
SDA5
VSC
L5V
A A
B B
C C
D D
E E
44
33
22
11
EAST
PLUSE
WEST
POSI
TIO
NER
1.4
TF50
00C
I
B
1417
, 1 3
1, 2
004
토요일
월
Title
Size
Doc
umen
t Num
ber
Rev
Dat
e:Sh
eet
of
PULS
EIN
PULS
E
EAST
WES
T
+3.3
V
+5V
+5V
+3.3
V
+3.3
V
+3.3
V
R17
310
K
R17
82.
2K
R18
12.
2K
R17
7
X(1K
)
U36
DX(
74LV
C14
)
98
14 7
R18
0
X(1K
)
R17
6X(
2.2K
)
U36
EX(
74LV
C14
)
111014 7
U36
CX(
74LV
C14
)
56
14 7
Q8
X(KS
T440
1)2
13
JP8
X(52
67-5
A)
1 2 3 4 5
R18
2X(
10K)
U36
AX(
74LV
C14
)
12
14 7
R17
5
X(10
0K)
C10
1X(
0.02
2uF)
U36
BX(
74LV
C14
)
34
14 7
U36
FX(
74LV
C14
)
1312
14 7
Q6
X(KS
R11
01)
2
13
BC80
X(0.
1uF)
R17
4X(
10K)
C10
2X
Q7
X(KS
T440
1)2
13
R17
9X(
10K)
SKEW
IN
DTR
0
MO
DEM
_RS
T
PULS
E
A A
B B
C C
D D
E E
44
33
22
11
FRO
NT
1.4
TF50
00C
I
B
1517
, 1 3
1, 2
004
토요일
월
Title
Size
Doc
umen
t Num
ber
Rev
Dat
e:Sh
eet
of
FRXD
nPO
WER
ON
SKEW
IN
FREM
INKE
YSC
LK0
SCLK
1
SDAT
A
FREM
INR
EMIN
FPC
_CLK
0SC
LK0
FPC
_CLK
1SC
LK1
FPC
_DAT
ASD
ATA
KEYI
NKE
Y
REM
INKE
YIN
FPC
_CLK
0FP
C_C
LK1
FPC
_DAT
A
FTXD
FRXD
RXD
2
TXD
2FT
XD
FRO
NT_
PWR
nPO
WER
ON
FRO
NT_
PWR
SKEW
INR
XD2
TXD
2
+5V
+5VS
+5VS
+3.3
V
+3.3
V
+3.3
V
U38
C
X(74
LVC
14)
56
14 7
JP9
5267
-7A
1 2 3 4 5 6 7
L22
BEAD
-601
C10
4X(
22pF
)
U38
F
X(74
LVC
14)
1312
14 7
U37
A
74LV
C14
12
14 7
C10
322
0pF
U38
A
X(74
LVC
14)
12
14 7
BC82
X(0.
1uF)
C11
222
0pF
R18
3
2K
L23
X(BE
AD-6
01)
BC81
0.1u
F
C11
122
0pF
Q9
X(KS
T440
1)
2
13
U38
E
X(74
LVC
14)
1110
14 7
R18
6X(
10K)
U38
D
X(74
LVC
14)
98
14 7
R18
8
X(4.
7K)
U37
B
74LV
C14
34
14 7
U37
C
74LV
C14
56
14 7
C11
022
0pF
U37
E
74LV
C14
1110
14 7
U37
D
74LV
C14
98
14 7
R18
7X
JP10
X(52
67-6
A)
1 2 3 4 5 6
U37
F
74LV
C14
1312
14 7
R18
5
X(4.
7K)
U38
B
X(74
LVC
14)
34
14 7
R18
410
K
REM
INKE
YIN
FPC
_CLK
0FP
C_C
LK1
FPC
_DAT
A
MO
DEL
_ID
2
TXD
2R
XD2
SKEW
IN
A A
B B
C C
D D
E E
44
33
22
11
SVH
S1.
4
TF50
00C
I
B
1617
, 1 3
1, 2
004
토요일
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Title
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Doc
umen
t Num
ber
Rev
Dat
e:Sh
eet
of
SVH
SCH
RO
MA
SVH
SLU
MA
+5V
+5V
AS
+5V
AS
+5V
R19
256
0
R19
030
0
Q10
KST4
403
2
1 3
D7
KDS2
26
2
3
1
R19
568
+
C10
547
0uF/
6.3V
R19
656
0
R19
330
0
R19
168
R19
430
0
R18
930
0
+
C10
647
0uF/
6.3V
Q11
KST4
403
2
1 3
JP11
SVH
S C
ON
NEC
TOR
(MIN
I DIN
JAC
K)
4 3 1 2
5 6 7
Y C GN
DG
ND
SGN
DSG
ND
SGN
D
D8
KDS2
26
2
3
1
SLU
MA_
NB
SCH
RO
MA_
NB
A A
B B
C C
D D
E E
44
33
22
11
SMAR
T C
ARD
1.4
TF50
00C
I
B
1717
, 1 3
1, 2
004
토요일
월
Title
Size
Doc
umen
t Num
ber
Rev
Dat
e:Sh
eet
of
SC0_
DET
SC0_
RST
SC0_
RST
SC0_
VCC
SC0_
IOSC
0_VC
C
SC_C
LOC
KR
XD2
SC0_
CLK
RXD
2
TXD
2
SC0_
DET
TXD
2
SC0_
IO
SC_C
LOC
K
SC_C
LOC
K
SC0_
CLK
+3.3
V+5
V+3
.3V
+3.3
V
+3.3
V
+3.3
V
R19
81.
2K
U40
B
X(74
LVC
02A)
5 64
14 7
U40
D
X(74
LVC
02A)
11 1213
14 7
L25
X(BE
AD-6
01)
JP7
X(52
67-1
0A)
1 2 3 4 5 6 7 8 9 10
R74
2.2K
OSC
1X(
6MH
z)
2
4
13
GND
VCC
VIN
CLK
U40
A
X(74
LVC
02A)
231
147
L26
X(BE
AD-6
01)
BC84
X(0.
1uF)
R80
10K
R81
10K
R75
2.2K
R82
2.2K
U40
C
X(74
LVC
02A)
8 910
14 7
R19
72.
2K
L24
X(BE
AD-6
01)
BC85
X(0.
1uF)
SC0_
IO
TXD
2R
XD2
SC0_
VCC
SC0_
RES
ET
SC0_
CLK
SC0_
DET
ECT
MO
DEL
_ID
2
29
A. 4 Schematic Diagram Section < SMPS >
A
B
C
D
E
F
G
H
I
J
K
L
Wux
i Har
d E
lect
roni
cs C
o.,L
td
App
rove
dC
heck
D
raw
ing
Mod
el
HD
AD
30W
701
Uni
t m
m
Part
no
Sc
ale
Rev
. 01
1
2
3
4
5
6
7
8
9
Rev
. D
ate
Des
crip
tion
Che
ck
Page
1
OF
1
C3 C4
LF1A
LF1B
C1
D1-
D4
C5R2
C6 D5
U2
D6
R3
PC1
C22
L1
C8
C18
C25
A
B
A B
TR1
F1
R13
R16
ZD1
T1
U1
C23
R15
D14
D9
D13
R1
R17
R4
R14
L4
L5
L2
C13 C1
6
C11 C1
9C2
1
C7
D12
D8
D7
C10
C2
VR1
L3
C17
C12
C14
C9
R7
C20
C24
C15
U3
D10
D11
R11
R9R1
0
R8
R6
R5
12
CN1
1 2 3 4 5 6 7 8 9 10 11 12CN2
30V
22V
17V
GN
D8VG
ND
5VGN
D
GN
D15
VG
ND
3.3V
