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8-1R530/R730
- -
- This Document can not be used without Samsung's authorization -
8. Block Diagram and Schematic
Samsung
Confidential
AA
C
LAST EDIT
REV
C
4
DEV. STEP
3
4
2
3
1
CPU : HAN :
PROPRIETARY INFORMATION THAT IS
1.0
APPRO
VAL
APPROVAL
GCE :
NAN :
Signature :
B
Intel Cantiga &
ICH
9M
SAMSUNG ELECTRONICS COS PROPERTY.
ELECTRONICS
D
Design
CHECK
PAR
T NO.
Model Name : Bremen-L
PBA Name :
TITLE
PCB Code :
T.R. Date :
Revision :
Dev. Step : PV
2
Brem
en-L
MAIN
2009.10.27
Remarks : Intel Penryn
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
Montevina Platform
DR
AW
CHECK
Chip Set :
THIS DOCUMENT CONTAINS CONFIDENTIAL
DA
TE
Owner :
1
SAM
SUN
G PR
OPR
IET
AR
Y
SEC Mobile R &
D
EXCEPT AS AUTHORIZED BY SAMSUNG.
MO
DULE CODE
B
OF
PAGE
X
D
D:/users/m
obile24/mentor/Brem
en-L/PV/Bremen-L_M
AIN
COVER
MA
IN
Brem
en-L
591
BA
41-xxxxxA
October 27, 2009 14:27:43 PM
1.0
PV
10/10/2008
HJ.KIM
YM.A
HN
Jun PARKSAM
SUNG
www.bufanxiu.com
8-2 R530/R730
8. Block Diagram and Schematic
- -
- This Document can not be used without Samsung's authorization -
Samsung
ConfidentialSam
sung
ConfidentialSam
sung
Confidential
Page 8
Page 8
CRTP
age 37
Page 9~11R
TC
P 4, 6
P 5P 8(17")W
LAN
Page 43
Intel Pentium
ICH9-M
CLOC
K
CPUTherm
istor
FAN
FSB ~1067MH
z
2.5" HD
DP
age 44SATA0
SATA112.7m
m O
DD
Page 44
PCIe
EMC2112
DD
R II 800
BR
EM
EN
-L
Intel Core2Duo
Internal -C
antiga-GL40
External -
PEX4
SPI ROM
Page 35
16Mbit
CARDREADERA
LCO
R A
U6336
3-in-1P
age 42P 4
FFC
ME
C1308
USB 2.0
CK-505M
AN
T
Dual channel
Bluetooth
Channel B (Reverse)
Channel A (Reverse)
For 17"For 15"
0.3M
gDDR3P
age 25~28
nVidia
N11M
-GE
Cantiga-P
M45
LVDS(15" Single, 17" Dual)D
DR
2-SODIM
M x 2
17.3" HD
+ / 15.6"LED
LCD
Page 36
Page 12
Page 20~24
P 2P 9(15")
Single USB Port
Dual USB Port
/UL
PAGE
B
MO
DULE CODE
LAST EDIT
PAR
T NO.
( Half Type)
LR
Page 39~40
ALC
269
High Definition
SATA
REV
C
12
BA
PEX1
Transforme
r
RTL8040
10/100 LANControlle
rR
J45
Page 41
2
PROPRIETARY INFORMATION THAT IS
DA
TE
DC
TITLE
APPRO
VAL
THIS DOCUMENT CONTAINS CONFIDENTIAL
D
A
ELECTRONICS
KEYBO
ARD
Space bar
MICO
M
Page 45
Page 46
SE
NTE
LIC
TOUCHPAD
DEV. STEP
1
CHECK
OF
DR
AW
SAMSUNG ELECTRONICS COS PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
Cantiga-G
M45
TBD
BL
OC
K D
IAG
RA
M
BR
EM
EN
-UL
Page 13~17
Page 30~34
Page 18~19
D:/users/m
obile24/mentor/Brem
en-L/PV/Bremen-L_M
AIN
BLO
CK DIAGRAM
Brem
en-L
592
BA
41-xxxxxA
October 27, 2009 14:27:43 PM
1.0
PV
9/23/2008
undefined
HJ.KIM
YM.A
HN
Jun PARK
MA
IN
SAM
SUN
G PR
OPR
IET
AR
Y4
3
EXCEPT AS AUTHORIZED BY SAMSUNG.
43
SAMSUNG
www.bufanxiu.com
8-3R530/R730
8. Block Diagram and Schematic
- -
- This Document can not be used without Samsung's authorization -
Samsung
ConfidentialSam
sung
ConfidentialSam
sung
Confidentialsu
Bxe
Hss
erdd
As e
civ e
D
rets
aM
M 9H
CISM
BU
S Master
1010 000X
Master
MIC
OM
16hX1
1 0 1
000
YR
ETT
AB
123
6789
BO
AR
D IN
FOR
MA
TIO
N
SCHEMATIC ANNO
TATIONS AND BO
ARD INFORM
ATION
See rev notes for m
ore information.
32.768KH
zC
rystalIC
H9-M
10MH
z
CA
RD
RE
AD
ER
(AU
6336)45
UH
CI_2
BLU
ETO
OTH
(TBD
)1011
Crystal
MIC
OM
25MH
zC
rystalLA
N14.318M
Hz
Crystal
CLO
CK
-Generator
REVISIO
N HISTORY
I C / S
MB
Address
OD
D-
SA
TA2
SA
TA3
-
PC
I EX
PR
ES
S A
ssignationP
ort Num
ber
Clock, U
nused Clock O
utput Disable
D2h
CK
-505M (C
lock Generator)
1101 001X-
A0h
SO
DIM
M0
-P
CIe3
PC
Ie4-
Crystal / O
scillatorTY
PE
PR
EQ
UE
NC
Y
EM
C2102
7Ah
0111 101X
A4h
X 100
010
11
MMI
DO
S
US
B P
OR
T Assignation
Port N
umber
AS
SIG
NE
D TO
US
B P
OR
T (RIG
HT, S
UB
)0
5.0V supply for A
udioAUD_P5V
PRTC_BAT
3.3V supply for the R
TC w
ell.C
harger Reference V
oltage Source
VDC_CHG
LCD_VD
D3V
UH
CI_0
UH
CI_1
UH
CI_3
UH
CI_4
Port N
umber
AS
SIG
NE
D TO
CA
ME
RA
(17")
P3.3V_MCD
3.3V (3-in-1 S
ocket)
P12.0V_ALW
12.0V alw
ays power w
ell
Pow
er Rail
Descriptions
P5.0V
UH
CI_5
US
B P
OR
T (LEFT)
US
B P
OR
T (RIG
HT, S
UB
)
SA
TA A
ssignationP
ort Num
berA
SS
IGN
ED
TO
HD
DS
ATA
0S
ATA
1
Port N
umber
AS
SIG
NE
D TO
1.5V P
ower R
ail (off in S3-S
5)
1.05V P
ower R
ail (off in S3-S
5)
5.0V P
ower R
ail (off in S4-S
5)3.3V
Pow
er Rail (off in S
4-S5)
1.5V P
ower R
ail (off in S4-S
5)
Core V
oltage for CP
U
KBC3_C
HG4.2V
AS
SIG
NE
D TO
WLA
NP
CIe1
PC
Ie2
Port N
umber
AS
SIG
NE
D TO
Wired LA
N
P1.8_AUX
1.8V P
ower R
ail (off in S4-S
5)P2.0V_VR
EFP
ower C
hip Reference
Auido A
nalog Voltage
P4.75V_AUD
To charge US
B device at sleep status
EG
AS
UE
CIV
ED
Voltage R
ails
Prim
ary DC
system pow
er supply (9 to 19V)
VDC
VDC_ADPT
P3.3V_MICOM
Pow
er Rail
Descriptions
Output voltage of R
T8205AG
QW
(if VD
C is rem
oved, it will be off)
PROPRIETARY INFORMATION THAT IS
A
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
B
2
C
1
3.3V (LE
D LC
D)
P1.05V_PEGP
1.05V (D
irect Media Interface C
ompensation)
P1.2V_LAN
Internal Regulators P
ower of LA
N C
ontroller
P5.0V_ALW
5.0V alw
ays power w
ell
3
B
REV
1
TITLE
C
P3.3V
P1.8V
P1.5V
P1.05
P5.0V_AUX
P3.3V_AUX
P1.5_AUX
CPU
_CORE
5.0V P
ower R
ail (off in S3-S
5)3.3V
Pow
er Rail (off in S
3-S5)
1.8V P
ower R
ail (off in S3-S
5)
PAGE
2
SAMSUNG
D
4
THIS DOCUMENT CONTAINS CONFIDENTIAL
DR
AW
To charge battery
P0.9VD
DR
2 Termination
P1.7V_VREF
Pow
er Chip R
eference
P5.0V_VREF_FILT
Pow
er Chip R
eference
DEV. STEP
PAR
T NO.
ELECTRONICS
OF
CHECK
LAST EDIT
DA
TE
P5.0V_STB5.0V
supply at SU
B_O
DD
Board
P5.0V_ODD
EGFX_C
ORE
nVidia G
raphic Chip pow
er
2
Pow
er source of External
CA
ME
RA
(15")P2.5V_LA
N
EXCEPT AS AUTHORIZED BY SAMSUNG.
APPRO
VAL
Jun PARK
YM.A
HN
HJ.KIM
undefined
9/23/2008
PV
1.0
October 27, 2009 14:27:43 PM
BA
41-xxxxxA
359
Brem
en-LM
AIN
BOARD INFO
D:/users/m
obile24/mentor/Brem
en-L/PV/Bremen-L_M
AIN D
SAMSUNG ELECTRONICS COS PROPERTY.
4
SAM
SUN
G PR
OPR
IET
AR
Y
3
A
MO
DULE CODE
www.bufanxiu.com
8-4 R530/R730
8. Block Diagram and Schematic
- -
- This Document can not be used without Samsung's authorization -
Samsung
ConfidentialSam
sung
ConfidentialSam
sung
Confidential 3-in-1 SocketW
LAN
HD
DM
ICOM
LID SW
LEDs
P1.5VPEN
TIUM CPU
CK505MG
L40A
LC269Q
DD
R II Term
ination
P1.05VPEN
TIUM CPU
TPS51620CPU_CO
RE
ICH9M,LED
,Wire LAN,LED
LCD
P5.0V_AUX
P5.0V_STB
SPI ROM
,
P12.0V_ALW
ELECTRONICS
3
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAM
SUN
G PR
OPR
IET
AR
Y
DR
AW
C
2
DEV. STEP
1
3
APPRO
VAL
D
MICO
M,LED
s
EMC2112
GL40
GL40
CRT
HD
D
OD
DTO
UTCHPAD
POW
ER
DIA
GR
AM
KBC3_VRO
N
VDC
KBC3_SUSPW
RK
BC3_PWRO
N
P5.0V
OF
EXCEPT AS AUTHORIZED BY SAMSUNG.
LAST EDIT
TITLE
PAR
T NO.
A
B
D
PAGE
A
4
SAMSUNG
1
CHECK
B
MO
DULE CODE
AC ADAPTER
P3.3V_MICO
MDC BATTERY
S5-S4S0
(CHP3_SLPS3*)(CHP3_S4_STATE*)
P0.9V
P5.0V_ALW
P3.3V_AUX
RT8205
APW
7141P1.8V_AU
XD
DR
II
USB,Swithched Pow
er
P1.8VN
11M-G
E
SC471EG
FX_CORE
N11M
-GE
gDDR3
APW
7141ICH9M
P1.2V_LAN
2
REV
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
4
C
DA
TE
SAMSUNG ELECTRONICS COS PROPERTY.
CAMERA
P5.0V_AUDA
LC269Q
P3.3VEM
C2112
FAN
CK505MG
L40D
DR
2ICH9M
80 PORT
LED LCD
ALC269Q
AU6336
RTL8103EL,
P3.3V_MCD
D:/users/m
obile24/mentor/Brem
en-L/PV/Bremen-L_M
AIN
POW
ER DIAGRAM
MA
IN
Brem
en-L
594
BA
41-xxxxxA
October 27, 2009 14:27:43 PM
1.0
PV
9/23/2008
undefined
HJ.KIM
YM.A
HN
Jun PARK
PENTIUM
CPU
GL40
ICH9M
P2.5V_LAN
88E8040
S3
GL40,
www.bufanxiu.com
8-5R530/R730
8. Block Diagram and Schematic
- -
- This Document can not be used without Samsung's authorization -
Samsung
ConfidentialSam
sung
ConfidentialSam
sung
Confidential
CHP3_RTCRST#
6) KBC3_PWRSW#
9
12) KBC3_RSMRST#
12
14
4) P3.3V_MICOM
14-1) KBC3_PWRON_INV#
4
8) P5.0V_AUX
14) KBC3_PWRBTN#
13
15) P5.0VA
P4435GM
Sheet 56
9) P3.3V_AUX
8) P5.0V_AUX
VR
MP
WR
GD
PW
RO
K
Sheet 56
Sheet 30~34
Sheet 9~11
1
2
RT8205
AO6409L
5
10) P1.8V_AUX
APW
7141S
heet 52 P1.8V
_AU
X
10
17) P1.5V17
2) VDC
18) P1.05V18
14) KBC3_PWRON
MEM
1_VREF
7) KBC3_SUSPWR
2) VDC
7
Sheet 13~17
Sheet 18~19
6
VD
C_A
DP
T /
BQ24751
ADAPTERBATTERY
2) VDC
23) KBC3_PWRGD
ICH9-M
KBC
RTC
Battery
PM45
2-1) P12.0V_ALW
3
Sheet 8
15) P5.0V9) P3.3V_AUX
18) P1.05V
17) P1.5V
19) CPU_CORE
CPU
18) P1.05V10) P1.8V_AU
X
17) P1.5V16) P3.3V
23) KBC3_PWRGD
10) P1.8V_AUX
MEM
1_VREF
16) P3.3V
14) KBC3_PWRON
24
7) KBC3_SUSPWR
14) KBC3_PWRON
16) P3.3V
27) CPU1_CPURST#
24) CPU1_PWRGDCPU
POW
ERS/W
DD
R2
CK-505M
PRTC_BAT
P3.3V
_AU
X &
P5V
_ALW
26) PLT3_RST#
Sheet 12
** KBC3_USBCHG **
5) P5.0V_STB
15) P5.0V
ALC 269
Sheet 39
16) P3.3V
P5.0V_AUD
17) P1.5V
0 OHM
P4.75V_AUDP5.0V_AUD15) P5.0V
88E8040S
heet 41
9) P3.3V_AUX
AU6336S
heet 42
19) CPU_CORE
TPS51620
7) KBC3_SUSPWR14) KBC3_PW
RON
21) CLK3_PWRGD
PW
RO
K
CL_P
WR
OK
4) P3.3V_MICOM
9) P3.3V_AUX
11) CHP3_SLPS5#/4#/3#1615
8
14-1
11
17) P3.3VEM
C21112
Sheet 45
LEDS
heet 47
16) P3.3V9) P3.3V_AUX
4) P3.3V_MICOM
P1.8VAO
6409L10) P1.8V_AU
XEG
FX_CORE
SC471E
GFX
_CO
RE
2) VDC
GCO
RE3_PWRG
D
APW
7141
PRTC_BAT
9) P3.3V_AUX
20) VRM3_CPU_PWRGD 23
25) CHP3_SUSSTAT#
25
20) VRM3_CPU_PWRGD
(KBC3_VRON)
22) KBC3_CPURST#22
26
27
POW
ER
SEQ
UE
NC
E
VD
C_C
HG
3) P5.0V_ALW
CRTS
heet 37
14) KBC3_PWRON
10) P1.8V_AUX
10 KOHM
10 KOHM
DA
TE
1
21
C
DEV. STEP
REV
LAST EDIT
SAMSUNG
D
C
16) P3.3VP3.3V_M
CD
Sheet 43
CP
U_C
OR
E
1919) VCCP3_PW
RGD
2) VDC
20) VRM3_CPU_PWRGD
CPU1_DPRSTP#CHP3_DPRSLPVR
20
21
26) PLT3_RST#
25) PLT3_RST#16) P1.5V
Sheet 46
15) P5.0V
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS COS PROPERTY.
PAR
T NO.
TITLE
MO
DULE CODE
APPRO
VAL
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
DR
AW
CHECK
334 4
Sheet 53
P1.5V
16) P3.3V17) P1.5V18) P1.05V
MX25L
Sheet 35
4) P3.3V_MICOM
LED LCD
Sheet 36
9) P3.3V_AUXLCD_VDD3V
16) P3.3VVD
D_LED
2) VDC
(Between P3.3V & P1.5V)(After P1.05V)
14) KBC3_PWRON
Sheet 56
P0.9V
14) KBC3_PWRON
APL5336
Sheet 52
P0.9V
8) P5.0V_AUX
ELECTRONICS
AA
OF
PAGE
SAM
SUN
G PR
OPR
IET
AR
Y2
D
WLA
NS
heet 43
16) P3.3V
ODD
Sheet 44
15) P5.0V
2.5" HD
DS
heet 44
15) P5.0V16) P3.3V
16) P3.3V4) P3.3V_MICOM
TOUCHPA
D
D:/users/m
obile24/mentor/Brem
en-L/PV/Bremen-L_M
AIN
POW
ER SEQUENCE
MA
IN
Brem
en-L
595
BA
41-xxxxxA
October 27, 2009 14:27:43 PM
1.0
PV
9/23/2008
undefined
HJ.KIM
YM.A
HN
Jun PARK
BB
2) VDC
14) KBC3_PWRON
APW
7141S
heet 53
P1.5V
www.bufanxiu.com
8-6 R530/R730
8. Block Diagram and Schematic
- -
- This Document can not be used without Samsung's authorization -
Samsung
ConfidentialSam
sung
ConfidentialSam
sung
Confidential CLK1_MCLK4/4# CLK1_MCLK0/0#CLK1_MCLK1/1#S
OD
IMM
#0
SO
DIM
M #1
333/400 MH
z
266 MH
zC
LK0_H
CLK
/CLK
#
266 MH
z
10 MH
z
Page 8
MC
H3_C
LKR
EQ
#
CLK
1_DR
EFS
SC
LK/D
RE
FSS
CLK
#
100 MH
z (SR
C 6)
1
SP
IK
BC
3_SP
I_CLK
17.86 MH
z
HP
LL
xSLG8SP513r05)
100 MH
z
CLK
1_DR
EFC
LK/D
RE
FCLK
#96 M
Hz
CLK
1_PC
IEIC
H/P
CIE
ICH
#100 M
Hz (S
RC
3)
CLK
1_PC
IELO
M/P
CIE
LOM
#100 M
Hz (S
RC
9)
32.768 KH
z
PC
I Express G
fx100 M
Hz (S
RC
0)
OS
CH
D A
udio
WIR
ED
LAN
LOM
3_CLK
RE
Q*#
CLK
3_US
B48
48 MH
z
CLK
1_SA
TA/S
ATA
#100 M
Hz (S
RC
2)
CL
OC
K D
ISTR
IBU
TIO
N
667/800 MH
z
CLK
1_MC
LK3/3#
CLK
3_PC
LKIC
H33 M
Hz
33 MH
zC
LK3_P
CLK
MIC
OM
BS
EL
14 MH
zO
SC
Main P
LLS
SC
48MH
z PLL
CLK
0_HC
LK1/H
CLK
1#
CLK
1_DR
EFS
SC
CLK
/DR
EFS
SC
CLK
# #LL
PG 3
HC
M /LL
PG3
HC
M _1
KLC
)4C
RS(
zH
M 0 0
1
AU
D3_B
CLK
CP
U
MC
H
KB
C
14.318 MH
z
CK-505M (w/ CLKREQ* & SSDC)
FS(2:0)
CP
U_S
TP*
ITP_E
N
SS
(96/100) SE
L
PC
I_STP
*
P3.3V
CLK
3_PW
RG
D*
100 MH
z (SR
C 6,9)
WLA
NC
LK1_M
INIP
CIE
/MIN
IPC
IE#
RTC
Clock
25 MH
z
333/400 MH
z
AA
SAMSUNG
2
OF
3
B
C
2
PC
IE P
LL
DP
LLA
MP
LL
DP
LLB
ICH
9-MU
SB
PLL
SA
TAP
LL
32.768 KH
z
PC
IEP
LL
Cantiga
3
PAR
T NO.
PAGE
DA
TE
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
CHECK
B
LAST EDIT
REV
14.318 MH
z
CH
P3_S
ATA
CLK
RE
Q#
Jun PARK
4
THIS DOCUMENT CONTAINS CONFIDENTIAL
1
DDC
4
ELECTRONICS
1
PLL3
SS
C33 MH
zB
uffer
MUXMUX MUX
FSB
PEG
DM
I
DEV. STEP
SAMSUNG ELECTRONICS COS PROPERTY.
TITLE
MO
DULE CODE
EXCEPT AS AUTHORIZED BY SAMSUNG.
APPRO
VAL
SAM
SUN
G PR
OPR
IET
AR
YPROPRIETARY INFORMATION THAT IS
DR
AW
MIN
3_CLK
RE
Q*#
333/400 MH
z
333/400 MH
z
D:/users/m
obile24/mentor/Brem
en-L/PV/Bremen-L_M
AIN
CLOCK DIAG
RAM
MA
IN
Brem
en-L
596
BA
41-xxxxxA
October 27, 2009 14:27:43 PM
1.0
PV
9/23/2008
undefined
HJ.KIM
YM.A
HN
www.bufanxiu.com
8-7R530/R730
8. Block Diagram and Schematic
- -
- This Document can not be used without Samsung's authorization -
Samsung
ConfidentialSam
sung
ConfidentialSam
sung
Confidential
DESIG
N
EXCEPT AS AUTHORIZED BY SAMSUNG.
3
B
Opposite side of G
PU
.
DA
TE
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
1
TRIP
_SE
T 1500 : 95 degree
2
EX
T.DIO
DE
2 MO
DE
HIG
H Z
Opposite side of C
PU
.
ELECTRONICS
0
HIG
H Z
4
To support heatsink
Check if P
U is doubled to M
icom S
ide.
Line Width = 20 m
il
CHECK
APPRO
VAL
C
A
0101 111xb
A
AM
D C
PU
/DIO
DE
MO
DE
4
PROPRIETARY INFORMATION THAT IS
For Intel 45nm(From
penryn)
B
1
THE
RM
AL S
EN
SO
R &
FAN
CO
NTR
OL
0101 110xb
SAMSUNG ELECTRONICS COS PROPERTY.
MO
DULE CODE
0111 101xb (7A)
SM
BU
S A
ddress 7Ah
THER
MA
L SENSOR EM
C2112
D:/users/m
obile24/mentor/Brem
en-L/PV/Bremen-L_M
AIN
Jun PARK
YM.A
HN
HJ.KIM
9/23/2008
PV
1.0
AD
DR
ES
SS
_SE
L MO
DE
SH
DN
_SE
L MO
DE
LAST EDIT
10mil w
idth and 10mil spacing.
0
SAMSUNG
To remove glitch w
hen system is booted up.
1
2
1
D
TITLE
3
D
OF
SAM
SUN
G PR
OPR
IET
AR
Y
C
PAR
T NO.
THIS DOCUMENT CONTAINS CONFIDENTIAL
INTE
L TR M
OD
E
PAGE
DEV. STEP
REV
BA
61-01090A
M505
October 27, 2009 14:27:43 PM
BA
41-xxxxxA
759
Brem
en-LTH
ERM
AL SENSO
R
BA61-01090A
M503
LENGTH
HEAD
DIA
LENGTH
HEAD
DIA
31-C3,44-C
3
1% R56749.9
7-C3 P3.3V
P3.3V
_AUX
1% R5641.5K
10000nF-X5R
C62
6.3V
1000nF-X5R
C1048
P3.3V
_AUX
19-D1,44-B
3
6.3V
nostuff
10KR548 1%1%R549 10K
nostuff
R566
7-B2
nostuff
7-B2
0
P3.3V
_AUX
P5.0V
19-D1,44-B
3
C559
100nF10V
10000nF-X5R
C562
6.3V10V100nFC564
4MNT1
56MNT2
P3.3V
HDR-4P
-1R-SMD
J23711-000456
123
M504
BA61-01090A
DIA
HEAD
LENGTH
Q12
13 2
7-C3
50V
C566
MMBT3904
R568
1% 10K
2.2nF
SYS_S
HDN#
20TA
CH
THERMAL_P
AD
21
7TR
IP_S
ET
1VDD_3V
16VDD_5V
_119
VDD_5V
_2
DN3_D
P2
5 3DP1
DP3_D
N2
417
FAN_1
18FA
N_2
GND
13
9RESET#
6SHDN_S
EL
15SMCLK
SMDATA
148
U503
EMC2112-B
P-TR1209-001887
ADDR_S
EL
10
12ALE
RT#
CLK
11 2DN1
LENGTH
HEAD
DIA
BA61-01090A
M502
44-D1
R579
0 0R578
nostuff
2.2nF
19-D2
19-D2
nostuff
MMBT3904
132
nostuff
C615
50V
50V
nostuff
Q506
9-C4
C565
2.2nF
9-C4
1%
nostuff
1%R558 10K1%
10KR550
THM3_TH
ERMDP_M
N
THM3_S
TP#
10KR43
THM3_V
DD_5V
_MN
THM3_V
DD_3V
_MN
FAN3_FD
BACK#
KBC3_TH
ERM_S
MDATA
KBC3_TH
ERM_S
MCLK
CPU2_TH
ERMDA
CPU2_TH
ERMDC
THM3_A
LERT#
FAN5_V
DD
FAN3_FD
BACK#
FAN5_V
DD
THM3_TR
IP_S
ET_M
NTH
M3_S
HDN_S
EL_M
N
THM3_TH
ERMDN_M
N
GFX
3_THERMDP
GFX
3_THERMDN
www.bufanxiu.com
8-8 R530/R730
8. Block Diagram and Schematic
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- This Document can not be used without Samsung's authorization -
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ConfidentialSam
sung
ConfidentialSam
sung
Confidential1 / 4
ADDR GROUP
ICH
0ADDR GROUP
1
CONTROL
2 / 4
DATA GRP 0
DATA GRP 2
DATA GRP 1
DATA GRP 3
C
CP
U S
ocket : 3704-001153
DA
TE
APPRO
VAL
THIS DOCUMENT CONTAINS CONFIDENTIAL
A
SAMSUNG ELECTRONICS COS PROPERTY.
REV
2
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
OF
DEV. STEP
B
CHECK
SAMSUNGELECTRO
NICS
TITLE
B
A
D
433
MO
DULE CODE
PROPRIETARY INFORMATION THAT IS
1
Jun PARK
YM.A
HN
HJ.KIM
undefined
9/23/2008
PV
1.0
October 27, 2009 14:27:43 PM
BA
41-xxxxxA
859
Brem
en-LCPU
PENR
YN (1/3)
D:/users/m
obile24/mentor/Brem
en-L/PV/Bremen-L_M
AIN
LAST EDIT
1
SAM
SUN
G PR
OPR
IET
AR
Y
PAR
T NO.
DR
AW
C
4
EXCEPT AS AUTHORIZED BY SAMSUNG.
CP
U bracket
D
PAGE
2
1718
12-B1
12-B1
12-B1
12-B1
3536
12-B1
12-C1
323334
DS
TBP
3#A
F24
616263
DIN
V0#
H25
DIN
V1#
N24
DIN
V2#
U22
DIN
V3#
AC
20
DS
TBN
0#J26
DS
TBN
1#L26
DS
TBN
2#Y
26
DS
TBN
3#A
E25
DSTB
P0#
H26
DSTB
P1#
M26
DSTB
P2#
AA26
AC25
D58#
AE21
D59#
AD21
D6#
E25
D60#
AC22
D61#
AD23
D62#
AF22
D63#
AC23
D7#
E23
D8#
K24
D9#
G24
D48#
AE24
D49#
AD24
D5#
G25
D50#
AA21
D51#
AB22
D52#
AB21
D53#
AC26
D54#
AD20
D55#
AE22
D56#
AF23
D57#
D38#
U25
D39#
U23
D4#
F23
D40#
Y25
D41#
W22
D42#
Y23
D43#
W24
D44#
W25
D45#
AA23
D46#
AA24
D47#
AB25
R24
D29#
L25
D3#
G22
D30#
T25D31#
N25
D32#
Y22
D33#
AB24
D34#
V24
D35#
V26
D36#
V23
D37#
T22
D19#
R23
D2#
E26
D20#
L23D21#
M24
D22#
L22D23#
M23
D24#
P25
D25#
P23
D26#
P22
D27#
T24D28#
D0#
E22
D1#
F24
D10#
J24
D11#
J23D12#
H22
D13#
F26D14#
K22
D15#
H23
D16#
N22
D17#
K25
D18#
P26
A3
STP
CLK
#D5
TRDY#
G2
0143854500|bga_479p_sock
CPU1-2
PENRYN
LOCK#
H4
K3
REQ0#
H2
REQ1#
K2
REQ2#
J3REQ3#
L1REQ4#
RESET#
C1
RS0#
F3RS1#
F4RS2#
G3
SMI#
DEFE
R#
H5
DRDY#
F21
FERR#
A5
HIT#
G6
HITM
#E4
IERR#
D20
IGNNE#
C4
INIT#
B3
LINT0
C6
LINT1
B4
A6#
K5
A7#
M3
A8#
N2
A9#
J1
ADS#
H1
ADSTB
0#M1
ADSTB
1#V1
BNR#
E2
BPRI#
G5
BR0#
F1
DBSY#
E1
W5
A29#
Y4
A3#
J4
A30#
U2
A31#
V4
A32#
W3
A33#
AA4
A34#
AB2
A35#
AA3
A4#
L5A5#
L4
A19#
R3
A20#
W6
A20M
#A6
A21#
U4
A22#
Y5
A23#
U1
A24#
R4
A25#
T5A26#
T3A27#
W2
A28#
CPU1-1
PENRYN
A10#
N3
A11#
P5
A12#
P2
A13#
L2A14#
P4
A15#
P1
A16#
R1
A17#
Y2
A18#
U5
3435
0143854500|bga_479p_sock
12-C1
3233
121314
12-B4
910112122 7817181920
12-C1
16 34
12-A1
12-A1
31 0
12-B1
12-A1
3 2 1
478
4
12-B1
3
12-D4
2728
12-D4
454647
R57156
12-B112-B1
P1.05V
15
12-D4
12-D4
12-B1
41424344 383940
28 25 23
37
12
27
53542426
58 57 4950
1MNT1
MNT2
23MNT3
MNT4
4
10
5960
M501
BA75-01937A
SUPLE
CODE
6
5556
9
29-B1
5
29-C1
29-C1
29-B1
52
0
29-B1
29-C1
29-C1
31
12-D1
51
12-B1
48
112930
12-B1
12-B1
2122 12
12-B1
1920
29-C1
12-C1
12-C1
12-B1
12-B1
12-B1
12-B1
562930 242526
12-C1
12-C1
23
1516
12-D1
12-B1
CPU1_A
DS#
CPU1_IE
RR#_M
N
CPU1_C
PURST#
CPU1_IN
TR
1314
CPU1_D
#(63:48)
CPU1_D
#(47:32)
CPU1_D
BI0#
CPU1_A
DSTB
0#
CPU1_A
DSTB
1#
CPU1_D
#(31:16)
CPU1_D
#(15:0)
CPU1_R
EQ#(4:0)
CPU1_A
#(16:3)
CPU1_D
STB
N2#
CPU1_D
STB
N3#
CPU1_D
STB
P2#
CPU1_D
STB
P3#
CPU1_D
STB
P1#
CPU1_D
STB
N1#
CPU1_D
STB
P0#
CPU1_D
BI1#
CPU1_D
STB
N0#
CPU1_A
#(35:17)CPU1_D
BI2#
CPU1_D
BI3#
CPU1_IN
IT#
CPU1_N
MI
CPU1_LO
CK#
CPU1_R
S0#
CPU1_R
S1#
CPU1_R
S2#
CPU1_S
MI#
CPU1_S
TPCLK
#
CPU1_TR
DY#
CPU1_A
20M#
CPU1_B
NR#
CPU1_B
PRI#
CPU1_B
REQ#
CPU1_D
BSY#
CPU1_D
EFE
R#
CPU1_D
RDY#
CPU1_FE
RR#
CPU1_H
IT#CPU1_H
ITM#
CPU1_IG
NNE#
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8. Block Diagram and Schematic
- -
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3 / 4
RSVD
THERMAL H CLK
XDP/ITP SIGNALS
0
0
1
1
0
0
00.7125 V
1
1
0
1
01
APPRO
VAL
0
0
1
1
0
0
1
1
REV
0
near the CP
U
1
0
Active
1
A
2
SAMSUNG ELECTRONICS COS PROPERTY.
0
0
1.4625 V
1
1
0
0
0
0
0
CP
U S
ocket : 3704-001153
0.9125 V
1
0
BS
EL0, B
SE
L2B
SE
L0, BS
EL1, B
SE
L2
1
1
FRQ
0
0
1.2250 V
0.0000 V
1
1
200M
1
0
0
0.5500 V
0
0
0
1
MO
DULE CODE
2
1
BSE
L
1
1.3125 V
01
1
0Minim
ize coupling of any switching signals to this net.
1
1
0
0
1
0
1
1
11
1
0
0
0
0
0
0
1
1
0
0
0
1
1.3000 V
0.3500 V
0
0
0
0
1
10
1
1
1
1
1
0
*"1111111" : 0V pow
er good asserted.
1
1
1
1
10
0
0
1
1.1750 V
0
0
0
1
0
1
1
0.0000 V
0
1
0
0
0
1.1375 V
0
0
*Yonah P
rocessor (2.33 GH
z / 800 MH
z : TBD
)
0
0
0
FSB
Route the V
CC
/VS
Ssense as a Zo=55ohm
traces with equal length.
0
1
1
0
0
0
FSA
0
1
1
0
0.3750 V
Pull-dow
n
1
DA
TE
0
0
0
DEV. STEP
1
0
0.6000 V
0.0625 V
1
11
0
1
00
0
1
OF
1
0
0
166M
0
1
0
1
1
0
1
1
0
1
1
0
0
0
11.0625 V
0
1
0.3375 V
0.1500 V
0
0
0.8125 V
1
FSC
1.5000 V
1
0
1
1
0
0
0.4875 V
1
1
1
0.5375 V
0
0.2375 V
1
1
0
1.4875 V
0
1
0
0
0
0
0
1
0
1
0.7250 V
0
SI team
request
0.2250 V
1
1
1
0
266M
0.0375 V
1
0
10.1625 V
11
0
1
0
0.0875 V
1
0
1
01
0
0
1
0
0
0
1
1
11
1
0
0
Observe 3:1 spacing b/w
VC
C/V
SS
sense lines and 25mil aw
ay
1
FSB
800 MH
z
1
1
0
DP
RS
LPV
R
0
0
1
1
1
0
1.2625 V
1.3625 V
0.3125 V
0
0
0
0
0.4750 V
1
0
0
DP
RS
TP*
1 00
1
0
1
1 1
1
1
10
0.5000 V
0
0
0
1
1 01
0
01
1
1
0.4625 V
1
SAMSUNG
0
0
0
1
0
3
0
-> delete and change layout (EC
AE
)
0
0
11
11
1
1
1
1
1
10
1
1
0
TITLE
1
1 0
1
1
1
0
1
1
0
1
0
1
1
0
(preferred 50mil) from
any other signal. And G
ND
via 100mil aw
ay
0.2625 V
11
0
1
0
1
1
0
1
0
1
0
PS
I2*
1
0
1
1
0 1
1.1125 V
1
0
1
1
1
1
1
0
1
0
0
10
0.6375 V
0.2875 V
0
1
0.5250 V
1
1
0
0
14
01
1
0
0
1
0
IMV
P-6
0
0
0.3000 V
1
0.7875 V
1
1
0
1
FSB
1067 MH
z
1
0
0
1
1
0.8500 V
0
01.1875 V
1
1
0.6875 V
0 or 1
0
1
1.4750 V110
1.4000 V
0.0500 V
10
0.5875 V
1
1
0
1
0.0750 V
0
0
0.5125 V
0
0
1
0
1
1
00
Dual M
ode Region
1
1
1
0
0
0.4000 V1
10
0.5750 V
1
1
0
0
1
0
0.4375 V0
1
0
1
10
DR
AW
0
0
1
1
1.0375 V
1
0
0
1
00
0
0
1
1
1 1
1
1
0
0.3625 V
1
1
1
11.4500 V
1
0
0
1
0
1
0
10
1
1
0
0
1
0
1
C
01
0
1
of the first GTLR
EF0 pin w
ith Zo=55ohm trace.
1
0
0
EXCEPT AS AUTHORIZED BY SAMSUNG.
V 05
23.0
10
0
0
0
0
0
0
0.2500 V
0
0
1
0
1
0
0.7000 V
0.0250 V
0
Deeper S
leep/Extended D
eeper Sleep
11
0
1.2750 V
1
0.9375 V
11
01.2875 V
0
1
00
0
1
1
1
0
0
1
0
00
1
00
1
0
1
0.1375 V
10.0000 V
11
0.0000 V
1
0
0
1
1
1
0.5625 V
VID
(6:0)
01
1
0
1
1
1
1
1
1
0
1
0
1.0750 V
00
0
1
0.0125 V
1 1
0
0.1125 V
0
0
0.3875 V1.3875 V
1
0
0.0000 V0.0000 V
trace shorter than 1/2" to their respective Banias socket pins.
11
11
0
0
1
0
Voltage
0.8250 V
0
1
1
0
1
0
1.0875 V
0
0
1
0
1
0
0
1
0
1
0
0
3
1
0
0
0
1
0
0
0.4250 V
0
1
1
00
1
0
10
0
0
1
0
Deeper S
lp
0
0
1
1
1
0
0
1
1
Voltage
0
0
11
0
0
1
1
1
1
0.6500 V
10.8375 V
0
D
0.6250 V
1
0
0
Active M
ode
0
1
0
C
PAGE
1.4375 V
0 0
11
0
1
1
1
1.3750 V
1.0000 V
1
0
1
1
1
1
1
0
0.2750 V
1
0
PS
I2*
1
1
1
1.0500 V
1.4125 V
1
1
GTLR
EF : K
eep the Voltage divider w
ithin 0.5"
0
0
0
1
0
10
SAM
SUN
G PR
OPR
IET
AR
Y
0
1
0
1
1
0
0
0.8000 V
0
0.7750 V
0
0
1
1
0.7375 V
00
1
1
0
1
1
Active/D
eeper Sleep
1
1
1.1250 V
PAR
T NO.
0
0
0
0
1
1
0
1
1
1 0
CO
MP
0,2(CO
MP
1,3) should be connected with Zo=27.4ohm
(55ohm)
1
1
1
1
0.4500 V
0 0
1.3250 V0
0
0.7625 V
0
0
0
1
1
0
1
1
0
0
1
1
0.0000 V
0
0
0
0
0
0
0
1
0
1
B
1
1 0
0.6750 V
0
0
1
1.1500 V1
11
1
1.0125 V
1 0
1
0
from each of the V
CC
/VS
S test point vias.
1
1
1
0.8625 V
0
0
DP
RS
TP*
1
1
1
1
0
0
0
0
1
CHECK
1.2375 V
1 1
11
LAST EDIT
0
1
0
0
0.9875 V
0
1.2500 V
0
0
1
0.4125 V
1
0
0
0
1
11
0
1
1
011
0
1.2125 V
0
1
1
0
0 0
1
0
0
1
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1
1
1
0
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0
0
1
1
0.2125 V
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0
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0
0
0
0
THIS DOCUMENT CONTAINS CONFIDENTIAL
0
1.2000 V
1
0
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(6:0)
0
0
0
1
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0
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0
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1
1
1
0 or 1
1
1
0 1
0
1
1
0
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0
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1
1
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1
0.9250 V
1
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0
1
0
1
1
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0
1
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1 0
0
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0.9750 V
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0
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ithin 100mil of the V
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1
00
0
1
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1
01
0
Voltage
0
1
0
0
0.6625 V
Jun PARK
YM.A
HN
HJ.KIM
undefined
9/23/2008
PV
1.0
October 27, 2009 14:27:43 PM
BA
41-xxxxxA
959
Brem
en-LCPU
PENR
YN (2/3)
D:/users/m
obile24/mentor/Brem
en-L/PV/Bremen-L_M
AIN
1
54.9 1%
2
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567
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R526
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1%
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nostuff
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13-B1,29-C
1
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0
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31-D3
11-C4,12-A
3
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3
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100nF
1% R5191K
9-A4
11-C1
11-C4,12-A
3
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1
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3
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4
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AF5
VID_2
AE5
VID_3
AF4
VID_4
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AF3
VID_6
AE2
AE7
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J6VCCP_2
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T6VCCP_5
R6
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K21
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J21VCCP_8
M21
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AF7
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VID_1
TRST#
B26
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C7
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9-C3
0143854500|bga_479p_sock
CPU1-3
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S
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CPU2_TH
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www.bufanxiu.com
8-10 R530/R730
8. Block Diagram and Schematic
- -
- This Document can not be used without Samsung's authorization -
Samsung
ConfidentialSam
sung
ConfidentialSam
sung
Confidential4 / 4
OF
1
APPRO
VAL
BB
4
D
3
PROPRIETARY INFORMATION THAT IS
4
2
9/23/2008
undefined
HJ.KIM
YM.A
HN
Jun PARK
SAM
SUN
G PR
OPR
IET
AR
Y1
Prodlizer &
Cbulk com
mon used(S
ocket inside)
SAMSUNG ELECTRONICS COS PROPERTY.
D
SAMSUNG
3
2
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
THIS DOCUMENT CONTAINS CONFIDENTIAL
EXCEPT AS AUTHORIZED BY SAMSUNG.
PAGE
REV
DR
AW
PAR
T NO.
TITLE
LAST EDIT
DEV. STEP
A
ELECTRONICS
MO
DULE CODE
CHECK
C
DA
TE
A
C
D:/users/m
obile24/mentor/Brem
en-L/PV/Bremen-L_M
AIN
PENR
YN (3/3)
CPU
Brem
en-L
5910
BA
41-xxxxxA
October 27, 2009 14:27:43 PM
1.0
PV
10000nF-X5RC577 6.3V
6.3VC578 10000nF-X5R
10000nF-X5RC527 6.3V
6.3VC575 10000nF-X5R
10000nF-X5RC576 6.3V
6.3VC574 10000nF-X5R
10000nF-X5RC573 6.3V
6.3VC526 10000nF-X5R
6.3VC547 10000nF-X5R
10000nF-X5RC545 6.3V
10000nF-X5RC546 6.3V
6.3VC544 10000nF-X5R
6.3VC543 10000nF-X5R
10000nF-X5RC542 6.3V
10000nF-X5RC541 6.3V
6.3VC540 10000nF-X5R
CPU_C
ORE
CPU_C
ORE
VSS_91
E16
VSS_92
VSS_93
E19
E21
VSS_94
E24
VSS_95
E3
VSS_96
E6
VSS_97
VSS_98
E8
F11VSS_99
CPU_C
ORE
D11
VSS_82
D13
VSS_83
D16
VSS_84
D19
VSS_85
D23
VSS_86
D26
VSS_87
D4
VSS_88
D8
VSS_89
A8
VSS_9
E11
VSS_90
E14
C11
VSS_72
C14
VSS_73
C16
VSS_74
C19
VSS_75
C2
VSS_76
C22
VSS_77
C25
VSS_78
C5
VSS_79
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C8
VSS_80
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VSS_81
VSS_62
AF8
VSS_63
VSS_64
B11
B13
VSS_65
VSS_66
B16
B19
VSS_67
B21
VSS_68
B24
VSS_69
A25
VSS_7
B6
VSS_70
B8
VSS_71
AE4
VSS_53
AE8
VSS_54
AF11
VSS_55
AF13
VSS_56
AF16
VSS_57
AF19
VSS_58
AF2
VSS_59
A23
VSS_6
AF21
VSS_60
AF25
VSS_61
AF6
AD25
VSS_43
AD5
VSS_44
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VSS_45
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VSS_46
AE11
VSS_47
AE14
VSS_48
AE16
VSS_49
A2
VSS_5
AE19
VSS_50
AE23
VSS_51
AE26
VSS_52
VSS_33
AC6
VSS_34
VSS_35
AC8
AD11
VSS_36
AD13
VSS_37
AD16
VSS_38
AD19
VSS_39
A19
VSS_4
AD2
VSS_40
AD22
VSS_41
AB23
VSS_42
AB26
VSS_24
AB4
VSS_25
AB8
VSS_26
AC11
VSS_27
AC14
VSS_28
AC16
VSS_29
A16
VSS_3
AC19
VSS_30
AC21
VSS_31
AC24
VSS_32
AC3
Y24 VSS_161Y3 VSS_162Y6 VSS_163
AA5
VSS_17
AA8
VSS_18
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VSS_19
A14
VSS_2
AB11
VSS_20
AB13
VSS_21
AB16
VSS_22
AB19
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VSS_151V2 VSS_152
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AA19
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F8VSS_107
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G26
VSS_110
G4
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VCC_96
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VCC_97
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E13
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VCC_89
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E7
VCC_90
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VCC_91
F10VCC_92
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D12
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VCC_21
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VCC_23
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VCC_24
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9-C4,54-A
4
0143854500|bga_479p_sock
CPU1-4
PENRYN
R515
1001%
1001%
9-C4,54-A
4
CPU1_V
CCSENSE
CPU1_V
SSSENSE
R516
www.bufanxiu.com
8-11R530/R730
8. Block Diagram and Schematic
- -
- This Document can not be used without Samsung's authorization -
Samsung
ConfidentialSam
sung
ConfidentialSam
sung
Confidential
IDT : 1205-003159
SAMSUNG
VD
D_S
RC
_IO
BS
EL1
A
C
SR
C2
DA
TE
400 MH
z
EXCEPT AS AUTHORIZED BY SAMSUNG.
SR
C4
0
2
SA
TA
CLK
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Q E
333 MH
z
0
0
SR
C6
Pin 24/25
APPRO
VAL
LAST EDIT
CK
505M
0
4
VD
D_48
3
->delete and change layout? (EC
AE
)
D
THIS DOCUMENT CONTAINS CONFIDENTIAL
HIG
H
0DO
T_96/DO
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AR
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4
SR
C_0/S
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DE
00
0
MIN
I CA
RD
1
A
TITLE
Jun PARK
YM.A
HN
HJ.KIM
undefined
9/23/2008
PV
1.0
October 27, 2009 14:27:43 PM
BA
41-xxxxxA
1159
Brem
en-LM
AIN
_CLOCK_CIRCUIT
D:/users/m
obile24/mentor/Brem
en-L/PV/Bremen-L_M
AIN
CK_Clock_505M
1
DR
AW
VD
D_C
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CLK
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3_CLK
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B48
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B3_C
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RG
D
CP
U1_B
SE
L1
CLK
0_HC
LK1#
CLK
0_HC
LK1
CLK
0_HC
LK0#
www.bufanxiu.com
8-12 R530/R730
8. Block Diagram and Schematic
- -
- This Document can not be used without Samsung's authorization -
Samsung
ConfidentialSam
sung
ConfidentialSam
sung
Confidential1 O
F 5
VTT
HOST DATA BUSVTTLF
NC
HOST CONTROL HOST ADDRESS BUS
VC
C C
OR
E
CFG
CFG
(5)
APPRO
VALD
MI Lane R
eversal
Low
Sim
ultaneouslyM
ODULE CO
DE
PROPRIETARY INFORMATION THAT IS
CFG
(7)
A
*POC
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emove in M
P Model)
Enabled (def.)CHECK
CFG
(19)
DR
AW
2
PC
IE Loop B
ack Enable
PAR
T NO.
CFG
(6)
C
CFG
#
PCIE Loop Back Disable(def)iTP
M option
1
ELECTRONICS
DM
Ix2
REV
Only(def.)
DA
TE
SDVO or PCIE X1
(def. : default Option)
CFG
(9)
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
3
SD
VO
and PC
IE X
1
Current Setting
ME Crypto confidentiality (def.)
PAGE
Dynamic O
DT
SAMSUNG
DEV. STEP
THIS DOCUMENT CONTAINS CONFIDENTIAL
4
2
CFG
(20)
D
1608
TITLE
D
4
B
CFG
(16)
C
OF
iTPM
Host Interface E
nable
CFG
(10)
High
Norm
alJun PARK
YM.A
HN
HJ.KIM
undefined
9/23/2008
PV
1.0
October 27, 2009 14:27:43 PM
BA
41-xxxxxA
1259
Brem
en-LM
CH_CANTIGA_G
M_DDR
2
CANTIGA (1/5)
D:/users/m
obile24/mentor/Brem
en-L/PV/Bremen-L_M
AIN
B
ME
Crypto no confidentiality
3
PE
G R
eversal (def.)
LAST EDIT
SAM
SUN
G PR
OPR
IET
AR
Y
DM
I Lane Norm
al (def.)
iTPM Host Interface Disable (def.)
1
Dynam
ic OD
T Disabled
DM
Ix4 (def.)
SAMSUNG ELECTRONICS COS PROPERTY.
EXCEPT AS AUTHORIZED BY SAMSUNG.
A
24
3545 3940 02025
12-C4
53
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3041
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4
4
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9121730
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8
8-C1
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8-C1
22
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23
56
8-C3
32
8-C3
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1
52
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28
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16
T2VTT_6 T5VTT_7 T6VTT_8 T7VTT_9 T8
21
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VTT_2 T11
VTT_20 U7VTT_21 U8VTT_22 U9V1VTT_23 V2VTT_24 V3VTT_25
VTT_3 T12
VTT_4 T13VTT_5
VTTLF_3
L1
VTT_1 T10
VTT_10 T9
VTT_11 U1VTT_12 U10VTT_13 U11VTT_14 U12VTT_15 U13VTT_16 U2VTT_17 U3
VTT_18 U5
VCC_NCTF_41Y29 VCC_NCTF_42Y30 VCC_NCTF_43Y32 VCC_NCTF_44
AC29 VCC_NCTF_5AC30 VCC_NCTF_6AC32 VCC_NCTF_7AE29 VCC_NCTF_8AE30 VCC_NCTF_9
VTTLF_1
A8
VTTLF_2
AB2
AL32 VCC_NCTF_32AM30 VCC_NCTF_33AM32 VCC_NCTF_34U30 VCC_NCTF_35U32 VCC_NCTF_36V29 VCC_NCTF_37V30 VCC_NCTF_38W29 VCC_NCTF_39
AB30 VCC_NCTF_4
W30 VCC_NCTF_40W32
VCC_NCTF_22AK26 VCC_NCTF_23AK28 VCC_NCTF_24AK29 VCC_NCTF_25AK30 VCC_NCTF_26AK32 VCC_NCTF_27AL26 VCC_NCTF_28AL28 VCC_NCTF_29
AA32 VCC_NCTF_3
AL29 VCC_NCTF_30AL30 VCC_NCTF_31
VCC_NCTF_12AG30 VCC_NCTF_13AG32 VCC_NCTF_14AH29 VCC_NCTF_15AH30 VCC_NCTF_16AH32 VCC_NCTF_17AJ29 VCC_NCTF_18AJ32 VCC_NCTF_19
AA30 VCC_NCTF_2
AK23 VCC_NCTF_20AK24 VCC_NCTF_21AK25
Y34VCC_35
VCC_4 AB34VCC_5 AC26VCC_6 AC28VCC_7 AC33VCC_8 AC34VCC_9 AE26
AA29 VCC_NCTF_1
AE32 VCC_NCTF_10AF30 VCC_NCTF_11AG29
VCC_25 AK33VCC_26 AM33VCC_27 T32VCC_28 U33VCC_29
VCC_3 AA34
U34VCC_30 V33VCC_31 V34VCC_32 W33VCC_33 Y33VCC_34
VCC_15 AG25VCC_16 AG26VCC_17 AG33VCC_18 AG34VCC_19
VCC_2 AA33
AH23VCC_20 AH25VCC_21 AH28VCC_22 AJ23VCC_23 AJ26VCC_24 AJ33
F12H_R
S#_1
C8
H_R
S#_2
H_S
WING
C5
C9
H_TR
DY#
VCC_1 AA28
VCC_10 AE33
VCC_11 AF23VCC_12 AF25VCC_13 AF28AF33VCC_14 AG24
H_D
VREF
B11
H9
H_H
IT#E12
H_H
ITM#
H11
H_LO
CK#
H_R
COMP
E3
B15
H_R
EQ#_0
K13
H_R
EQ#_1
F13H_R
EQ#_2
B13
H_R
EQ#_3
B14
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EQ#_4
B6
H_R
S#_0
H_D
INV#_3
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PWR#
F9H_D
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L10H_D
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M7
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#_62AD6
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H_D
#_9
B10
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R#
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L3H_D
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#_52AD3
H_D
#_53AD7
H_D
#_54AE14
H_D
#_55AF3
H_D
#_56AC1
H_D
#_57AE3
H_D
#_58AC3
H_D
#_59
H2
H_D
#_6
AE11
H_D
#_60AE8
H_D
#_61
H_D
#_42AA9
H_D
#_43AA11
H_D
#_44AD11
H_D
#_45AD10
H_D
#_46AD13
H_D
#_47AE12
H_D
#_48AE9
H_D
#_49
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#_5
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#_50AD8
H_D
#_51AA3
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#_33Y6
H_D
#_34Y10
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#_35Y12
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#_36Y14
H_D
#_37Y7
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#_38W2
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#_39
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H_D
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H_D
#_23R1
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#_24N5
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#_25N6
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#_26P13
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#_27N8
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#_30M3
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#_31Y3
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#_32
H_D
#_13N12
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#_14J6
H_D
#_15P2
H_D
#_16L2
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#_17R2
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#_18N9
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#_19
F8H_D
#_2
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C15
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#_4F16
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#_6C18
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#_7M16
H_A
#_8J13
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#_9
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DS#
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H_A
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H_A
DSTB
#_1
H_A
VREF
A11
H_A
#_25L16
H_A
#_26C21
H_A
#_27J17
H_A
#_28H20
H_A
#_29
A14
H_A
#_3
B18
H_A
#_30K17
H_A
#_31B20
H_A
#_32F21
H_A
#_33K21
H_A
#_34L20
P17
H_A
#_15F17
H_A
#_16G20
H_A
#_17B19
H_A
#_18J16
H_A
#_19E20
H_A
#_20H16
H_A
#_21J20
H_A
#_22L17
H_A
#_23A17
H_A
#_24B17
CFG_6M24 CFG_7E21 CFG_8C23 CFG_9
HPLL_C
LKAH7
AH6
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P16
H_A
#_10R16
H_A
#_11N17
H_A
#_12M13
H_A
#_13E17
H_A
#_14
CFG_14M20 CFG_15L21 CFG_16H21 CFG_17P29 CFG_18R28 CFG_19
P25 CFG_2
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P20 CFG_3P24 CFG_4C25 CFG_5N24
0904-002376
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8-B1
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8-C3
MCH1_H
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MCH1_V
TTLF2_MN
MCH1_C
FG6_M
N
61 24
CPU1_LO
CK#
CPU1_R
S0#
CPU1_R
S1#
CPU1_R
S2#
CPU1_TR
DY#
CPU1_R
EQ#(4:0)
CPU1_D
PWR#
MCH1_H
VREF
MCH1_V
TTLF1_MN
MCH1_V
TTLF3_MN
MCH1_H
XSWING
MCH1_H
VREF
CPU1_B
SEL0
CPU1_B
SEL1
CPU1_B
SEL2
CPU1_D
#(63:0)CPU1_A
#(35:3)
CPU1_A
DS#
CPU1_A
DSTB
0#CPU1_A
DSTB
1#CPU1_B
NR#
CPU1_B
PRI#
CPU1_B
REQ#
CPU1_S
LP#
CPU1_C
PURST#
CLK
0_HCLK
1#CLK
0_HCLK
1
CPU1_D
BSY#
CPU1_D
EFE
R#
CPU1_D
BI0#
MCH1_H
XSWING
CPU1_D
BI1#
CPU1_D
BI2#
CPU1_D
BI3#
CPU1_D
RDY#
CPU1_D
STB
N0#
CPU1_D
STB
N1#
CPU1_D
STB
N2#
CPU1_D
STB
N3#
CPU1_D
STB
P0#
CPU1_D
STB
P1#
CPU1_D
STB
P2#
CPU1_D
STB
P3#
CPU1_H
IT#CPU1_H
ITM#
www.bufanxiu.com
8-13R530/R730
8. Block Diagram and Schematic
- -
- This Document can not be used without Samsung's authorization -
Samsung
ConfidentialSam
sung
ConfidentialSam
sung
Confidential2 O
F 5
LVDSHDA
NC
RS
VD
GFX
VC
C N
CTF
GFX
VC
C N
CTF
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VC
C
AGVVT
PC
IE G
FXP
CIE
GFX
DMICLKMEPMMISC
D
3
REV
CHECK
B
1
RSVD12
RSVD11
2PAG
E
PAR
T NO.
DR
AW
4
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
SAMSUNG ELECTRONICS COS PROPERTY.
1608
MO
DULE CODE
A C
ELTI
TET
AD
ME
Debug P
ort
SAMSUNG
2
B
C
RSVD10
THIS DOCUMENT CONTAINS CONFIDENTIAL
D
SAM
SUN
G PR
OPR
IET
AR
Y4
ELECTRONICS
A
EXCEPT AS AUTHORIZED BY SAMSUNG.
3
PROPRIETARY INFORMATION THAT IS
OF
1
APPRO
VAL
LAST EDIT
Jun PARK
YM.A
HN
HJ.KIM
undefined
9/23/2008
PV
1.0
October 27, 2009 14:27:43 PM
BA
41-xxxxxA
1359
Brem
en-LM
CH_CANTIGA_G
M_DDR
2
CANTIGA (2/5)
D:/users/m
obile24/mentor/Brem
en-L/PV/Bremen-L_M
AIN
RSVD13
DEV. STEP
20
14
31-B3
601
51
P3.3V
811
100nFC654 10V
4
11-B1
P1.05V
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G
2
100nFC688 10V
R704
1001%
31-D3
31-D1
14
1%49.9
R664
W26 VCC_AXG_NCTF_56W28 VCC_AXG_NCTF_57Y16 VCC_AXG_NCTF_58Y17 VCC_AXG_NCTF_59 AC16VCC_AXG_NCTF_6Y19 VCC_AXG_NCTF_60 AC17VCC_AXG_NCTF_7
AE16 VCC_AXG_NCTF_8AE17 VCC_AXG_NCTF_9
V26V28 VCC_AXG_NCTF_47W16 VCC_AXG_NCTF_48W17 VCC_AXG_NCTF_49
AB19VCC_AXG_NCTF_5
VCC_AXG_NCTF_50W19W20 VCC_AXG_NCTF_51W21 VCC_AXG_NCTF_52W23 VCC_AXG_NCTF_53VCC_AXG_NCTF_54W24W25 VCC_AXG_NCTF_55
U20 VCC_AXG_NCTF_37U21 VCC_AXG_NCTF_38V16 VCC_AXG_NCTF_39
AB17VCC_AXG_NCTF_4
V17 VCC_AXG_NCTF_40V19 VCC_AXG_NCTF_41V21 VCC_AXG_NCTF_42V23 VCC_AXG_NCTF_43V24 VCC_AXG_NCTF_44VCC_AXG_NCTF_45V25VCC_AXG_NCTF_46
AL16 VCC_AXG_NCTF_27AL19 VCC_AXG_NCTF_28AL21 VCC_AXG_NCTF_29
AB16VCC_AXG_NCTF_3
AM16 VCC_AXG_NCTF_30AM17 VCC_AXG_NCTF_31AM19 VCC_AXG_NCTF_32AM20 VCC_AXG_NCTF_33AM21 VCC_AXG_NCTF_34U16 VCC_AXG_NCTF_35U19 VCC_AXG_NCTF_36
AH16AH17 VCC_AXG_NCTF_18AH19 VCC_AXG_NCTF_19
AA19VCC_AXG_NCTF_2
AJ16 VCC_AXG_NCTF_20VCC_AXG_NCTF_21AJ19AK16 VCC_AXG_NCTF_22AK17 VCC_AXG_NCTF_23AK19 VCC_AXG_NCTF_24VCC_AXG_NCTF_25AK20AK21 VCC_AXG_NCTF_26
AB20VCC_AXG_8 AB23VCC_AXG_9
AA16VCC_AXG_NCTF_1
AE19 VCC_AXG_NCTF_10AF16 VCC_AXG_NCTF_11AF17 VCC_AXG_NCTF_12AF19 VCC_AXG_NCTF_13AG16 VCC_AXG_NCTF_14AG17 VCC_AXG_NCTF_15VCC_AXG_NCTF_16AG19VCC_AXG_NCTF_17
VCC_AXG_36 U14VCC_AXG_37 U15VCC_AXG_38 V15VCC_AXG_39 Y15
AA23VCC_AXG_4
Y21VCC_AXG_40VCC_AXG_41 Y24
VCC_AXG_42 Y26
AA24VCC_AXG_5 AA25VCC_AXG_6 AB15VCC_AXG_7
AH20AJ15VCC_AXG_27 AJ21VCC_AXG_28 AL15VCC_AXG_29
AA21VCC_AXG_3
VCC_AXG_30 AM14AM15VCC_AXG_31 AN14VCC_AXG_32 T14VCC_AXG_33VCC_AXG_34 T16T17VCC_AXG_35
AE21VCC_AXG_17 AE23VCC_AXG_18 AE24VCC_AXG_19
AA20VCC_AXG_2
AE25VCC_AXG_20 AF15VCC_AXG_21 AF20VCC_AXG_22 AG15VCC_AXG_23 AG21VCC_AXG_24VCC_AXG_25 AH15
VCC_AXG_26
C31
TV_D
CONSEL_0
E32
TV_D
CONSEL_1
H24
TV_R
TN
AA15VCC_AXG_1
AB25VCC_AXG_10 AC20VCC_AXG_11 AC21VCC_AXG_12 AC23VCC_AXG_13 AC24VCC_AXG_14 AE15VCC_AXG_15 AE20VCC_AXG_16
AL34 RSVD_6RSVD_7AM35RSVD_8AN35AY21 RSVD_9
SDVO_C
TRLC
LKG36
E36
SDVO_C
TRLD
ATA
THERMTR
IP#
T20
TSATN
#B12
F25TV
A_D
AC
TVB_D
AC
H25
K25
TVC_D
AC
K12M1 RSVD_17
RSVD_18M36N36 RSVD_19
AH12 RSVD_2
R33 RSVD_20T24 RSVD_21T33 RSVD_22
AH13 RSVD_3AH9 RSVD_4AK34 RSVD_5
PM_SYNC#
R29
PWROK
AT40
AT11
RSTIN
#
AH10 RSVD_1
B2 RSVD_10B31 RSVD_11BF18 RSVD_12BF23 RSVD_13BG23 RSVD_14BH18 RSVD_15RSVD_16
M48
PEG_TX_3 M39PEG_TX_4 M43R47PEG_TX_5PEG_TX_6 N37PEG_TX_7 T39U36PEG_TX_8PEG_TX_9 U39
PM_D
PRSTP
#B7
N33
PM_EXT_TS
#_0PM_EXT_TS
#_1P32
T40PEG_TX#_8 U37PEG_TX#_9 U40
J42PEG_TX_0PEG_TX_1 L46
PEG_TX_10 Y39Y46PEG_TX_11PEG_TX_12 AA36PEG_TX_13 AA39PEG_TX_14 AD42PEG_TX_15 AD46
PEG_TX_2
PEG_TX#_11 AA46PEG_TX#_12 AA37AA40PEG_TX#_13 AD43PEG_TX#_14PEG_TX#_15 AC46
PEG_TX#_2 M47M40PEG_TX#_3PEG_TX#_4 M42PEG_TX#_5 R48N38PEG_TX#_6PEG_TX#_7
L43PEG_RX_3 L41PEG_RX_4 N40P47PEG_RX_5PEG_RX_6 N43
PEG_RX_7 T42U42PEG_RX_8PEG_RX_9 Y42
PEG_TX#_0 J41PEG_TX#_1 M46
PEG_TX#_10 Y40
T43PEG_RX#_8 U43PEG_RX#_9 Y43
H43PEG_RX_0PEG_RX_1 J44
PEG_RX_10 W47PEG_RX_11 Y37PEG_RX_12 AA42PEG_RX_13 AD36
PEG_RX_14 AC48PEG_RX_15 AD40
PEG_RX_2
PEG_RX#_11 Y36PEG_RX#_12 AA43AD37PEG_RX#_13 AC47PEG_RX#_14PEG_RX#_15 AD39
PEG_RX#_2 L44L40PEG_RX#_3 N41PEG_RX#_4PEG_RX#_5 P48PEG_RX#_6 N44PEG_RX#_7
A6 NC_6B4 NC_7B45 NC_8NC_9B47
F43PEG_C
LKPEG_C
LK#
E43
PEG_C
OMPI
T37T36
PEG_C
OMPO
PEG_RX#_0 H44PEG_RX#_1 J46
PEG_RX#_10 Y48
C3NC_36C46NC_37C48NC_38D2NC_39D47
A47 NC_4
NC_40E1
NC_41E48F1 NC_42NC_43F48
A5 NC_5
NC_26BG48NC_27BH2NC_28BH3NC_29BH43
A46 NC_3
BH44 NC_30BH46 NC_31NC_32BH47NC_33BH5NC_34BH6NC_35
BE47 NC_16NC_17BF1
NC_18BF3BF46 NC_19
A44 NC_2
NC_20BF48NC_21BG1NC_22BG2NC_23BG4NC_24BG45BG47 NC_25
L_CTR
L_DATA
L_DDC_C
LKK33J33
L_DDC_D
ATA
M29
L_VDD_EN
A43 NC_1
B48 NC_10BC1 NC_11BC48 NC_12BD1 NC_13BD48 NC_14BE2 NC_15
LVDSB_D
ATA
_1G38
LVDSB_D
ATA
_2F37K37
LVDSB_D
ATA
_3
C44
LVDS_IB
GLVDS_VBG
B43
E37
LVDS_VREFH
E38
LVDS_VREFL
L32L_B
KLT_C
TRL
G32
L_BKLT_E
N
M32
L_CTR
L_CLK
M33
H48
D45
LVDSA_D
ATA
_1LVDSA_D
ATA
_2F40
LVDSA_D
ATA
_3B40
LVDSB_C
LKA37
B37
LVDSB_C
LK#
LVDSB_D
ATA
#_0A41
LVDSB_D
ATA
#_1H38
LVDSB_D
ATA
#_2G37J37
LVDSB_D
ATA
#_3
LVDSB_D
ATA
_0B42
B30
HDA_SDI
B29
C29
HDA_SDO
A28
HDA_SYNC
ICH_SYNC#
H36
C40
LVDSA_C
LKLVDSA_C
LK#
C41
LVDSA_D
ATA
#_0H47
LVDSA_D
ATA
#_1E46
G40
LVDSA_D
ATA
#_2LVDSA_D
ATA
#_3A40
LVDSA_D
ATA
_0
E41
DPLL_R
EF_S
SCLK
DPLL_R
EF_S
SCLK#
F41
DPRSLPVR
R32
B33
GFX
_VID_0
GFX
_VID_1
B32
G33
GFX
_VID_2
F33GFX
_VID_3
GFX
_VID_4
E33
C34
GFX
_VR_EN
HDA_BCLK
B28
HDA_R
ST#
AH40
DMI_R
XP_3
AE35
DMI_TX
N_0
AE43
DMI_TX
N_1
AE46
DMI_TX
N_2
AH42
DMI_TX
N_3
DMI_TX
P_0
AD35
AE44
DMI_TX
P_1
AF46
DMI_TX
P_2
AH43
DMI_TX
P_3
B38
DPLL_R
EF_C
LKDPLL_R
EF_C
LK#
A38
CRT_TV
O_IR
EF
L29CRT_V
SYNC
DDPC_C
TRLC
LKN28
DDPC_C
TRLD
ATA
M28
AE41
DMI_R
XN_0
AE37
DMI_R
XN_1
AE47
DMI_R
XN_2
AH39
DMI_R
XN_3
DMI_R
XP_0
AE40
AE38
DMI_R
XP_1
AE48
DMI_R
XP_2
CL_P
WROK
AN36
CL_R
ST#
AJ35
CL_V
REF
AH34
E28
CRT_B
LUE
H32
CRT_D
DC_C
LKJ32
CRT_D
DC_D
ATA
G28
CRT_G
REEN
J29CRT_H
SYNC
CRT_IR
TNG29
J28CRT_R
ED
E29
0904-002376
EB88C
TPM
U7-2
CLK
REQ#
K36
AH37
CL_C
LKCL_D
ATA
AH36
10KR622
C655 100nF 10V
47
65
85
5
C685 100nF 10V
213
1
100nFC657 10V
100nFC749 10V
19-C4
100nFC723 10V
19-B4
11-B1
69
10V
31-D1
11-B4
100nFC783 10V
C656 100nF
C748 10V
60
54-C4
9-D4,29-C
1
100nF
1112
31-D1
31-C1
100nFC728 10V
9
100nFC686 10V
13
10V
73
20
C777 100nF
R599
210
38
0nostuff
1312
15
100nFC722 10V
100nFC708 10VC100 100nF 10V
0
19-D4,30-C
134-A
4,40-D4
42-C2,44-B
3
P1.05V
31-C131-C
3,54-C4
1
31-C1
31-D1
1% 499R671
10V
9-C4,29-B
1
31-D1
C782 100nF 10V
C702 100nF
100nFC104 10V
31-D1
711
812
19-A4
10V
5
31-D1
10V
4
C765 100nF
C729 100nF 10V
C687 100nF
100nFC810
10V
31-C1
56R595
415
P1.05V
31-C1
13
100nFC776 10V
14
31-B3,44-C
4
C730 100nF 10V
31-D1
13
100nFC732 10V
311
9
31-D1
1%
10V
31-C1
31-D1
10KR638
1
19-C4
C758 100nF
141
9
C108 100nF 10V
10V
1%R639
10K
100nFC101 10VC707 100nF
7
31-B3,44-C
4
31-C1
10V
10
31-D1
10
C731 100nF
R679
1K
P3.3V
31-D1
1%
100nFC757 10V
11-B4
15
C744 100nF 10V
PEG1_TXN14_MN
PEG1_TXP0_MNPEG1_TXP1_MNPEG1_TXP2_MNPEG1_TXP3_MNPEG1_TXP4_MNPEG1_TXP5_MNPEG1_TXP6_MN
CPU1_TH
RMTR
IP#
PEG1_TXP11_MN
PEG1_TXN7_MNPEG1_TXN6_MN
PEG1_TXN9_MNPEG1_TXN8_MN
PEG1_TXN11_MNPEG1_TXN10_MN
PEG1_TXN13_MNPEG1_TXN12_MN
PEG1_TXN15_MN
PEG1_TXP13_MNPEG1_TXP12_MN
PEG1_TXP15_MNPEG1_TXP14_MN
PEG1_TXN1_MNPEG1_TXN0_MN
PEG1_TXN3_MNPEG1_TXN2_MN
PEG1_TXN5_MNPEG1_TXN4_MN
PEG1_TX
P(15:0)
PEG1_TXP7_MN
PEG1_TXP9_MNPEG1_TXP8_MN
PEG1_TXP10_MN
PEG1_TX
N(15:0)
MCH1_C
L_VREF_M
N
MCH3_E
XTTS
0#_MN
PLT3_R
ST#_R
_MN
PLT3_R
ST#
MCH3_E
XTTS
1#_MN
PEG1_R
XN(15:0)
PEG1_R
XP(15:0)
MCH3_C
LKREQ#
MCH3_IC
HSYNC#
MCH3_C
LKREQ#
CLK
1_MCH3G
PLL#
CLK
1_MCH3G
PLL
CHP3_C
L_RST_0#
KBC3_P
WRGD
CPU1_D
PRSTP
#
DMI1_TX
N_0
DMI1_TX
P_0
DMI1_TX
N_1
DMI1_TX
P_1
DMI1_TX
N_2
DMI1_TX
P_2
DMI1_TX
N_3
DMI1_TX
P_3
DMI1_R
XN_0
DMI1_R
XP_0
DMI1_R
XN_1
DMI1_R
XP_1
DMI1_R
XN_2
DMI1_R
XP_2
DMI1_R
XN_3
DMI1_R
XP_3
CHP3_C
L_CLK
_0CHP3_C
L_DATA
_0KBC3_P
WRGD
CHP3_D
PRSLP
VR
CHP3_P
M_S
YNC#
MCH3_TSATN#_MN
MCH1_C
OMPIO_R
_MN
www.bufanxiu.com
8-14 R530/R730
8. Block Diagram and Schematic
- -
- This Document can not be used without Samsung's authorization -
Samsung
ConfidentialSam
sung
ConfidentialSam
sung
Confidential3 O
F 5
SY
STE
M M
EM
OR
Y A
SYSTEM MEMORY A
SY
STE
M M
EM
OR
Y B
SYSTEM MEMORY B
3
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
4O
FPAG
E
DD
R3 : C
onnect to VR
M.
DD
R2 : G
ND
DA
TE
PLA
CE
EA
CH
CA
P N
EA
R A
V42 P
IN
C
Cantiga
EXCEPT AS AUTHORIZED BY SAMSUNG.
10nF->100nF
SM
_PW
RO
K
CHECK
SM
_RC
OM
P# : 80 ohm
to VS
S
2
A C
A
DD
R2
TITLE
SAMSUNG ELECTRONICS COS PROPERTY.
SM
_RC
OM
P : 80 ohm
to P1.8V
_AU
X
LAST EDIT
3
PAR
T NO.
MO
DULE CODE
1
PROPRIETARY INFORMATION THAT IS
B
1
APPRO
VAL
4SA
MSU
NG
PRO
PRIE
TA
RY
B
ELECTRONICS
CANTIGA (3/5)
MCH_CANTIG
A_GM
_DDR2
Brem
en-L
5914
BA
41-xxxxxA
October 27, 2009 14:27:43 PM
1.0
PV
9/23/2008
HJ.KIM
YM.A
HN
Jun PARKD
EV. STEP
REV
D
THIS DOCUMENT CONTAINS CONFIDENTIAL
Route as short as possible
2
SAMSUNG
D
DR
AW
R715
3.01K
51-B117-C
3,18-C3
32
17-B4
1%
2453
63
1
717
57
11
0
17-D4
36
3
31
11
1213
23