Alexandru Alice431G

Sample and Hold Circuits

1. Theoretical considerations

The first figure shows the wave forms characteristic to the ideal functioning of a sample and hold (S/H) circuit.

A S/H circuit has two fundamental working modes, determined by the value of the logic signal at the control input:

- SAMPLE mode: the circuit acquires rapidly (instantaneous – for the ideal circuit) the input signal, reproducing it at the output. The output signal tracks the input one.

- HOLD mode: as soon as the control signal changes its value, the circuit switches rapidly (instantaneous – for the ideal circuit) in the hold mode. The circuit provides at the output the input value at the moment of the mode switch.

Therefore, the circuit follows the input analogic signal, the output signal freezing at the instantaneous input value when the control signal transition occurs.

These circuits are named both sample and hold and track and hold circuits. A S/H circuit has a very small sample duration with respect to the signal’s time scale, while the T/H circuit has a sample duration comparable to the signal’s time scale.

These circuits are used in applications where the signal processing is discontinuous or when rapidly varying signals need to be multiplexed and transmitted to a data acquisition system.

Alexandru Alice431G

The second figure shows the working principle of a S/H circuit. It contains an analogic switch. At the sampling command, it retains the instantaneous input value as a continuous voltage inside the capacitor C. Therefore, the quality requirements for a S/H circuit are the following:

- The capacitor used as memory should charge and reach the final voltage value as quickly as possible;

- In the memory stage, the output variation with respect to time (Vo/t) should be as small as possible.

The following schematic respects the previous requirements by reducing to the minimum the influence of the signal source and the load.

The circuit is quick enough, but due to the fact that the two amplifiers work independently, the errors introduced by each one are added. If the precision is more important than the working speed, a feedback loop is needed.

It may be noticed that when the switch is in the S position, the output voltage is equal to the input one no matter if the switch is ideal or not. In the H position, the operation amplifier AO1 is in open loop configuration, the output becomes saturated and the circuit enters slowly in the sampling mode.

In the hold mode, the capacitor discharges with a current I p=I A+ IK off+ IC

Where IA is the input polarization current of AO1, IK off is the rezidual current of the switch in the blocking state (H) and IC is the capacitor leakage current.

For constant current I, we obtain a variation rate of the memorised voltage:∆V o∆ t

= IC

2

Alexandru Alice431G

The S/H circuit studied in this laboratory work has the following schematic:

In the sampling mode, the switches K2 and K3 are closed and K1 is open. The AO2 operational amplifier works as voltage follower (as AO1, which has the feedback loop closed through K2 and AO2). Both AO1 and AO2 should have the slew rate big enough to follow the signal’s edges. The charging rate of capacitor C1 may be limited by the maximum output value of AO1. The capacitor C2 is discharged through K3.

If we suppose that both operational amplifiers are ideal and that they work in the linear regime, we obtain that:

V C 1=V O=V iTherefore, the output follows the input. The deviations from this formula are given by the

static and dynamic non-ideal characteristics of the operational amplifiers.In the hold mode, the switches K2 and K3 are open and K1 is closed. By opening K2, the

global feedback loop is interrupted; AO1 still has a closed feedback loop because K1 is closed and the saturation of AO1’s output is avoided.

The storage is done using the capacitor C1. Because we avoided using operational amplifiers with low input polarization currents, we need to reduce the contribution of IA in the IP expression. The current is minimized by using FET switches. The IC current is minimized by choosing accordingly the capacitor C1. In the feedback loop a capacitor identical with C1 is introduced.

3

Alexandru Alice431G

2. Laboratory work

Circuit’s schematic:

1. By turning the potentiometer P1 we adjust the offset voltage of the circuit.We connect the circuit in the sample mode: VC = 0 (E/M input is connected to the

ground; pin 13 is connected with 14). VI is connected to the ground also (pin 1 is connected with pin 2). We measure the output voltage with the millivoltmeter and the adjust P1 until VO becomes 0.

2. We need to sample a sine wave (VIpp=2 V, f = 100Hz, connect pin 1 with pin 2). Apply at the control input (connect pin 13 with pin 6) a TTL signal with 50% duty factor and a frequency of 2KHz.

4

Alexandru Alice431G

View the wave forms of v1 (connect pin 5 with pin 8), v13 (connect pin 7 with pin 8), v12 (connect pin 12 with pin 8), v11 (connect pin 11 with pin 8) and the voltages on the collector of transistor Q4 (connect pin 21 with pin 8) and Q5 (connect pin 22 with pin 8).

Blue – v1

Red – v13

Blue – v1

Red – v13

We can notice the S/H behaviorof the circuit.

Blue – vin

Red – v12

Blue – v21

Red – v22

3. Determine the maximum load current of the storage capacitor. The circuit is put in sample mode (VC=0, connect pin 13 with pin 14). Apply at the input a rectangular signal (Vipp=5V, f=1KHz) with 50% duty factor (connect pin 1 to pin 4).

Using the scope, measure the edge duration tr and the signal’s amplitude at the capacitor terminals (v12pp). The load current is computed using the following relation:

Imax=C1

V 12 pp

t r

5

Alexandru Alice431G

The obtained value will be compared with the maximum value of the AO1 output current (IOmax=20…25mA) and the maximum value of the FET current (IDSS=50mA).

The variation rate of the output signal (V12pp/tr) will be compared with the maximum variation rate of the signal from the AO’s output (aprox. 0.5V/μs).

t r=240 μs

Imax=10−6 5.52240∗10−6 =23mA→Imax≅ IOmax ; Imax< IDSS

v=v12 pp

t r=23V / μs>0.5V /μs

4. To determine the total loss current we apply a continuous voltage Vi of approx. 5V (connect pin 1 with pin 3). Connect the voltmeter at the output of the S/H circuit (connect pin 10 with pin 11). We switch to the hold mode from the sampling mode leaving an open circuit at the control input (pin 13) which was initially connected to the ground (pin 13 connected with pin 14). We measure t in which the output voltage decreases with vo=0.5V and determine Ip using the formula above.

Imax=10−6 0.542.8

=11.6nA

5. Disconnect the circuit that reduces the polarization currents by short-circuiting the capacitor C2 (connect pin 18 with pin 19). Make the same measurements as before.

Imax=10−6 0.54.3

=116nA

3. Questions

1. Estimate the range in which the input signal can have values for the S/H circuit.The input values range is limited by the breakdown voltage of the capacitor C1.

2. Inspect the stability of the S/H circuit knowing that the switch resistance while conducting is rds,on100Ω. P2 can be neglected.In the ground of C1 there is rds,on||RinAO2. RinAO2 is supposed to be high, therefore the resistance seen by C1 is only rds,on. The capacitor introduces the pole in the frequency characteristic given by its time constant.

6

Alexandru Alice431G

→f p=1

2 πrC1=1.6kHz

The feedback loop of AO1 formed by C1 and AO2 introduce another pole in the circuit’s frequency characteristic. At high frequencies, the two poles determine the circuit instability.

3. What factors impose the minimum and maximum values for the capacitor C1?The most important factor is the circuit’s stability.

4. Indicate what capacitor type may be used for C1 and justify.For C1 we may use polystyrene capacitor because it should have a small charging time and low losses.

5. Which is the minimum absolute value of VEE?The minimum absolute value of VEE depends on the limit supply voltage of the operational amplifiers and on the input voltage limit.

6. What is the role of diodes D1, D2 and D3?D1 represents a protection for J1 because the on its gate may appear voltage high enough to destroy it (AO1 works as voltage follower and V[-15;15]V). D2 and D3 have the same role for J2 and J3, respectively.

7. What is the role of R5 and how can it be determined? Does the circuit work when R5=0?If R5=0, then rds on is shunted and the capacitor C1 sees a very small resistance. At high frequencies, C2 introduces a pole in the circuit’s frequency characteristic. R5 is introduced to move the pole such that the circuit is stable.

11. Describe the AO2 behavior in the hold mode.In hold mode, the AO2 has the following configuration:IP=I

+

V C 1=1C1∫ i

+ dt

V o=1C 2∫ i

− dt

I+=I−VC1=VO

14. How is the circuit modified if the supply voltage is only one positive supply? But for a negative supply?

If the circuit is supplied only from a positive source, the maximum input amplitude is modified. If the source is negative, the minimum input amplitude is modified.15. What is the role of the potentiometer P2?

The potentiometer allows the adjustment of Rech in series with C1 such that it allows the movement of the pole introduced by C1 and the circuit to remain stable.16. Draw an inverting S/H circuit.

7