Sam Palermo TAMU High Speed IO

8/10/2019 Sam Palermo TAMU High Speed IO

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Sam Palermo

Analog & Mixed-Signal Center

Texas A&M University

ECEN620: Network Theory

Broadband Circuit DesignFall 2013

Lecture 1: Introduction


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Why Broadband Circuits?

Broadband circuits are used in many wireline andwireless communication systems

Trends in processor design and the growing

demand for digital connectivity are pushing datarates and bandwidth requirements in thesesystems

In this class, we will study key clocking, amplifier,and logic circuits that enable thesecommunication systems to scale in performance

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Class Topics

Broadband circuit design methodologies

Clocking circuits

Phase-Locked Loops (PLLs)

Clock-and-Data Recovery systems (CDRs)

Broadband amplifiers

Transimpedance, limiting, and variable-gain amplifers

High-Speed Logic Design techniques for high-speed CMOS and CML logic

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Analog Circuit Sequence

326

Pre/Co-Requisite

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Administrative

Instructor: Sam Palermo

315E WERC Bldg., 845-4114, [email protected]

Office hours: MW 2:00pm-3:30pm

Lectures: MWF 10:20am-11:10am, ZACH 223A

Class web page http://www.ece.tamu.edu/~spalermo/ecen620.html

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Class Material

Textbook: Class Notes and Technical Papers Key References

Phaselock Techniques, F. Gardner, John Wiley & Sons, 2005.

Design of Integrated Circuits for Optical Communications, B.

Razavi, McGraw-Hill, 2003. Phase-Locked Loops: Design, Simulation, & Applications, R. Best,

McGraw-Hill, 1997.

Broadband Circuits for Optical Fiber Communication, E. Sackinger,Wiley, 2005.

Design of Analog CMOS Integrated Circuits, B. Razavi, McGraw-Hill, 2001.

Class notes

Will hand out hard copies in class

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Grading

Exams (60%) Three midterm exams (20% each)

Homework (20%)

Collaboration is allowed, but independent simulations and write-ups Need to setup CADENCE simulation environment

No late homework will be graded

Final Project (20%) Groups of 1-2 students

Report and PowerPoint presentation required

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Prerequisites

Circuits ECEN474 or approval of instructor

Basic knowledge of CMOS gates, flops, etc

Circuit simulation experience (HSPICE, Spectre)

Systems

Basic knowledge of s- and z-transforms MATLAB experience

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Simulation Tools

Matlab

Cadence

90nm CMOS device models Can use other technology models if they are a

130nm or more advanced CMOS node

Other tools, schematic, layout, etc areoptional

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Preliminary Schedule

Dates may change with reasonable notice

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High-Speed Electrical Link System

TX

Channel

TXdata

Serializer

PLLref clk

RX

Deserializer

RXdata

TX clk RX clk

D[n+1]D[n] D[n+2] D[n+3]TX data

TX clk

RX clk

CDR

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PLL Performance TxPLL RxPLL

Min freq (GHz) 8.98 8.96

Max freq (GHz) 13.54 13.47

Mean freq (GHz) 11.26 11.22

Lock range (GHz) 4.56 4.52

+/-20.2% +/-20.1%

Fine tune hold range 5.8% 5.8%

Quarter rate clock phase noise

@ 10MHz offset (dBc/Hz)

-117.8 -117.7

Jitter, 1MHz-100MHz (ps rms) 1.5 1.4

Jitter, fc/1667-100MHz (ps rms) 0.64 0.64

-20

-15

-10

-5

0

5

0.1 1 10

Frequency (MHz)

Gain(dB) (2MHz,-3dB)

Measured Jitter Transfer Function

10GHz PLL Example

100mW Power consumption

(with clock distribution)

[Meghelli (IBM) ISSCC 2006]

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High-Speed Logic Example:Divide-by-2 with CML FF

High-speed logic blocks are required in numerous high-speed circuits, such as PLLs, CDRs, and equalizers

Relative to CMOS logic, current-mode logic (CML) circuitscan achieve higher bandwidth due to lower self-loading

Additional bandwidth extension can be achieved with theaddition of passives (inductors) and feedback

[Razavi]

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Detailed Serial-Link Receiver Architecture

Key Features:

- Half-rate design

- 5-tap continuously adaptive DFE- Variable gain amplifier

- Digital CDR

- ESD protection (HBM & CDM)

- 130mW (with DFE and CDR logic)

T-Coil Compensation

Network

50

In_P

In_N

(10Gb/s)

ESD

VGA

Vcm

PI PI

Phase rotator

2:8

DMUX

8:16

DMUX

CDR

logic

I-Clock control

Q-Clock control

I Q

DFE

logic

Tap weights

C2-I C2-Q

Edge

DataAmp

From on-chip PLL (5GHz)

CML

CMOS logicVDDA=1.2V

8

2

D0

D1

D2

D3

2

2

2

(2.5

Gb/s)

1

1

1

1VDDIO=1V

DFE

Block

Phase

detector

VDD=1.0V

Data

Amp

EdgeClock

[Meghelli (IBM) ISSCC 2006] 14


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CDR Loop

Data

Z-1

Z-1

DMUX XORs

D

E

D

E

Early

Late

Digital

Filter

I Rotator

Control

Q Rotator

Control

PID/A

PID/A

C2-I

C2-Q

Fromo

n-chipPLL

Data Clock

Edge Clock

Key Features:

- Fully digital loop

- Can handle up to +/- 4000ppm

frequency offset

- Independent I,Q control

Jitter Tolerance

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.00E+05 1.00E+06 1.00E+07 1.00E+08 1.00E+09

Modulation Frequency

SineJitter(U

Ipp)

Receiver Jitter tolerance curve ( BER


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Variable-Gain Amplif ier (VGA) Example

Key Features: Dual Diff Amps

Half/Full Amplitude

Switched R Degen

7 Bit Thermometer

Multi-bit Slewrate

Glitchless Operation

Continuous Adjustment

Optimized with GA

[Sorna (IBM) ISSCC 2005]


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Optical Receiver Front-End

[Razavi]

Transimpedance amplifiers (TIAs) convert an inputcurrent signal into an output voltage with a

transimpedance gain Limiting amplifier amplifies the TIA output to a

reliable level to achieve a given BER with a certaindecision element (comparator)

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Next Time

Linear circuit analysis review

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Sam Palermo TAMU High Speed IO