S6E2CC Series - cdn.rowleydownload.co.ukcdn.rowleydownload.co.uk/arm/packages/targets/FM4/...Spansion Inc. issues data sheets with advance information or preliminary designations to

S6E2CC Series 32-bit ARM® Cortex®-M4F based Microcontroller S6E2CC8H0A/S6E2CC9H0A/S6E2CCAH0A/ S6E2CC8J0A/S6E2CC9J0A/S6E2CCAJ0A/ S6E2CC8L0A/S6E2CC9L0A/S6E2CCAL0A

Data Sheet (Preliminary)

Publication Number S6E2CC_DS709-00009 Revision 0.1 Issue Date September 30, 2014 CONFIDENTIAL

Notice to Readers: This document states the current technical specifications regarding the Spansion

product(s) described herein. The Preliminary status of this document indicates that product qualification has

been completed, and that initial production has begun. Due to the phases of the manufacturing process that

require maintaining efficiency and quality, this document may be revised by subsequent versions or

modifications due to changes in technical specifications.

D a t a S h e e t ( P r e l i m i n a r y )

2 S6E2CC_DS709-00009-0v01-E, September 30, 2014 CONFIDENTIAL

Notice On Data Sheet Designations

Spansion Inc. issues data sheets with advance information or preliminary designations to advise readers of

product information or intended specifications throughout the product life cycle, including development,

qualification, initial production, and full production. In all cases, however, readers are encouraged to verify

that they have the latest information before finalizing their design. The following descriptions of Spansion

data sheet designations are presented here to highlight their presence and definitions.

Advance Information

The Advance Information designation indicates that Spansion Inc. is developing one or more specific

products, but has not committed any design to production. Information presented in a document with this

designation is likely to change, and in some cases, development on the product may discontinue. Spansion

Inc. therefore places the following conditions upon Advance Information content:

“This document contains information on one or more products under development at Spansion Inc.

The information is intended to help you evaluate this product. Do not design in this product without

contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this

proposed product without notice.”

Preliminary

The Preliminary designation indicates that the product development has progressed such that a commitment

to production has taken place. This designation covers several aspects of the product life cycle, including

product qualification, initial production, and the subsequent phases in the manufacturing process that occur

before full production begins. Changes to the technical specifications presented in a Preliminary document

should be expected while keeping these aspects of production under consideration. Spansion places the

following conditions upon Preliminary content:

“This document states the current technical specifications regarding the Spansion product(s)

described herein. The Preliminary status of this document indicates that product qualification has

been completed and that initial production has begun. Due to the phases of the manufacturing

process that require maintaining efficiency and quality, this document may be revised by subsequent

versions or modifications to accommodate changes in technical specifications.”

Combination

Some data sheets contain a combination of products with different designations (Advance Information,

Preliminary, or Full Production). This type of document distinguishes these products and their designations

wherever necessary, typically on the first page, the ordering information page, and pages with the DC

Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first

page refers the reader to the notice on this page.

Full Production (No Designation on Document)

When a product has been in production for a period of time such that no changes or only nominal changes

are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include

those affecting the number of ordering part numbers available, such as the addition or deletion of a speed

option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a

description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following

conditions to documents in this category:

“This document states the current technical specifications regarding the Spansion product(s)

described herein. Spansion Inc. deems the products to have been in sufficient production volume

such that subsequent versions of this document are not expected to change. However,

typographical or specification corrections, or modifications to the valid combinations offered may

occur.”

Questions regarding these document designations may be directed to your local sales office.

S6E2CC Series 32-bit ARM® Cortex®-M4F based Microcontroller S6E2CC8H0A/S6E2CC9H0A/S6E2CCAH0A/ S6E2CC8J0A/S6E2CC9J0A/S6E2CCAJ0A/ S6E2CC8L0A/S6E2CC9L0A/S6E2CCAL0A

Data Sheet (Preliminary)

Publication Number S6E2CC_DS709-00009 Revision 0.1 Issue Date September 30, 2014 CONFIDENTIAL

This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications.

1. Description

S6E2CC Series is a family of highly integrated 32-bit microcontrollers dedicated for embedded controllers

with high performance and competitive cost.

This series is based on the ARM Cortex-M4F processor with on-chip flash memory and SRAM, and has

peripherals such as motor control timers, A/D converters, and communications interfaces (USB, CAN, UART,

CSIO (SPI), I2C, LIN).

The products that are described in this data sheet are placed into TYPE3-M4 product categories "FM4

Family Peripheral Manual Main Part (MN709-00001)."

Note:

− ARM and Cortex are the registered trademarks of ARM Limited in the EU and other countries.



Table of Contents

1. Description ............................................................................................................................................... 3

2. Features .................................................................................................................................................... 6

3. Product Lineup ...................................................................................................................................... 15

4. Packages ................................................................................................................................................ 17

5. Pin Assignments .................................................................................................................................... 18

6. Pin Descriptions .................................................................................................................................... 22

7. I/O Circuit Type ...................................................................................................................................... 75

8. Handling Precautions ............................................................................................................................ 83

8.1. Precautions for Product Design ..................................................................................................... 83

8.2. Precautions for Package Mounting ................................................................................................ 84

8.3. Precautions for Use Environment .................................................................................................. 86

9. Handling Devices ................................................................................................................................... 87

10. Block Diagram ........................................................................................................................................ 90

11. Memory Size ........................................................................................................................................... 91

12. Memory Map ........................................................................................................................................... 91

13. Pin Status In Each CPU State ............................................................................................................... 97

14. Electrical Characteristics .................................................................................................................... 107

14.1. Absolute Maximum Ratings ....................................................................................................... 107

14.2. Recommended Operating Conditions ........................................................................................ 109

14.3. DC Characteristics ..................................................................................................................... 114

14.3.1. Current Rating................................................................................................................ 114

14.3.2. Pin Characteristics ......................................................................................................... 124

14.4 AC Characteristics ...................................................................................................................... 126

14.4.1. Main Clock Input Characteristics .................................................................................... 126

14.4.2. Sub Clock Input Characteristics ..................................................................................... 127

14.4.3. Built-In CR Oscillation Characteristics ........................................................................... 127

14.4.4. Operating Conditions of Main PLL (in the case of using main clock for input clock of

PLL) ....................................................................................................................... 128

14.4.5. Operating Conditions of USB/Ethernet PLL・I2S PLL (in the case of using main clock for

input clock of PLL) ........................................................................................................... 128

14.4.6. Operating Conditions of Main PLL (in the case of using built-in high-speed CR clock for input

clock of main PLL) ........................................................................................................... 129

14.4.7. Reset Input Characteristics ............................................................................................ 129

14.4.8. Power-On Reset Timing ................................................................................................. 130

14.4.9. GPIO Output Characteristics ......................................................................................... 130

14.4.10. External Bus Timing ..................................................................................................... 131

14.4.11. Base Timer Input Timing .............................................................................................. 142

14.4.12. CSIO (SPI) Timing ....................................................................................................... 143

14.4.13. External Input Timing ................................................................................................... 176

14.4.14. Quadrature Position/Revolution Counter Timing .......................................................... 177

14.4.15. I2C Timing .................................................................................................................... 179

14.4.16. SD Card Interface Timing ............................................................................................ 181

14.4.17. ETM/ HTM Timing ........................................................................................................ 183

14.4.18. JTAG Timing ................................................................................................................ 184

14.4.19. Ethernet-MAC Timing .................................................................................................. 185

14.4.20. I2S Timing .................................................................................................................... 190

14.4.21. High-Speed Quad SPI Timing ...................................................................................... 195

14.5. 12-bit A/D Converter .................................................................................................................. 197

14.6. 12-bit D/A Converter .................................................................................................................. 200

14.7. USB Characteristics ................................................................................................................... 201

14.8. Low-Voltage Detection Characteristics ...................................................................................... 205


September 30, 2014, S6E2CC_DS709-00009-0v01-E 5 CONFIDENTIAL

14.8.1. Low-Voltage Detection Reset ........................................................................................ 205

14.8.2. Interrupt of Low-Voltage Detection ................................................................................. 205

14.9. MainFlash Memory Write/Erase Characteristics ........................................................................ 206

14.10. Dual Flash Memory Write/Erase Characteristics ...................................................................... 206

14.11. Standby Recovery Time ........................................................................................................... 207

14.11.1. Recovery cause: Interrupt/WKUP ................................................................................ 207

14.11.2. Recovery Cause: Reset ............................................................................................... 209

15. ORDERING INFORMATION ................................................................................................................. 211

16. PACKAGE DIMENSIONS ..................................................................................................................... 212

17. Major Changes ..................................................................................................................................... 216



2. Features

32-bit ARM Cortex-M4F Core

Processor version: r0p1

Up to 200 MHz frequency operation

FPU built-in

Support DSP instructions

Memory protection unit (MPU): improves the reliability of an embedded system

Integrated nested vectored interrupt controller (NVIC): 1 NMI (non-maskable interrupt) and 128 peripheral

interrupts and 16 priority levels

24-bit system timer (Sys Tick): system timer for OS task management

On-chip Memories

Flash memory

This series is based on two independent on-chip flash memories.

− Up to 2048 Kbytes

− Built-in flash accelerator system with 16 Kbytes trace buffer memory

− Read access to flash memory that can be achieved without wait-cycle up to an operating frequency of

72 MHz. Even at the operating frequency more than 72 MHz, an equivalent single cycle access to

flash memory can be obtained by the flash accelerator system.

− Security function for code protection

SRAM

This is composed of three independent SRAMs (SRAM0, SRAM1 and SRAM2). SRAM0 is connected to the

I-code bus or D-code bus of Cortex-M4F core. SRAM1 and SRAM2 are connected to system bus of

Cortex-M4F core.

− SRAM0: up to 192 Kbytes

− SRAM1: 32 Kbytes

− SRAM2: 32 Kbytes

External Bus Interface

Supports SRAM, NOR, NAND flash and SDRAM device

Up to 9 chip selects CS0 to CS8 (CS8 is only for SDRAM)

8/16/32-bit data width

Up to 25-bit address bus

Supports address/data multiplexing

Supports external RDY function

Supports scramble function

Possible to set the validity/invalidity of the scramble function for the external areas 0x6000_0000 to

0xDFFF_FFFF in 4 Mbytes units.

Possible to set two kinds of the scramble key

Note: It is necessary to use the Spansion provided software library to use the scramble function.



USB Interface (Max 2 Channels)

The USB interface is composed of a function and a host.

USB function

− USB 2.0 Full-speed supported

− Max 6 EndPoint supported

− EndPoint 0 is control transfer

− EndPoint 1, 2 can be selected bulk-transfer, interrupt-transfer or isochronous-transfer

− EndPoint 3 to 5 can select bulk-transfer or interrupt-transfer

− EndPoint 1 to 5 comprise double buffer

− The size of each endpoint is as follows.

− Endpoint 0, 2 to 5: 64 byte

− EndPoint 1: 256 byte

USB host

− USB2.0 Full-Speed/Low-Speed supported

− Bulk-transfer, interrupt-transfer, and isochronous-transfer support

− USB Device connected/dis-connected automatically detect

− IN/OUT token handshake packet automatically

− Max 256-byte packet length supported

− Wake-up function supported

CAN Interface (Max 2 Channels)

Compatible with CAN specification 2.0A/B

Maximum transfer rate: 1 Mbps

Built-in 32-message buffer

CAN-FD Interface (1 Channel)

Compatible with CAN Specification 2.0A/B

Maximum transfer rate: 5 Mbps

Message buffer for receiver: up to 192 messages

Message buffer for transmitter: up to 32 messages

CAN with flexible data rate



Multi-function Serial Interface (Max 16 channels)

Separate 64 byte receive and transmit FIFO buffers for channels 0 to 7.

Operation mode is selectable for each channel from the following:

− UART

− CSIO (SPI)

− LIN

− I2C

UART

− Full-duplex double buffer

− Selection with or without parity supported

− Built-in dedicated baud rate generator

− External clock available as a serial clock

− Various error detect functions available (parity errors, framing errors, and overrun errors)

CSIO (SPI)


− Built-in dedicated baud rate generator

− Overrun error detect function available

− Serial chip select function (ch 6 and ch 7 only)

− Supports high-speed SPI (ch 4 and ch 6 only)

− Data length 5 to 16-bit

LIN

− LIN protocol Rev.2.1 supported


− Master/slave mode supported

− LIN break field generation (can change to 13- to 16-bit length)

− LIN break delimiter generation (can change to 1- to 4-bit length)

− Various error detect functions available (parity errors, framing errors, and overrun errors)

I2C

− Standard mode (Max 100 kbps)/Fast mode (Max 400 kbps) supported

− Fast mode Plus (Fm+) (Max 1000 kbps, only for ch 3 = ch A and ch 7 = ch B) supported

DMA Controller (8 channels)

DMA controller has an independent bus, so the CPU and DMA controller can process simultaneously.

Eight independently configured and operated channels

Transfer can be started by software or request from the built-in peripherals

Transfer address area: 32-bit (4 GB)

Transfer mode: Block transfer/Burst transfer/Demand transfer

Transfer data type: bytes/half-word/word

Transfer block count: 1 to 16

Number of transfers: 1 to 65536

DSTC (Descriptor System data Transfer Controller; 256 Channels)

The DSTC can transfer data at high-speed without going via the CPU. The DSTC adopts the descriptor

system and, following the specified contents of the descriptor that has already been constructed on the

memory, can access directly the memory/peripheral device and perform the data-transfer operation.

It supports the software activation, the hardware activation, and the chain activation functions.



A/D Converter (Max 32 channels)

12-bit A/D Converter

− Successive approximation type

− Built-in three units

− Conversion time: 0.5 μs at 5V

− Priority conversion available (priority at two levels)

− Scanning conversion mode

− Built-in FIFO for conversion data storage (for SCAN conversion: 16 steps, for priority conversion: 4

steps)

D/A Converter (Max 2 Channels)

R-2R type

12-bit resolution

Base Timer (Max 16 Channels)

Operation mode is selected from the following for each channel:

16-bit PWM timer

16-bit PPG timer

16/32-bit reload timer

16/32-bit PWC timer

General Purpose I/O Port

This series can use its pins as general purpose I/O ports when they are not used for external bus or

peripherals; moreover, the port relocate function is built in. It can set the I/O port to which the peripheral

function can be allocated.

Capable of pull-up control per pin

Capable of reading pin level directly

Built-in port-relocate function

Up to 120 high-speed general-purpose I/O ports in 144 pin package

Some pins 5V tolerant I/O.

See "6. Pin Descriptions" and "7. I/O Circuit Type" for the corresponding pins.



Multi-function Timer (Max 3 Units)

The multi-function timer is composed of the following blocks:

Minimum resolution: 5.00 ns

16-bit free-run timer × 3 ch/unit

Input capture × 4 ch/unit

Output compare × 6 ch/unit

A/D activation compare × 6 ch/unit

Waveform generator × 3 ch/unit

16-bit PPG timer × 3 ch/unit

The following functions can be used to achieve the motor control:

PWM signal output function

DC chopper waveform output function

Dead time function

Input capture function

A/D convertor activate function

DTIF (motor emergency stop) interrupt function

Real-Time Clock (RTC)

The real-time clock can count year, month, day, hour, minute, second, or day of the week from 01 to 99.

Interrupt function with specifying date and time (year/month/day/hour/minute/second/day of the week) is

available. This function is also available by specifying only year, month, day, hour, or minute.

Timer interrupt function after set time or each set time.

Capable of rewriting the time with continuing the time count.

Leap year automatic count is available.

Quadrature Position/Revolution Counter (QPRC; Max 4 Channels)

The Quadrature Position/Revolution Counter (QPRC) is used to measure the position of the position

encoder. It is also possible to use up/down counter.

The detection edge of the three external event input pins AIN, BIN and ZIN is configurable.

16-bit position counter

16-bit revolution counter

Two 16-bit compare registers

Dual Timer (32/16-bit Down Counter)

The dual timer consists of two programmable 32/16-bit down counters.

Operation mode is selectable from the following for each channel:

Free-running

Periodic (= Reload)

One shot

Watch Counter

The watch counter is used for wake up from low-power consumption mode. It is possible to select the main

clock, sub clock, built-in high-speed CR clock, or built-in low-speed CR clock as the clock source.

Interval timer: up to 64 s (max) with a sub clock of 32.768 kHz



External Interrupt Controller Unit

External interrupt input pin: Max 32 pins

Include one non-maskable interrupt (NMI)

Watchdog Timer (2 Channels)

A watchdog timer can generate interrupts or a reset when a time-out value is reached.

This series consists of two different watchdogs: a "hardware" watchdog and a "software" watchdog.

The hardware watchdog timer is clocked by low-speed internal CR oscillator. The hardware watchdog is thus

active in any power saving mode except RTC mode and Stop mode.

Cyclic Redundancy Check (CRC) Accelerator

The CRC accelerator helps to verify data transmission or storage integrity.

CCITT CRC16 and IEEE-802.3 CRC32 are supported.

CCITT CRC16 generator polynomial: 0x1021

IEEE-802.3 CRC32 generator polynomial: 0x04C11DB7

Programmable Cyclic Redundancy Check (PRGCRC) Accelerator

The CRC accelerator helps a verify data transmission or storage integrity.

CCITT CRC16, IEEE-802.3 CRC32 and generating polynomial are supported.

CCITT CRC16 generator polynomial: 0x1021

IEEE-802.3 CRC32 generator polynomial: 0x04C11DB7

Generating polynomial

SD Card Interface

It is possible to use the SD card that conforms to the following standards.

Part 1 Physical Layer Specification version 3.01

Part E1 SDIO Specification version 3.00

Part A2 SD Host Controller Standard Specification version 3.00

1-bit or 4-bit data bus

Ethernet-MAC

Compliant with IEEE802.3 specification

10 Mbps/100 Mbps data transfer rates supported

MII/RMII for external PHY device supported.

MII: Max one channel

RMII: Max one channel

Full-duplex and half-duplex mode supported.

Wake-ON-LAN supported

Built-in dedicated descriptor-system DMAC

Built-in 2 Kbytes transmit FIFO and 2 Kbytes receive FIFO.

Compliant IEEE1558-2008 (PTP)



I2S (Inter-IC Sound Bus) Interface (TX x 1 channel, RX x 1 channel)

Supports three transfer protocols

− I2S

− Left justified

− DSP mode

− Separate clock generation block for flexible system integration options

Master/slave mode selectable

RX Only, TX Only or TX and RX simultaneous operation selectable

Word length is programmable from 7-bits to 32 bits

RX/TX FIFO integrated (RX: 66 words x 32-bits, TX: 66 words x 32-bits)

DMA, interrupts, or polling based data transfer supported

HDMI-CEC/Remote Control Receiver (Max 2 Channels)

HDMI-CEC transmitter

− Header block automatic transmission by judging signal free

− Generating status interrupt by detecting arbitration lost

− Generating START, EOM, ACK automatically to output CEC transmission by setting 1 byte data

− Generating transmission status interrupt when transmitting 1 block (1 byte data and EOM/ACK)

HDMI-CEC receiver

− Automatic ACK reply function available

− Line-error detection function available

Remote control receiver

− 4 bytes reception buffer

− Repeat code detection function available

High-Speed Quad SPI

Up to 66 MHz clock rates for very fast data transfers to and from SPI compatible devices.

Up to 256 Mbytes of memory mapped address space.

Single data rate (SDR)

Supports single, dual, and quad data modes

Built-in direct mode and command sequencer mode

− Direct mode: Access by use of transmission FIFO/reception FIFO (up to16 word x 32 bit)

− Command sequencer mode: Automatic access assigned to external device area.

Clock and Reset

Clocks

Five clock sources (two external oscillators, two internal CR oscillators, and main PLL) that are dynamically

selectable.

− Main clock : 4 MHz to 48 MHz

− Sub clock : 30 kHz to 100 kHz

− High-speed internal CR clock : 4 MHz

− Low-speed internal CR clock : 100 kHz

− Main PLL Clock

Resets

− Reset requests from INITX pin

− Power on reset

− Software reset

− Watchdog timer reset

− Low-voltage detector reset

− Clock supervisor reset



Clock Supervisor (CSV)

Clocks generated by internal CR oscillators are used to supervise abnormality of the external clocks.

External OSC clock failure (clock stop) is detected, reset is asserted.

External OSC frequency anomaly is detected, interrupt or reset is asserted.

Low-Voltage Detector (LVD)

This Series include two-stage monitoring of voltage on the VCC pins. when the voltage falls below the

voltage that has been set, the low-voltage detector function generates an interrupt or reset.

LVD1: error reporting via interrupt

LVD2: auto-reset operation

Low-power Consumption Mode

Six low power consumption modes are supported.

Sleep

Timer

RTC

Stop

Deep standby RTC (selectable from with/without RAM retention)

Deep standby stop (selectable from with/without RAM retention)

Peripheral Clock Gating

The system can reduce the current consumption of the total system with gating the operation clocks of

peripheral functions not used.

VBAT

The consumption power during the RTC operation can be reduced by supplying the power supply

independent from the RTC (calendar circuit)/32 kHz oscillation circuit. The following circuits can also be

used.

RTC

32-kHz oscillation circuit

Power-on circuit

Back up register: 32 bytes

Port circuit

Debug

Serial wire JTAG debug port (SWJ-DP)

Embedded trace macrocells (ETM) provide comprehensive debug and trace facilities.

AHB trace macrocells (HTM)

Unique ID

Unique value of the device (41-bit) is set.



Power Supply

Five power supplies

− Wide range voltage : VCC = 2.7V to 5.5V

− Power supply for USB ch 0 I/O : USBVCC0 = 3.0V to 3.6V (when USB is used)

= 2.7V to 5.5V (when GPIO is used)

− Power supply for USB ch 1 I/O : USBVCC1 = 3.0V to 3.6V (when USB is used)


− Power supply for Ethernet-MAC I/O : ETHVCC = 3.0V to 5.5V (when Ethernet is used.)


− Power supply for VBAT : VBAT = 1.65V to 5.5V



3. Product Lineup

Memory Size

Product Name S6E2CC8H/J/L S6E2CC9H/J/L S6E2CCAH/J/L

On-chip flash memory 1024 Kbytes 1536 Kbytes 2048 Kbytes

On-chip SRAM 128 Kbytes 192 Kbytes 256 Kbytes

SRAM0 64 Kbytes 128 Kbytes 192 Kbytes



Function

Product Name

S6E2CC8H0A

S6E2CC9H0A

S6E2CCAH0A

S6E2CC8J0A

S6E2CC9J0A

S6E2CCAJ0A

S6E2CC8L0A

S6E2CC9L0A

S6E2CCAL0A

Pin count 144 176/192 216

CPU Cortex-M4F, MPU, NVIC 128 ch

Freq. 200 MHz

Power supply voltage range 2.7V to 5.5V

USB2.0 (function/host) 2 ch

Ethernet-MAC MII: 1 ch /RMII: 1 ch

CAN 2 ch (Max)

CAN-FD 1 ch

DMAC 8ch

DSTC 256 ch

External bus interface

Addr: 25-bit (Max),

Data: 8/16-bit

CS: 9 (Max),

SRAM,

NOR flash

NAND flash

Addr: 25-bit (Max),

Data: 8/16-bit

CS: 9 (Max),

SRAM,

NOR flash ,

NAND flash

SDRAM

Addr: 25-bit (Max),

Data: 8/16/32-bit

CS: 9 (Max),

SRAM,

NOR flash ,

NAND flash,

SDRAM

Multi-function serial interface

(UART/CSIO/LIN/I2C)

16ch (Max)

ch 0 to ch 7：FIFO, ch 8 to ch 15：No FIFO

Base timer

(PWC/Reload timer/PWM/PPG) 16 ch (Max)

MF

tim

er

A/D activation compare 6 ch

3 units (Max)

Input capture 4 ch

Free-run timer 3 ch

Output compare 6 ch

Waveform generator 3 ch

PPG 3 ch

SD card interface 1 unit

I2S - 1 unit

HDMI-CEC/ remote control receiver 2 ch

High-speed quad SPI - 1 unit

QPRC 4 ch (Max)

Dual timer 1 unit

Real-time clock 1 unit

Watch counter 1 unit

CRC accelerator Yes (fixed, programmable)

Watchdog timer 1 ch (SW) + 1 ch (HW)



Product Name

S6E2CC8H0A

S6E2CC9H0A

S6E2CCAH0A

S6E2CC8J0A

S6E2CC9J0A

S6E2CCAJ0A

S6E2CC8L0A

S6E2CC9L0A

S6E2CCAL0A

External interrupts 32 pins (Max)+ NMI × 1

I/O ports 120 pins (Max) 152 pins (Max) 190 pins (Max)

12-bit A/D converter 24 ch (3 units) 32 ch (3 units)

12-bit D/A converter 2 units (Max)

CSV (clock supervisor) Yes

LVD (low-voltage detector) 2 ch

Built-in CR High-speed 4 MHz (±2%)

Low-speed 100 kHz (Typ)

Debug function SWJ-DP/ETM/HTM

Unique ID Yes

Note:

− All signals of the peripheral function in each product cannot be allocated by limiting the pins of

package.

It is necessary to use the port relocate function of the I/O port according to your function use.

− See “14.4.3 Built-In CR Oscillation Characteristics” for the accuracy of the built-in CR.



4. Packages

Product Name

Package

S6E2CC8H0A

S6E2CC9H0A

S6E2CCAH0A

S6E2CC8J0A

S6E2CC9J0A

S6E2CCAJ0A

S6E2CC8L0A

S6E2CC9L0A

S6E2CCAL0A

LQFP: FPT-144P-M08 (0.5-mm pitch) - -


BGA : LBE192 (0.8-mm pitch) - -


: Supported

Note:

− See "16. PACKAGE DIMENSIONS" for detailed information on each package.



5. Pin Assignments

FPT-144P-M08

Note:

− The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the

relocated port number. For these pins, there are multiple pins that provide the same function for the

same channel.

Use the extended port function register (EPFR) to select the pin.

(Top View)

VS

S

P81/U

DP

0

P80/U

DM

0

US

BV

CC

0

P60/S

IN4_0/IN

T31_0/W

KU

P3/C

EC

1_0

P61/U

HC

ON

X0/S

OT

4_0/M

AL

E_0/R

TC

CO

_0/S

UB

OU

T_0

P62/S

CK

4_0/M

WE

X_0

P63/A

DT

G_3/R

TS

4_0/IN

T30_0/M

OE

X_0

P6E

/AD

TG

_5/S

CK

4_1/IC

23_1/IN

T29_0/E

_P

PS

PD

2/C

TS

4_1/F

RC

K2_1/E

_T

XE

N

PD

1/IN

T31_1/E

_T

X00

PD

0/IN

T30_1/E

_T

X01

PC

F/R

TS

4_1/IN

T12_0/E

_T

X02

PC

E/S

IN4_1/IN

T15_0/E

_T

X03

PC

D/S

OT

4_1/IN

T14_0/E

_T

XE

R

PC

C/E

_T

CK

PC

B/IN

T28_0/E

_C

OU

T

VS

S

ET

HV

CC

PC

A/T

IOA

15_0/E

_C

RS

PC

9/T

IOB

15_0/E

_C

OL

PC

8/E

_R

XC

K_R

EF

CK

PC

7/IN

T13_0/E

_M

DC

/CR

OU

T_1

PC

6/T

IOA

14_0/E

_M

DIO

PC

5/T

IOB

14_0/E

_R

XD

V

PC

4/T

IOA

7_0/E

_R

X00

PC

3/T

IOB

7_0/E

_R

X01

PC

2/T

IOA

6_0/E

_R

X02

PC

1/T

IOB

6_0/E

_R

X03

PC

0/E

_R

XE

R

P04/T

DO

/SW

O

P03/T

MS

/SW

DIO

P02/T

DI

P01/T

CK

/SW

CL

K

P00/T

RS

TX

VC

C

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

VCC 1 108 VSS

PA0/RTO20_0/TIOA8_0/AIN2_0/INT00_0/MADATA00_0 2 107 P83/UDP1

PA1/RTO21_0/TIOA9_0/BIN2_0/MADATA01_0 3 106 P82/UDM1

PA2/RTO22_0/TIOA10_0/ZIN2_0/MADATA02_0 4 105 USBVCC1

PA3/RTO23_0/TIOA11_0/MADATA03_0 5 104 P20/NMIX/WKUP0

PA4/RTO24_0/TIOA12_0/MADATA04_0 6 103 P21/ADTG_4/SIN0_0/INT27_0/CROUT_0

PA5/SIN1_0/RTO25_0/TIOA13_0/INT01_0/MADATA05_0 7 102 P22/AN31/SOT0_0/INT26_0

PA6/SOT1_0/DTTI2X_0/MADATA06_0 8 101 P23/UHCONX1/AN30/SCK0_0/TIOB13_1

PA7/SCK1_0/IC20_0/MADATA07_0 9 100 P24/AN29/TIOA13_1/MAD18_0

PA8/SIN7_0/IC21_0/INT02_0/WKUP1/MADATA08_0 10 99 P25/AN28/RX1_0/INT25_0/MAD17_0

PA9/SOT7_0/IC22_0/MADATA09_0 11 98 P26/TX1_0/MAD16_0

PAA/SCK7_0/IC23_0/MADATA10_0 12 97 P27/AN27/SIN5_0/INT24_0/MAD15_0

PAB/SCS70_0/RX0_0/FRCK2_0/INT03_0/MADATA11_0 13 96 P28/AN26/SOT5_0/MAD14_0

PAC/SCS71_0/TX0_0/TIOB8_0/AIN3_0/MADATA12_0 14 95 P29/AN25/SCK5_0/MAD13_0

PAD/SCK3_0/TIOB9_0/BIN3_0/MADATA13_0 15 94 P2A/AN24/CTS5_0/MAD12_0

PAE/ADTG_0/SOT3_0/TIOB10_0/ZIN3_0/MADATA14_0 16 93 P1F/AN15/RTS5_0/TIOB8_1/INT27_1/MAD11_0

PAF/SIN3_0/TIOB11_0/INT16_0/MADATA15_0 17 92 P1E/AN14/TIOA8_1/INT26_1/MAD10_0

P08/SIN14_0/TIOB12_0/INT17_0/MDQM0_0 18 91 P1D/AN13/SCK12_0/TIOB5_2/TRACED3

P09/SOT14_0/TIOB13_0/INT18_0/MDQM1_0 19 90 P1C/AN12/SOT12_0/TIOA5_2/TRACED2

P0A/ADTG_1/SCK14_0/AIN2_1/MCLKOUT_0 20 89 P1B/AN11/SIN12_0/TIOB4_2/INT11_0/TRACED1

P32/BIN2_1/INT19_0/S_DATA1_0 21 88 P1A/AN10/SCK2_0/TIOA4_2/TRACED0

P33/FRCK0_0/ZIN2_1/S_DATA0_0 22 87 P19/AN09/SOT2_0/TIOB3_2/INT24_1/TRACECLK

P34/IC03_0/INT00_1/S_CLK_0 23 86 P18/AN08/SIN2_0/TIOA3_2/INT10_0

VCC 24 85 P17/AN07/SCK11_0/TIOB2_2/ZIN1_2

VSS 25 84 P16/AN06/SOT11_0/TIOA2_2/BIN1_2

P35/IC02_0/INT01_1/S_CMD_0 26 83 P15/AN05/SIN11_0/TIOB1_2/AIN1_2/INT09_0

P36/IC01_0/INT02_1/S_DATA3_0 27 82 P14/AN04/SOT6_1/TX1_1

P37/IC00_0/INT03_1/S_DATA2_0 28 81 P13/AN03/SIN6_1/RX1_1/INT25_1

P38/ADTG_2/DTTI0X_0/S_WP_0 29 80 P12/AN02/SCK10_0/TIOA1_2/ZIN0_2

P39/SIN2_1/RTO00_0/TIOA0_1/AIN3_1/INT16_1/S_CD_0/MAD24_0 30 79 P11/AN01/SOT10_0/TIOB0_2/BIN0_2

P3A/SOT2_1/RTO01_0/TIOA1_1/BIN3_1/INT17_1/MAD23_0 31 78 P10/AN00/SIN10_0/TIOA0_2/AIN0_2/INT08_0

P3B/SCK2_1/RTO02_0/TIOA2_1/ZIN3_1/INT18_1/MAD22_0/MNALE_0 32 77 AVRH

P3C/SIN13_0/RTO03_0/TIOA3_1/INT19_1/MAD21_0/MNCLE_0 33 76 AVRL

P3D/SOT13_0/RTO04_0/TIOA4_1/MAD20_0/MNWEX_0 34 75 AVSS

P3E/SCK13_0/RTO05_0/TIOA5_1/MAD19_0/MNREX_0 35 74 AVCC

VSS 36 73 VCC

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

VC

C

P40/S

IN3_1/R

TO

10_0/T

IOA

0_0/A

IN0_0/IN

T23_0/M

CS

X7_0

P41/S

OT

3_1/R

TO

11_0/T

IOA

1_0/B

IN0_0/M

CS

X6_0

P42/S

CK

3_1/R

TO

12_0/T

IOA

2_0/Z

IN0_0/M

CS

X5_0

P43/S

IN15_0/R

TO

13_0/T

IOA

3_0/IN

T04_0/M

CS

X4_0

P44/S

OT

15_0/R

TO

14_0/T

IOA

4_0/M

CS

X3_0

P45/S

CK

15_0/R

TO

15_0/T

IOA

5_0/M

CS

X2_0 C

VS

S

VC

C

P7D

/SC

K1_1/R

X2_0/D

TT

I1X

_0/IN

T05_0/W

KU

P2/M

CS

X1_0

P7E

/AD

TG

_7/T

X2_0/F

RC

K1_0/M

CS

X0_0

INIT

X

P46/X

0A

P47/X

1A

VB

AT

P48/V

RE

GC

TL

P49/V

WA

KE

UP

P70/A

DT

G_8/S

IN1_1/IN

T06_0/M

RD

Y_0/C

EC

0_0

P71/S

OT

1_1/M

AD

00_0

P72/S

IN9_0/T

IOB

0_0/IN

T07_0/M

AD

01_0

P73/S

OT

9_0/T

IOB

1_0/M

AD

02_0

P74/S

CK

9_0/T

IOB

2_0/M

AD

03_0

P75/S

IN8_0/T

IOB

3_0/A

IN1_0/IN

T20_0/M

AD

04_0

P76/S

OT

8_0/T

IOB

4_0/B

IN1_0/M

AD

05_0

P77/S

CK

8_0/T

IOB

5_0/Z

IN1_0/M

AD

06_0

P78/S

IN6_0/IC

10_0/IN

T21_0/M

AD

07_0

P79/S

OT

6_0/IC

11_0/M

AD

08_0

P7A

/SC

K6_0/IC

12_0/M

AD

09_0

P7B

/DA

1/S

CS

60_0/IC

13_0/IN

T22_0

P7C

/DA

0/S

CS

61_0/IN

T04_1

PE

0/M

D1

MD

0

PE

2/X

0

PE

3/X

1

VS

S

LQFP - 144



FPT-176P-M07

Note:



same channel.


(Top View)

VS

S

P81/U

DP

0

P80/U

DM

0

US

BV

CC

0

P60/S

IN4_0/IN

T31_0/W

KU

P3/C

EC

1_0

P61/U

HC

ON

X0/S

OT

4_0/M

AL

E_0/R

TC

CO

_0/S

UB

OU

T_0

P62/S

CK

4_0/M

WE

X_0

P63/A

DT

G_3/R

TS

4_0/IN

T30_0/M

OE

X_0

P64/C

TS

4_0/R

TO

25_1/IN

T29_1

P65/R

TO

24_1/IN

T28_1

P6E

/AD

TG

_5/S

CK

4_1/IC

23_1/IN

T29_0/E

_P

PS

PD

2/C

TS

4_1/F

RC

K2_1/E

_T

XE

N

PD

1/IN

T31_1/E

_T

X00

PD

0/IN

T30_1/E

_T

X01

PC

F/R

TS

4_1/IN

T12_0/E

_T

X02

PC

E/S

IN4_1/IN

T15_0/E

_T

X03

PC

D/S

OT

4_1/IN

T14_0/E

_T

XE

R

PC

C/E

_T

CK

PC

B/IN

T28_0/E

_C

OU

T

VS

S

ET

HV

CC

PC

A/T

IOA

15_0/E

_C

RS

PC

9/T

IOB

15_0/E

_C

OL

PC

8/E

_R

XC

K_R

EF

CK

PC

7/IN

T13_0/E

_M

DC

/CR

OU

T_1

PC

6/T

IOA

14_0/E

_M

DIO

PC

5/T

IOB

14_0/E

_R

XD

V

PC

4/T

IOA

7_0/E

_R

X00

PC

3/T

IOB

7_0/E

_R

X01

PC

2/T

IOA

6_0/E

_R

X02

PC

1/T

IOB

6_0/E

_R

X03

PC

0/E

_R

XE

R

P95/R

TS

5_1/Q

_C

S0_0

P94/C

TS

5_1/Q

_S

CK

_0

P93/S

CK

5_1/IN

T15_1/Q

_IO

0_0

P92/S

OT

5_1/IN

T14_1/Q

_IO

1_0

P91/S

IN5_1/IN

T13_1/Q

_IO

2_0

P90/IN

T12_1/Q

_IO

3_0

P04/T

DO

/SW

O

P03/T

MS

/SW

DIO

P02/T

DI

P01/T

CK

/SW

CL

K

P00/T

RS

TX

VC

C

176

175

174

173

172

171

170

169

168

167

166

165

164

163

162

161

160

159

158

157

156

155

154

153

152

151

150

149

148

147

146

145

144

143

142

141

140

139

138

137

136

135

134

133

VCC 1 132 VSS









P50/SCS72_0/RTO00_1/TIOA8_2/MADATA16_0 10 123 P25/AN28/RX1_0/INT25_0/MAD17_0

P51/SCS73_0/RTO01_1/TIOB8_2/MADATA17_0 11 122 P26/TX1_0/MAD16_0

P52/RTO02_1/TIOA9_2/MADATA18_0 12 121 P27/AN27/SIN5_0/INT24_0/MAD15_0

PA8/SIN7_0/IC21_0/INT02_0/WKUP1/MADATA08_0 13 120 P28/AN26/SOT5_0/MAD14_0

PA9/SOT7_0/IC22_0/MADATA09_0 14 119 P29/AN25/SCK5_0/MAD13_0

PAA/SCK7_0/IC23_0/MADATA10_0 15 118 P2A/AN24/CTS5_0/MAD12_0

PAB/SCS70_0/RX0_0/FRCK2_0/INT03_0/MADATA11_0 16 117 P1F/AN15/RTS5_0/TIOB8_1/INT27_1/MAD11_0

PAC/SCS71_0/TX0_0/TIOB8_0/AIN3_0/MADATA12_0 17 116 P1E/AN14/TIOA8_1/INT26_1/MAD10_0

PAD/SCK3_0/TIOB9_0/BIN3_0/MADATA13_0 18 115 PB7/AN23/TIOB12_1/TRACED7

PAE/ADTG_0/SOT3_0/TIOB10_0/ZIN3_0/MADATA14_0 19 114 PB6/AN22/SCK8_1/TIOA12_1/TRACED6

PAF/SIN3_0/TIOB11_0/INT16_0/MADATA15_0 20 113 PB5/AN21/SOT8_1/TIOB11_1/INT11_1/TRACED5

P08/SIN14_0/TIOB12_0/INT17_0/MDQM0_0 21 112 PB4/AN20/SIN8_1/TIOA11_1/INT10_1/TRACED4

P09/SOT14_0/TIOB13_0/INT18_0/MDQM1_0 22 111 P1D/AN13/SCK12_0/TIOB5_2/TRACED3

P0A/ADTG_1/SCK14_0/AIN2_1/MCLKOUT_0 23 110 P1C/AN12/SOT12_0/TIOA5_2/TRACED2

P30/RX0_1/TIOA13_2/INT03_2/MDQM2_0/I2SDI_0 24 109 P1B/AN11/SIN12_0/TIOB4_2/INT11_0/TRACED1

P31/TX0_1/TIOB13_2/MDQM3_0/I2SCK_0 25 108 P1A/AN10/SCK2_0/TIOA4_2/TRACED0

P32/BIN2_1/INT19_0/S_DATA1_0 26 107 P19/AN09/SOT2_0/TIOB3_2/INT24_1/TRACECLK

P33/FRCK0_0/ZIN2_1/S_DATA0_0 27 106 P18/AN08/SIN2_0/TIOA3_2/INT10_0

P34/IC03_0/INT00_1/S_CLK_0 28 105 PB3/AN19/SCS62_1/TIOB10_1

VCC 29 104 PB2/AN18/SCS61_1/TIOA10_1/INT09_1

VSS 30 103 PB1/AN17/SCS60_1/TIOB9_1/INT08_1

P35/IC02_0/INT01_1/S_CMD_0 31 102 PB0/AN16/SCK6_1/TIOA9_1

P36/IC01_0/INT02_1/S_DATA3_0 32 101 P17/AN07/SCK11_0/TIOB2_2/ZIN1_2

P37/IC00_0/INT03_1/S_DATA2_0 33 100 P16/AN06/SOT11_0/TIOA2_2/BIN1_2

P38/ADTG_2/DTTI0X_0/S_WP_0 34 99 P15/AN05/SIN11_0/TIOB1_2/AIN1_2/INT09_0

P39/SIN2_1/RTO00_0/TIOA0_1/AIN3_1/INT16_1/S_CD_0/MAD24_0 35 98 P14/AN04/SOT6_1/TX1_1

P3A/SOT2_1/RTO01_0/TIOA1_1/BIN3_1/INT17_1/MAD23_0 36 97 P13/AN03/SIN6_1/RX1_1/INT25_1

P3B/SCK2_1/RTO02_0/TIOA2_1/ZIN3_1/INT18_1/MAD22_0/MNALE_0 37 96 P12/AN02/SCK10_0/TIOA1_2/ZIN0_2

P3C/SIN13_0/RTO03_0/TIOA3_1/INT19_1/MAD21_0/MNCLE_0 38 95 P11/AN01/SOT10_0/TIOB0_2/BIN0_2

P3D/SOT13_0/RTO04_0/TIOA4_1/MAD20_0/MNWEX_0 39 94 P10/AN00/SIN10_0/TIOA0_2/AIN0_2/INT08_0

P3E/SCK13_0/RTO05_0/TIOA5_1/MAD19_0/MNREX_0 40 93 AVRH

P5D/SIN10_1/TIOB11_2/INT01_2/MADATA29_0/I2SMCLK_0 41 92 AVRL

P5E/SOT10_1/TIOA12_2/MADATA30_0/I2SDO_0 42 91 AVSS

P5F/SCK10_1/TIOB12_2/MADATA31_0/I2SWS_0 43 90 AVCC

VSS 44 89 VCC

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

VC

C

P40/S

IN3_1/R

TO

10_0/T

IOA

0_0/A

IN0_0/IN

T23_0/M

CS

X7_0

P41/S

OT

3_1/R

TO

11_0/T

IOA

1_0/B

IN0_0/M

CS

X6_0

P42/S

CK

3_1/R

TO

12_0/T

IOA

2_0/Z

IN0_0/M

CS

X5_0

P43/S

IN15_0/R

TO

13_0/T

IOA

3_0/IN

T04_0/M

CS

X4_0

P44/S

OT

15_0/R

TO

14_0/T

IOA

4_0/M

CS

X3_0

P45/S

CK

15_0/R

TO

15_0/T

IOA

5_0/M

CS

X2_0 C

VS

S

VC

C

P7D

/SC

K1_1/R

X2_0/D

TT

I1X

_0/IN

T05_0/W

KU

P2/M

CS

X1_0

P7E

/AD

TG

_7/T

X2_0/F

RC

K1_0/M

CS

X0_0

INIT

X

P46/X

0A

P47/X

1A

VB

AT

P48/V

RE

GC

TL

P49/V

WA

KE

UP

PF

0/S

CS

63_0/R

X2_1/F

RC

K1_1/T

IOA

15_1/IN

T22_1

PF

1/S

CS

62_0/T

X2_1/T

IOB

15_1/IN

T23_1

P70/A

DT

G_8/S

IN1_1/IN

T06_0/M

RD

Y_0/C

EC

0_0

P71/S

OT

1_1/M

AD

00_0

P72/S

IN9_0/T

IOB

0_0/IN

T07_0/M

AD

01_0

P73/S

OT

9_0/T

IOB

1_0/M

AD

02_0

P74/S

CK

9_0/T

IOB

2_0/M

AD

03_0

PF

2/R

TO

10_1/T

IOA

6_1/M

RA

SX

_0

PF

3/R

TO

11_1/T

IOB

6_1/IN

T05_1/M

CA

SX

_0

PF

4/R

TO

12_1/T

IOA

7_1/IN

T06_1/M

SD

WE

X_0

PF

5/R

TO

13_1/T

IOB

7_1/IN

T07_1/M

CS

X8_0

PF

6/R

TO

14_1/T

IOA

14_1/IN

T20_1/M

SD

CK

E_0

PF

7/R

TO

15_1/T

IOB

14_1/IN

T21_1/M

SD

CL

K_0

P75/S

IN8_0/T

IOB

3_0/A

IN1_0/IN

T20_0/M

AD

04_0

P76/S

OT

8_0/T

IOB

4_0/B

IN1_0/M

AD

05_0

P77/S

CK

8_0/T

IOB

5_0/Z

IN1_0/M

AD

06_0

P78/S

IN6_0/IC

10_0/IN

T21_0/M

AD

07_0

P79/S

OT

6_0/IC

11_0/M

AD

08_0

P7A

/SC

K6_0/IC

12_0/M

AD

09_0

P7B

/DA

1/S

CS

60_0/IC

13_0/IN

T22_0

P7C

/DA

0/S

CS

61_0/IN

T04_1

PE

0/M

D1

MD

0

PE

2/X

0

PE

3/X

1

VS

S

LQFP - 176



FPT-216P-M01

Note:



same channel.


(Top View)

VS

S

P81/U

DP

0

P80/U

DM

0

US

BV

CC

0

P60/S

IN4_0/IN

T31_0/W

KU

P3/C

EC

1_0

P61/U

HC

ON

X0/S

OT

4_0/M

AL

E_0/R

TC

CO

_0/S

UB

OU

T_0

P62/S

CK

4_0/M

WE

X_0

P63/A

DT

G_3/R

TS

4_0/IN

T30_0/M

OE

X_0

P64/C

TS

4_0/R

TO

25_1/IN

T29_1

P65/R

TO

24_1/IN

T28_1

P66/S

IN13_1/R

TO

23_1/T

IOA

15_2/IN

T15_2

P67/S

OT

13_1/R

TO

22_1/T

IOB

15_2

P68/S

CK

13_1/R

TO

21_1/T

IOA

14_2

P69/R

TO

20_1/T

IOB

14_2

P6A

/DT

TI2

X_1/T

IOA

7_2

P6B

/SIN

14_1/IC

20_1/T

IOB

7_2/IN

T14_2

P6C

/SO

T14_1/IC

21_1/T

IOA

6_2

P6D

/SC

K14_1/IC

22_1/T

IOB

6_2

P6E

/AD

TG

_5/S

CK

4_1/IC

23_1/IN

T29_0/E

_P

PS

PD

2/C

TS

4_1/F

RC

K2_1/E

_T

XE

N

PD

1/IN

T31_1/E

_T

X00

PD

0/IN

T30_1/E

_T

X01

PC

F/R

TS

4_1/IN

T12_0/E

_T

X02

PC

E/S

IN4_1/IN

T15_0/E

_T

X03

PC

D/S

OT

4_1/IN

T14_0/E

_T

XE

R

PC

C/E

_T

CK

PC

B/IN

T28_0/E

_C

OU

T

VS

S

ET

HV

CC

PC

A/T

IOA

15_0/E

_C

RS

PC

9/T

IOB

15_0/E

_C

OL

PC

8/E

_R

XC

K_R

EF

CK

PC

7/IN

T13_0/E

_M

DC

/CR

OU

T_1

PC

6/T

IOA

14_0/E

_M

DIO

PC

5/T

IOB

14_0/E

_R

XD

V

PC

4/T

IOA

7_0/E

_R

X00

PC

3/T

IOB

7_0/E

_R

X01

PC

2/T

IOA

6_0/E

_R

X02

PC

1/T

IOB

6_0/E

_R

X03

PC

0/E

_R

XE

R

P97/T

X0_2/IN

T13_2/Q

_C

S2_0

P96/R

X0_2/IN

T12_2/Q

_C

S1_0

P95/R

TS

5_1/Q

_C

S0_0

P94/C

TS

5_1/Q

_S

CK

_0

P93/S

CK

5_1/IN

T15_1/Q

_IO

0_0

P92/S

OT

5_1/IN

T14_1/Q

_IO

1_0

P91/S

IN5_1/IN

T13_1/Q

_IO

2_0

P90/IN

T12_1/Q

_IO

3_0

P04/T

DO

/SW

O

P03/T

MS

/SW

DIO

P02/T

DI

P01/T

CK

/SW

CL

K

P00/T

RS

TX

VC

C

216

215

214

213

212

211

210

209

208

207

206

205

204

203

202

201

200

199

198

197

196

195

194

193

192

191

190

189

188

187

186

185

184

183

182

181

180

179

178

177

176

175

174

173

172

171

170

169

168

167

166

165

164

163

VCC 1 162 VSS









P50/SCS72_0/RTO00_1/TIOA8_2/MADATA16_0 10 153 P25/AN28/RX1_0/INT25_0/MAD17_0

P51/SCS73_0/RTO01_1/TIOB8_2/MADATA17_0 11 152 P26/TX1_0/MAD16_0

P52/RTO02_1/TIOA9_2/MADATA18_0 12 151 PBF/SIN0_1/ZIN3_2/INT11_2/TRACED15

P53/RTO03_1/TIOB9_2/MADATA19_0 13 150 PBE/SOT0_1/BIN3_2/TRACED14

PA8/SIN7_0/IC21_0/INT02_0/WKUP1/MADATA08_0 14 149 PBD/SCK0_1/RX1_2/AIN3_2/INT10_2/TRACED13

PA9/SOT7_0/IC22_0/MADATA09_0 15 148 PBC/TX1_2/TRACED12

PAA/SCK7_0/IC23_0/MADATA10_0 16 147 P27/AN27/SIN5_0/INT24_0/MAD15_0

PAB/SCS70_0/RX0_0/FRCK2_0/INT03_0/MADATA11_0 17 146 P28/AN26/SOT5_0/MAD14_0

PAC/SCS71_0/TX0_0/TIOB8_0/AIN3_0/MADATA12_0 18 145 P29/AN25/SCK5_0/MAD13_0

P54/SIN15_1/RTO04_1/TIOA10_2/INT00_2/MADATA20_0 19 144 P2A/AN24/CTS5_0/MAD12_0

P55/SOT15_1/RTO05_1/TIOB10_2/MADATA21_0 20 143 P1F/AN15/RTS5_0/TIOB8_1/INT27_1/MAD11_0

P56/SCK15_1/DTTI0X_1/TIOB0_1/MADATA22_0 21 142 P1E/AN14/TIOA8_1/INT26_1/MAD10_0

P57/IC00_1/TIOB1_1/MADATA23_0 22 141 PB7/AN23/TIOB12_1/TRACED7

PAD/SCK3_0/TIOB9_0/BIN3_0/MADATA13_0 23 140 PB6/AN22/SCK8_1/TIOA12_1/TRACED6

PAE/ADTG_0/SOT3_0/TIOB10_0/ZIN3_0/MADATA14_0 24 139 PB5/AN21/SOT8_1/TIOB11_1/INT11_1/TRACED5

PAF/SIN3_0/TIOB11_0/INT16_0/MADATA15_0 25 138 PB4/AN20/SIN8_1/TIOA11_1/INT10_1/TRACED4

P58/SIN11_1/IC01_1/TIOB2_1/INT02_2/MADATA24_0 26 137 VCC

P59/SOT11_1/IC02_1/TIOB3_1/MADATA25_0 27 136 VSS

P5A/SCK11_1/IC03_1/TIOB4_1/MADATA26_0 28 135 P1D/AN13/SCK12_0/TIOB5_2/TRACED3

P5B/FRCK0_1/TIOB5_1/MADATA27_0 29 134 P1C/AN12/SOT12_0/TIOA5_2/TRACED2

P08/SIN14_0/TIOB12_0/INT17_0/MDQM0_0 30 133 P1B/AN11/SIN12_0/TIOB4_2/INT11_0/TRACED1

P09/SOT14_0/TIOB13_0/INT18_0/MDQM1_0 31 132 P1A/AN10/SCK2_0/TIOA4_2/TRACED0

P0A/ADTG_1/SCK14_0/AIN2_1/MCLKOUT_0 32 131 P19/AN09/SOT2_0/TIOB3_2/INT24_1/TRACECLK

P5C/TIOA11_2/MADATA28_0/RTCCO_1/SUBOUT_1 33 130 P18/AN08/SIN2_0/TIOA3_2/INT10_0

P30/RX0_1/TIOA13_2/INT03_2/MDQM2_0/I2SDI_0 34 129 PB3/AN19/SCS62_1/TIOB10_1

P31/TX0_1/TIOB13_2/MDQM3_0/I2SCK_0 35 128 PB2/AN18/SCS61_1/TIOA10_1/INT09_1

P32/BIN2_1/INT19_0/S_DATA1_0 36 127 PB1/AN17/SCS60_1/TIOB9_1/INT08_1

P33/FRCK0_0/ZIN2_1/S_DATA0_0 37 126 PB0/AN16/SCK6_1/TIOA9_1

P34/IC03_0/INT00_1/S_CLK_0 38 125 P17/AN07/SCK11_0/TIOB2_2/ZIN1_2

VCC 39 124 P16/AN06/SOT11_0/TIOA2_2/BIN1_2

VSS 40 123 P15/AN05/SIN11_0/TIOB1_2/AIN1_2/INT09_0

P35/IC02_0/INT01_1/S_CMD_0 41 122 PBB/SCK9_1/ZIN2_2/TRACED11

P36/IC01_0/INT02_1/S_DATA3_0 42 121 PBA/SOT9_1/BIN2_2/TRACED10

P37/IC00_0/INT03_1/S_DATA2_0 43 120 PB9/SIN9_1/AIN2_2/INT09_2/TRACED9

P38/ADTG_2/DTTI0X_0/S_WP_0 44 119 PB8/ADTG_6/SCS63_1/INT08_2/TRACED8

P39/SIN2_1/RTO00_0/TIOA0_1/AIN3_1/INT16_1/S_CD_0/MAD24_0 45 118 P14/AN04/SOT6_1/TX1_1

P3A/SOT2_1/RTO01_0/TIOA1_1/BIN3_1/INT17_1/MAD23_0 46 117 P13/AN03/SIN6_1/RX1_1/INT25_1

P3B/SCK2_1/RTO02_0/TIOA2_1/ZIN3_1/INT18_1/MAD22_0/MNALE_0 47 116 P12/AN02/SCK10_0/TIOA1_2/ZIN0_2

P3C/SIN13_0/RTO03_0/TIOA3_1/INT19_1/MAD21_0/MNCLE_0 48 115 P11/AN01/SOT10_0/TIOB0_2/BIN0_2

P3D/SOT13_0/RTO04_0/TIOA4_1/MAD20_0/MNWEX_0 49 114 P10/AN00/SIN10_0/TIOA0_2/AIN0_2/INT08_0

P3E/SCK13_0/RTO05_0/TIOA5_1/MAD19_0/MNREX_0 50 113 AVRH

P5D/SIN10_1/TIOB11_2/INT01_2/MADATA29_0/I2SMCLK_0 51 112 AVRL

P5E/SOT10_1/TIOA12_2/MADATA30_0/I2SDO_0 52 111 AVSS

P5F/SCK10_1/TIOB12_2/MADATA31_0/I2SWS_0 53 110 AVCC

VSS 54 109 VCC

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

101

102

103

104

105

106

107

108

VC

C

P40/S

IN3_1/R

TO

10_0/T

IOA

0_0/A

IN0_0/IN

T23_0/M

CS

X7_0

P41/S

OT

3_1/R

TO

11_0/T

IOA

1_0/B

IN0_0/M

CS

X6_0

P42/S

CK

3_1/R

TO

12_0/T

IOA

2_0/Z

IN0_0/M

CS

X5_0

P43/S

IN15_0/R

TO

13_0/T

IOA

3_0/IN

T04_0/M

CS

X4_0

P44/S

OT

15_0/R

TO

14_0/T

IOA

4_0/M

CS

X3_0

P45/S

CK

15_0/R

TO

15_0/T

IOA

5_0/M

CS

X2_0 C

VS

S

VC

C

P4A

/SIN

12_1/A

IN0_1/IN

T04_2

P4B

/SO

T12_1/B

IN0_1

P4C

/SC

K12_1/Z

IN0_1

P4D

/SC

S72_1/R

X2_2/IN

T05_2

P4E

/SC

S73_1/T

X2_2

P7D

/SC

K1_1/R

X2_0/D

TT

I1X

_0/IN

T05_0/W

KU

P2/M

CS

X1_0

P7E

/AD

TG

_7/T

X2_0/F

RC

K1_0/M

CS

X0_0

INIT

X

P46/X

0A

P47/X

1A

VB

AT

P48/V

RE

GC

TL

P49/V

WA

KE

UP

PF

0/S

CS

63_0/R

X2_1/F

RC

K1_1/T

IOA

15_1/IN

T22_1

PF

1/S

CS

62_0/T

X2_1/T

IOB

15_1/IN

T23_1

P70/A

DT

G_8/S

IN1_1/IN

T06_0/M

RD

Y_0/C

EC

0_0

P71/S

OT

1_1/M

AD

00_0

P72/S

IN9_0/T

IOB

0_0/IN

T07_0/M

AD

01_0

P73/S

OT

9_0/T

IOB

1_0/M

AD

02_0

P74/S

CK

9_0/T

IOB

2_0/M

AD

03_0

PF

2/R

TO

10_1/T

IOA

6_1/M

RA

SX

_0

PF

3/R

TO

11_1/T

IOB

6_1/IN

T05_1/M

CA

SX

_0

PF

4/R

TO

12_1/T

IOA

7_1/IN

T06_1/M

SD

WE

X_0

PF

5/R

TO

13_1/T

IOB

7_1/IN

T07_1/M

CS

X8_0

PF

6/R

TO

14_1/T

IOA

14_1/IN

T20_1/M

SD

CK

E_0

PF

7/R

TO

15_1/T

IOB

14_1/IN

T21_1/M

SD

CL

K_0

P75/S

IN8_0/T

IOB

3_0/A

IN1_0/IN

T20_0/M

AD

04_0

P76/S

OT

8_0/T

IOB

4_0/B

IN1_0/M

AD

05_0

P77/S

CK

8_0/T

IOB

5_0/Z

IN1_0/M

AD

06_0

PF

8/S

CS

70_1/D

TT

I1X

_1/A

IN1_1

PF

9/S

CS

71_1/IC

10_1/B

IN1_1

P78/S

IN6_0/IC

10_0/IN

T21_0/M

AD

07_0

P79/S

OT

6_0/IC

11_0/M

AD

08_0

P7A

/SC

K6_0/IC

12_0/M

AD

09_0

P7B

/DA

1/S

CS

60_0/IC

13_0/IN

T22_0

P7C

/DA

0/S

CS

61_0/IN

T04_1

PF

A/S

CK

7_1/IC

11_1/Z

IN1_1

PF

B/S

OT

7_1/IC

12_1/IN

T07_2

PF

C/S

IN7_1/IC

13_1/IN

T06_2

PE

0/M

D1

MD

0

PE

2/X

0

PE

3/X

1

VS

S

LQFP - 216



LBE192

Note:



same channel.


(Top View)

1 2 3 4 5 6 7 8 9 10 11 12 13 14

A UDP0 UDM0USBV

CC0VSS PCD PCB VSS

ETHV

CCPC8 VSS TCK VCC

B VSS PA0 P60 P62 P64 PD1 PCA PC1 P95 P92 TDO TMS TRSTX VSS

C VCC PA1 PA2 P61 P63 PD2 PCC PC5 PC0 P93 P90 TDI P20 UDP1

D PA5 PA4 PA6 PA7 PA3 P6E PCE PC6 PC2 P94 P91 P22 P21 UDM1

E VSS P50 P51 P52 PA8 P65 PCF PC7 PC3 P26 P25 P24 P23USBV

CC1

F PA9 PAA PAB PAC PAD PAE PD0 PC9 PC4 P2A P29 P28 P27 PB5

G VSS PAF P08 P09 P0A P30 VSS VSS P1F P1E PB7 PB6 PB4 P1B

H VCC P32 P34 P31 VSS P35 VSS VSS P18 PB2 P1D P19 P1C P1A

J P33 P39 P38 P37 P36 P71 VSS P74 PB1 PB0 P17 P16 P15 PB3

K P3A P3B P3C P3D PF0 PF1 VSS P73 P75 P79 P14 P12 P11 P13

L P3E P5D P5E P43 P7D P70 VSS P72 PF7 P78 P10 AVRH AVRL VSS

M VSS P5F P42 P44 P7E P49 VSS PF3 PF6 P7A P7C AVSS AVCC VCC

N VCC P40 P41 P45 INITX P48 VSS PF2 PF4 P77 P7B MD0 MD1 VSS

P C VSS VCC X0A X1A VSS VBAT PF5 P76 VSS X0 X1

PFBGA-192



6. Pin Descriptions

List of Pin Functions

The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port

number. For these pins, there are multiple pins that provide the same function for the same channel.


Pin Number

Pin Name

I/O

Circuit

Type

Pin State

Type LQFP-216 LQFP-176 LQFP-144 LBE192

1 1 1 C1 VCC - -

2 2 2 B2

PA0

G K

RTO20_0

(PPG20_0)

TIOA8_0

AIN2_0

INT00_0

MADATA00_0

3 3 3 C2

PA1

G I

RTO21_0

(PPG20_0)

TIOA9_0

BIN2_0

MADATA01_0

4 4 4 C3

PA2

G I

RTO22_0

(PPG22_0)

TIOA10_0

ZIN2_0

MADATA02_0

5 5 5 D5

PA3

G I

RTO23_0

(PPG22_0)

TIOA11_0

MADATA03_0

6 6 6 D2

PA4

G I

RTO24_0

(PPG24_0)

TIOA12_0

MADATA04_0

7 7 7 D1

PA5

G K

SIN1_0

RTO25_0

(PPG24_0)

TIOA13_0

INT01_0

MADATA05_0



Pin Number

Pin Name

I/O

Circuit

Type

Pin State


8 8 8 D3

PA6

E I

SOT1_0

(SDA1_0))

DTTI2X_0

MADATA06_0

9 9 9 D4

PA7

E I

SCK1_0

(SCL1_0)

IC20_0

MADATA07_0

10 10 - E2

P50

E I

SCS72_0

RTO00_1

(PPG00_1)

TIOA8_2

MADATA16_0

11 11 - E3

P51

E I

SCS73_0

RTO01_1

(PPG00_1)

TIOB8_2

MADATA17_0

12 12 - E4

P52

E I

RTO02_1

(PPG02_1)

TIOA9_2

MADATA18_0

13 - - -

P53

E I

RTO03_1

(PPG02_1)

TIOB9_2

MADATA19_0

14 13 10 E5

PA8

I Q

SIN7_0

IC21_0

INT02_0

WKUP1

MADATA08_0

15 14 11 F1

PA9

N I

SOT7_0

(SDA7_0)

IC22_0

MADATA09_0

16 15 12 F2

PAA

N I

SCK7_0

(SCL7_0)

IC23_0

MADATA10_0



Pin Number

Pin Name

I/O

Circuit

Type

Pin State


17 16 13 F3

PAB

E K

SCS70_0

RX0_0

FRCK2_0

INT03_0

MADATA11_0

18 17 14 F4

PAC

E I

SCS71_0

TX0_0

TIOB8_0

AIN3_0

MADATA12_0

19 - - -

P54

E K

SIN15_1

RTO04_1

(PPG04_1)

TIOA10_2

INT00_2

MADATA20_0

20 - - -

P55

E I

SOT15_1

(SDA15_1)

RTO05_1

(PPG04_1)

TIOB10_2

MADATA21_0

21 - - -

P56

E I

SCK15_1

(SCL15_1)

DTTI0X_1

TIOB0_1

MADATA22_0

22 - - -

P57

E I IC00_1

TIOB1_1

MADATA23_0

23 18 15 F5

PAD

N I

SCK3_0

(SCL3_0)

TIOB9_0

BIN3_0

MADATA13_0



Pin Number

Pin Name

I/O

Circuit

Type

Pin State


24 19 16 F6

PAE

N I

ADTG_0

SOT3_0

(SDA3_0)

TIOB10_0

ZIN3_0

MADATA14_0

25 20 17 G2

PAF

I K

SIN3_0

TIOB11_0

INT16_0

MADATA15_0

26 - - -

P58

E K

SIN11_1

IC01_1

TIOB2_1

INT02_2

MADATA24_0

27 - - -

P59

E I

SOT11_1

(SDA11_1)

IC02_1

TIOB3_1

MADATA25_0

28 - - -

P5A

E I

SCK11_1

(SCL11_1)

IC03_1

TIOB4_1

MADATA26_0

29 - - -

P5B

E I FRCK0_1

TIOB5_1

MADATA27_0

30 21 18 G3

P08

E K

SIN14_0

TIOB12_0

INT17_0

MDQM0_0

31 22 19 G4

P09

E K

SOT14_0

(SDA14_0)

TIOB13_0

INT18_0

MDQM1_0



Pin Number

Pin Name

I/O

Circuit

Type

Pin State


32 23 20 G5

P0A

L I

ADTG_1

SCK14_0

(SCL14_0)

AIN2_1

MCLKOUT_0

33 - - -

P5C

E I

TIOA11_2

MADATA28_0

RTCCO_1

SUBOUT_1

34 24 - G6

P30

E K

RX0_1

TIOA13_2

INT03_2

MDQM2_0

I2SDI_0

35 25 - H4

P31

E I

TX0_1

TIOB13_2

MDQM3_0

I2SCK_0

36 26 21 H2

P32

L K BIN2_1

INT19_0

S_DATA1_0

37 27 22 J1

P33

L I FRCK0_0

ZIN2_1

S_DATA0_0

38 28 23 H3

P34

L K IC03_0

INT00_1

S_CLK_0

39 29 24 H1 VCC - -

40 30 25 H5 VSS - -

41 31 26 H6

P35

L K IC02_0

INT01_1

S_CMD_0

42 32 27 J5

P36

L K IC01_0

INT02_1

S_DATA3_0

43 33 28 J4

P37

L K IC00_0

INT03_1

S_DATA2_0



Pin Number

Pin Name

I/O

Circuit

Type

Pin State


44 34 29 J3

P38

E I ADTG_2

DTTI0X_0

S_WP_0

45 35 30 J2

P39

G K

SIN2_1

RTO00_0

(PPG00_0)

TIOA0_1

AIN3_1

INT16_1

S_CD_0

MAD24_0

46 36 31 K1

P3A

G K

SOT2_1

(SDA2_1)

RTO01_0

(PPG00_0)

TIOA1_1

BIN3_1

INT17_1

MAD23_0

47 37 32 K2

P3B

G K

SCK2_1

(SCL2_1)

RTO02_0

(PPG02_0)

TIOA2_1

ZIN3_1

INT18_1

MAD22_0

MNALE_0

48 38 33 K3

P3C

G K

SIN13_0

RTO03_0

(PPG02_0)

TIOA3_1

INT19_1

MAD21_0

MNCLE_0

49 39 34 K4

P3D

G I

SOT13_0

(SDA13_0)

RTO04_0

(PPG04_0)

TIOA4_1

MAD20_0

MNWEX_0



Pin Number

Pin Name

I/O

Circuit

Type

Pin State


50 40 35 L1

P3E

G I

SCK13_0

(SCL13_0)

RTO05_0

(PPG04_0)

TIOA5_1

MAD19_0

MNREX_0

51 41 - L2

P5D

E K

SIN10_1

TIOB11_2

INT01_2

MADATA29_0

I2SMCLK_0

52 42 - L3

P5E

E I

SOT10_1

(SDA10_1)

TIOA12_2

MADATA30_0

I2SDO_0

53 43 - M2

P5F

E I

SCK10_1

(SCL10_1)

TIOB12_2

MADATA31_0

I2SWS_0

54 44 36 M1 VSS - -

55 45 37 N1 VCC - -

56 46 38 N2

P40

G K

SIN3_1

RTO10_0

(PPG10_0)

TIOA0_0

AIN0_0

INT23_0

MCSX7_0

57 47 39 N3

P41

G I

SOT3_1

(SDA3_1)

RTO11_0

(PPG10_0)

TIOA1_0

BIN0_0

MCSX6_0



Pin Number

Pin Name

I/O

Circuit

Type

Pin State


58 48 40 M3

P42

G I

SCK3_1

(SCL3_1)

RTO12_0

(PPG12_0)

TIOA2_0

ZIN0_0

MCSX5_0

59 49 41 L4

P43

G K

SIN15_0

RTO13_0

(PPG12_0)

TIOA3_0

INT04_0

MCSX4_0

60 50 42 M4

P44

G I

SOT15_0

(SDA15_0)

RTO14_0

(PPG14_0)

TIOA4_0

MCSX3_0

61 51 43 N4

P45

G I

SCK15_0

(SCL15_0)

RTO15_0

(PPG14_0)

TIOA5_0

MCSX2_0

62 52 44 P2 C - -

63 53 45 P3 VSS - -

64 54 46 P4 VCC - -

65 - - -

P4A

E K SIN12_1

AIN0_1

INT04_2

66 - - -

P4B

E I SOT12_1

(SDA12_1)

BIN0_1

67 - - -

P4C

E I SCK12_1

(SCL12_1)

ZIN0_1

68 - - -

P4D

E K SCS72_1

RX2_2

INT05_2



Pin Number

Pin Name

I/O

Circuit

Type

Pin State


69 - - -

P4E

E I SCS73_1

TX2_2

70 55 47 L5

P7D

L Q

SCK1_1

(SCL1_1)

RX2_0

DTTI1X_0

INT05_0

WKUP2

MCSX1_0

71 56 48 M5

P7E

L I

ADTG_7

TX2_0

FRCK1_0

MCSX0_0

72 57 49 N5 INITX B C

73 58 50 P5 P46

P S X0A

74 59 51 P6 P47

Q T X1A

75 60 52 P8 VBAT - -

76 61 53 N6 P48

O U VREGCTL

77 62 54 M6 P49

O U VWAKEUP

78 63 - K5

PF0

E K

SCS63_0

RX2_1

FRCK1_1

TIOA15_1

INT22_1

79 64 - K6

PF1

E K

SCS62_0

TX2_1

TIOB15_1

INT23_1

80 65 55 L6

P70

I X

ADTG_8

SIN1_1

INT06_0

MRDY_0

CEC0_0

81 66 56 J6

P71

E I SOT1_1

(SDA1_1)

MAD00_0



Pin Number

Pin Name

I/O

Circuit

Type

Pin State


82 67 57 L8

P72

E K

SIN9_0

TIOB0_0

INT07_0

MAD01_0

83 68 58 K8

P73

E I

SOT9_0

(SDA9_0)

TIOB1_0

MAD02_0

84 69 59 J8

P74

E I

SCK9_0

(SCL9_0)

TIOB2_0

MAD03_0

85 70 - N8

PF2

L I

RTO10_1

(PPG10_1)

TIOA6_1

MRASX_0

86 71 - M8

PF3

L K

RTO11_1

(PPG10_1)

TIOB6_1

INT05_1

MCASX_0

87 72 - N9

PF4

L K

RTO12_1

(PPG12_1)

TIOA7_1

INT06_1

MSDWEX_0

88 73 - P9

PF5

L K

RTO13_1

(PPG12_1)

TIOB7_1

INT07_1

MCSX8_0

89 74 - M9

PF6

L K

RTO14_1

(PPG14_1)

TIOA14_1

INT20_1

MSDCKE_0



Pin Number

Pin Name

I/O

Circuit

Type

Pin State


90 75 - L9

PF7

L K

RTO15_1

(PPG14_1)

TIOB14_1

INT21_1

MSDCLK_0

91 76 60 K9

P75

E K

SIN8_0

TIOB3_0

AIN1_0

INT20_0

MAD04_0

92 77 61 P10

P76

E I

SOT8_0

(SDA8_0)

TIOB4_0

BIN1_0

MAD05_0

93 78 62 N10

P77

E I

SCK8_0

(SCL8_0)

TIOB5_0

ZIN1_0

MAD06_0

94 - - -

PF8

E I SCS70_1

DTTI1X_1

AIN1_1

95 - - -

PF9

E I SCS71_1

IC10_1

BIN1_1

96 79 63 L10

P78

E K

SIN6_0

IC10_0

INT21_0

MAD07_0

97 80 64 K10

P79

L I

SOT6_0

(SDA6_0)

IC11_0

MAD08_0

98 81 65 M10

P7A

L I

SCK6_0

(SCL6_0)

IC12_0

MAD09_0



Pin Number

Pin Name

I/O

Circuit

Type

Pin State


99 82 66 N11

P7B

R J

DA1

SCS60_0

IC13_0

INT22_0

100 83 67 M11

P7C

R J DA0

SCS61_0

INT04_1

101 - - -

PFA

E I

SCK7_1

(SCL7_1)

IC11_1

ZIN1_1

102 - - -

PFB

E K

SOT7_1

(SDA7_1)

IC12_1

INT07_2

103 - - -

PFC

E K SIN7_1

IC13_1

INT06_2

104 84 68 N13 PE0

C E MD1

105 85 69 N12 MD0 J D

106 86 70 P12 PE2

A A X0

107 87 71 P13 PE3

A B X1

108 88 72 N14 VSS - -

109 89 73 M14 VCC - -

110 90 74 M13 AVCC - -

111 91 75 M12 AVSS - -

112 92 76 L13 AVRL - -

113 93 77 L12 AVRH - -

114 94 78 L11

P10

F M

AN00

SIN10_0

TIOA0_2

AIN0_2

INT08_0



Pin Number

Pin Name

I/O

Circuit

Type

Pin State


115 95 79 K13

P11

F L

AN01

SOT10_0

(SDA10_0)

TIOB0_2

BIN0_2

116 96 80 K12

P12

F L

AN02

SCK10_0

(SCL10_0)

TIOA1_2

ZIN0_2

117 97 81 K14

P13

F M

AN03

SIN6_1

RX1_1

INT25_1

118 98 82 K11

P14

F L

AN04

SOT6_1

(SDA6_1)

TX1_1

119 - - -

PB8

E O

ADTG_6

SCS63_1

INT08_2

TRACED8

120 - - -

PB9

E O

SIN9_1

AIN2_2

INT09_2

TRACED9

121 - - -

PBA

E N

SOT9_1

(SDA9_1)

BIN2_2

TRACED10

122 - - -

PBB

E N

SCK9_1

(SCL9_1)

ZIN2_2

TRACED11

123 99 83 J13

P15

F M

AN05

SIN11_0

TIOB1_2

AIN1_2

INT09_0



Pin Number

Pin Name

I/O

Circuit

Type

Pin State


124 100 84 J12

P16

F L

AN06

SOT11_0

(SDA11_0)

TIOA2_2

BIN1_2

125 101 85 J11

P17

F L

AN07

SCK11_0

(SCL11_0)

TIOB2_2

ZIN1_2

126 102 - J10

PB0

F L

AN16

SCK6_1

(SCL6_1)

TIOA9_1

127 103 - J9

PB1

F M

AN17

SCS60_1

TIOB9_1

INT08_1

128 104 - H10

PB2

F M

AN18

SCS61_1

TIOA10_1

INT09_1

129 105 - J14

PB3

F L AN19

SCS62_1

TIOB10_1

130 106 86 H9

P18

F M

AN08

SIN2_0

TIOA3_2

INT10_0

131 107 87 H12

P19

F O

AN09

SOT2_0

(SDA2_0)

TIOB3_2

INT24_1

TRACECLK



Pin Number

Pin Name

I/O

Circuit

Type

Pin State


132 108 88 H14

P1A

F N

AN10

SCK2_0

(SCL2_0)

TIOA4_2

TRACED0

133 109 89 G14

P1B

F O

AN11

SIN12_0

TIOB4_2

INT11_0

TRACED1

134 110 90 H13

P1C

F N

AN12

SOT12_0

(SDA12_0)

TIOA5_2

TRACED2

135 111 91 H11

P1D

F N

AN13

SCK12_0

(SCL12_0)

TIOB5_2

TRACED3

136 - - - VSS - -

137 - - - VCC - -

138 112 - G13

PB4

F O

AN20

SIN8_1

TIOA11_1

INT10_1

TRACED4

139 113 - F14

PB5

F O

AN21

SOT8_1

(SDA8_1)

TIOB11_1

INT11_1

TRACED5

140 114 - G12

PB6

F N

AN22

SCK8_1

(SCL8_1)

TIOA12_1

TRACED6



Pin Number

Pin Name

I/O

Circuit

Type

Pin State


141 115 - G11

PB7

F N AN23

TIOB12_1

TRACED7

142 116 92 G10

P1E

F M

AN14

TIOA8_1

INT26_1

MAD10_0

143 117 93 G9

P1F

F M

AN15

RTS5_0

TIOB8_1

INT27_1

MAD11_0

144 118 94 F10

P2A

F L AN24

CTS5_0

MAD12_0

145 119 95 F11

P29

F L

AN25

SCK5_0

(SCL5_0)

MAD13_0

146 120 96 F12

P28

F L

AN26

SOT5_0

(SDA5_0)

MAD14_0

147 121 97 F13

P27

F M

AN27

SIN5_0

INT24_0

MAD15_0

148 - - -

PBC

E N TX1_2

TRACED12

149 - - -

PBD

E O

SCK0_1

(SCL0_1)

RX1_2

AIN3_2

INT10_2

TRACED13



Pin Number

Pin Name

I/O

Circuit

Type

Pin State


150 - - -

PBE

E N

SOT0_1

(SDA0_1)

BIN3_2

TRACED14

151 - - -

PBF

E O

SIN0_1

ZIN3_2

INT11_2

TRACED15

152 122 98 E10

P26

E I TX1_0

MAD16_0

153 123 99 E11

P25

F M

AN28

RX1_0

INT25_0

MAD17_0

154 124 100 E12

P24

F L AN29

TIOA13_1

MAD18_0

155 125 101 E13

P23

F L

UHCONX1

AN30

SCK0_0

(SCL0_0)

TIOB13_1

156 126 102 D12

P22

F M

AN31

SOT0_0

(SDA0_0)

INT26_0

157 127 103 D13

P21

I K

ADTG_4

SIN0_0

INT27_0

CROUT_0

158 128 104 C13

P20

I F NMIX

WKUP0

159 129 105 E14 USBVCC1 - -

160 130 106 D14 P82

H R UDM1

161 131 107 C14 P83

H R UDP1

162 132 108 B14 VSS - -

163 133 109 A13 VCC - -



Pin Number

Pin Name

I/O

Circuit

Type

Pin State


164 134 110 B13 P00

E G TRSTX

165 135 111 A12

P01

E G TCK

SWCLK

166 136 112 C12 P02

E G TDI

167 137 113 B12

P03

E G TMS

SWDIO

168 138 114 B11

P04

E G TDO

SWO

169 139 - C11

P90

S K INT12_1

Q_IO3_0

170 140 - D11

P91

S K SIN5_1

INT13_1

Q_IO2_0

171 141 - B10

P92

S K

SOT5_1

(SDA5_1)

INT14_1

Q_IO1_0

172 142 - C10

P93

S K

SCK5_1

(SCL5_1)

INT15_1

Q_IO0_0

173 143 - D10

P94

S I CTS5_1

Q_SCK_0

174 144 - B9

P95

S I RTS5_1

Q_CS0_0

175 - - -

P96

S K RX0_2

INT12_2

Q_CS1_0

176 - - -

P97

S K TX0_2

INT13_2

Q_CS2_0

177 145 115 C9 PC0

K V E_RXER



Pin Number

Pin Name

I/O

Circuit

Type

Pin State


178 146 116 B8

PC1

K V TIOB6_0

E_RX03

179 147 117 D9

PC2

K V TIOA6_0

E_RX02

180 148 118 E9

PC3

K V TIOB7_0

E_RX01

181 149 119 F9

PC4

K V TIOA7_0

E_RX00

182 150 120 C8

PC5

K V TIOB14_0

E_RXDV

183 151 121 D8

PC6

K V TIOA14_0

E_MDIO

184 152 122 E8

PC7

E W INT13_0

E_MDC

CROUT_1

185 153 123 A10 PC8

K V E_RXCK_REFCK

186 154 124 F8

PC9

K V TIOB15_0

E_COL

187 155 125 B7

PCA

K V TIOA15_0

E_CRS

188 156 126 A9 ETHVCC - -

189 157 127 A8 VSS - -

190 158 128 A7

PCB

L W INT28_0

E_COUT

191 159 129 C7 PCC

K V E_TCK

192 160 130 A6

PCD

L W

SOT4_1

(SDA4_1)

INT14_0

E_TXER

193 161 131 D7

PCE

L W SIN4_1

INT15_0

E_TX03



Pin Number

Pin Name

I/O

Circuit

Type

Pin State


194 162 132 E7

PCF

L W RTS4_1

INT12_0

E_TX02

195 163 133 F7

PD0

L W INT30_1

E_TX01

196 164 134 B6

PD1

L W INT31_1

E_TX00

197 165 135 C6

PD2

L V CTS4_1

FRCK2_1

E_TXEN

198 166 136 D6

P6E

E W

ADTG_5

SCK4_1

(SCL4_1)

IC23_1

INT29_0

E_PPS

199 - - -

P6D

E I

SCK14_1

(SCL14_1)

IC22_1

TIOB6_2

200 - - -

P6C

E I

SOT14_1

(SDA14_1)

IC21_1

TIOA6_2

201 - - -

P6B

E K

SIN14_1

IC20_1

TIOB7_2

INT14_2

202 - - -

P6A

E I DTTI2X_1

TIOA7_2

203 - - -

P69

E I RTO20_1

(PPG20_1)

TIOB14_2

204 - - -

P68

E I

SCK13_1

(SCL13_0)

RTO21_1

(PPG20_1)

TIOA14_2



Pin Number

Pin Name

I/O

Circuit

Type

Pin State


205 - - -

P67

E I

SOT13_1

(SDA13_1)

RTO22_1

(PPG22_1)

TIOB15_2

206 - - -

P66

E K

SIN13_1

RTO23_1

(PPG22_1)

TIOA15_2

INT15_2

207 167 - E6

P65

E K RTO24_1

(PPG24_1)

INT28_1

208 168 - B5

P64

I K

CTS4_0

RTO25_1

(PPG24_1)

INT29_1

209 169 137 C5

P63

L K

ADTG_3

RTS4_0

INT30_0

MOEX_0

210 170 138 B4

P62

L I SCK4_0

(SCL4_0)

MWEX_0

211 171 139 C4

P61

L I

UHCONX0

SOT4_0

(SDA4_0)

MALE_0

RTCCO_0

SUBOUT_0

212 172 140 B3

P60

I Y

SIN4_0

INT31_0

WKUP3

CEC1_0

213 173 141 A4 USBVCC0 - -

214 174 142 A3 P80

H R UDM0

215 175 143 A2 P81

H R UDP0



Pin Number

Pin Name

I/O

Circuit

Type

Pin State


216 176 144 B1

VSS

- -

E1

- - - G1 - -

- - - P7 - -

- - - P11 - -

- - - L14 - -

- - - A11 - -

- - - A5 - -

- - - N7 - -

- - - M7 - -

- - - L7 - -

- - - K7 - -

- - - J7 - -

-- - - G7 - -

- - - H7 - -

- - - H8 - -

- - - G8 - -



Signal Descriptions

The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port

number. For these pins, there are multiple pins that provide the same function for the same channel.


Module Pin Name Function

Pin Number

LQFP

216

LQFP

176

LQFP

144

LBE

192

A/D

converter

ADTG_0

A/D converter external trigger input pin

24 19 16 F6

ADTG_1 32 23 20 G5

ADTG_2 44 34 29 J3

ADTG_3 209 169 137 C5

ADTG_4 157 127 103 D13

ADTG_5 198 166 136 D6

ADTG_6 119 - - -

ADTG_7 71 56 48 M5

ADTG_8 80 65 55 L6

AN00

A/D converter analog input pin.

ANxx describes A/D converter ch xx.

114 94 78 L11

AN01 115 95 79 K13

AN02 116 96 80 K12

AN03 117 97 81 K14

AN04 118 98 82 K11

AN05 123 99 83 J13

AN06 124 100 84 J12

AN07 125 101 85 J11

AN08 130 106 86 H9

AN09 131 107 87 H12

AN10 132 108 88 H14

AN11 133 109 89 G14

AN12 134 110 90 H13

AN13 135 111 91 H11

AN14 142 116 92 G10

AN15 143 117 93 G9

AN16 126 102 - J10

AN17 127 103 - J9

AN18 128 104 - H10

AN19 129 105 - J14

AN20 138 112 - G13

AN21 139 113 - F14

AN22 140 114 - G12

AN23 141 115 - G11

AN24 144 118 94 F10

AN25 145 119 95 F11

AN26 146 120 96 F12

AN27 147 121 97 F13

AN28 153 123 99 E11

AN29 154 124 100 E12

AN30 155 125 101 E13

AN31 156 126 102 D12




Pin Number

LQFP

216

LQFP

176

LQFP

144

LBE

192

Base Timer

0

TIOA0_0

Base Timer ch 0 TIOA pin

56 46 38 N2

TIOA0_1 45 35 30 J2

TIOA0_2 114 94 78 L11

TIOB0_0

Base Timer ch 0 TIOB pin

82 67 57 L8

TIOB0_1 21 - - -

TIOB0_2 115 95 79 K13

Base Timer

1

TIOA1_0


57 47 39 N3

TIOA1_1 46 36 31 K1

TIOA1_2 116 96 80 K12

TIOB1_0


83 68 58 K8

TIOB1_1 22 - - -

TIOB1_2 123 99 83 J13

Base Timer

2

TIOA2_0


58 48 40 M3

TIOA2_1 47 37 32 K2

TIOA2_2 124 100 84 J12

TIOB2_0


84 69 59 J8

TIOB2_1 26 - - -

TIOB2_2 125 101 85 J11

Base Timer

3

TIOA3_0


59 49 41 L4

TIOA3_1 48 38 33 K3

TIOA3_2 130 106 86 H9

TIOB3_0


91 76 60 K9

TIOB3_1 27 - - -

TIOB3_2 131 107 87 H12

Base Timer

4

TIOA4_0


60 50 42 M4

TIOA4_1 49 39 34 K4

TIOA4_2 132 108 88 H14

TIOB4_0


92 77 61 P10

TIOB4_1 28 - - -

TIOB4_2 133 109 89 G14

Base Timer

5

TIOA5_0


61 51 43 N4

TIOA5_1 50 40 35 L1

TIOA5_2 134 110 90 H13

TIOB5_0


93 78 62 N10

TIOB5_1 29 - - -

TIOB5_2 135 111 91 H11

Base Timer

6

TIOA6_0


179 147 117 D9

TIOA6_1 85 70 - N8

TIOA6_2 200 - - -

TIOB6_0


178 146 116 B8

TIOB6_1 86 71 - M8

TIOB6_2 199 - - -




Pin Number

LQFP

216

LQFP

176

LQFP

144

LBE

192

Base Timer

7

TIOA7_0


181 149 119 F9

TIOA7_1 87 72 - N9

TIOA7_2 202 - - -

TIOB7_0


180 148 118 E9

TIOB7_1 88 73 - P9

TIOB7_2 201 - - -

Base Timer

8

TIOA8_0


2 2 2 B2

TIOA8_1 142 116 92 G10

TIOA8_2 10 10 - E2

TIOB8_0


18 17 14 F4

TIOB8_1 143 117 93 G9

TIOB8_2 11 11 - E3

Base Timer

9

TIOA9_0


3 3 3 C2

TIOA9_1 126 102 - J10

TIOA9_2 12 12 - E4

TIOB9_0


23 18 15 F5

TIOB9_1 127 103 - J9

TIOB9_2 13 - - -

Base Timer

10

TIOA10_0


4 4 4 C3

TIOA10_1 128 104 - H10

TIOA10_2 19 - - -

TIOB10_0


24 19 16 F6

TIOB10_1 129 105 - J14

TIOB10_2 20 - - -

Base Timer

11

TIOA11_0

Base Timer ch 11の TIOA pin

5 5 5 D5

TIOA11_1 138 112 - G13

TIOA11_2 33 - - -

TIOB11_0


25 20 17 G2

TIOB11_1 139 113 - F14

TIOB11_2 51 41 - L2

Base Timer

12

TIOA12_0


6 6 6 D2

TIOA12_1 140 114 - G12

TIOA12_2 52 42 - L3

TIOB12_0


30 21 18 G3

TIOB12_1 141 115 - G11

TIOB12_2 53 43 - M2

Base Timer

13

TIOA13_0


7 7 7 D1

TIOA13_1 154 124 100 E12

TIOA13_2 34 24 - G6

TIOB13_0


31 22 19 G4

TIOB13_1 155 125 101 E13

TIOB13_2 35 25 - H4




Pin Number

LQFP

216

LQFP

176

LQFP

144

LBE

192

Base Timer

14

TIOA14_0


183 151 121 D8

TIOA14_1 89 74 - M9

TIOA14_2 204 - - -

TIOB14_0


182 150 120 C8

TIOB14_1 90 75 - L9

TIOB14_2 203 - - -

Base Timer

15

TIOA15_0


187 155 125 B7

TIOA15_1 78 63 - K5

TIOA15_2 206 - - -

TIOB15_0

Base timer ch 15 TIOB pin

186 154 124 F8

TIOB15_1 79 64 - K6

TIOB15_2 205 - - -

CAN 0

TX0_0

CAN interface ch 0 TX output pin

18 17 14 F4

TX0_1 35 25 - H4

TX0_2 176 - - -

RX0_0

CAN interface ch 0 RX output pin

17 16 13 F3

RX0_1 34 24 - G6

RX0_2 175 - - -

CAN 1

TX1_0

CAN interface ch 1 TX output pin

152 122 98 E10

TX1_1 118 98 82 K11

TX1_2 148 - - -

RX1_0

CAN interface ch 1 RX output pin

153 123 99 E11

RX1_1 117 97 81 K14

RX1_2 149 - - -

CAN 2

(CAN-FD)

TX2_0

CAN-FD interface ch 2 TX output pin

71 56 48 M5

TX2_1 79 64 - K6

TX2_2 69 - - -

RX2_0

CAN-FD interface ch 2 RX input pin

70 55 47 L5

RX2_1 78 63 - K5

RX2_2 68 - - -




Pin Number

LQFP

216

LQFP

176

LQFP

144

LBE

192

Debugger

SWCLK Serial wire debug interface clock input

pin 165 135 111 A12

SWDIO Serial wire debug interface data input/

output pin 167 137 113 B12

SWO Serial wire viewer output pin 168 138 114 B11

TCK J-TAG test clock input pin 165 135 111 A12

TDI J-TAG test data input pin 166 136 112 C12

TDO J-TAG debug data output pin 168 138 114 B11

TMS J-TAG test mode state input/output pin 167 137 113 B12

TRACECLK Trace CLK output pin of ETM/HTM 131 107 87 H12

TRACED0

Trace data output pin of ETM/

Trace data output pin of HTM

132 108 88 H14

TRACED1 133 109 89 G14

TRACED2 134 110 90 H13

TRACED3 135 111 91 H11

TRACED4

Trace data output pin of HTM

138 112 - G13

TRACED5 139 113 - F14

TRACED6 140 114 - G12

TRACED7 141 115 - G11

TRACED8 119 - - -

TRACED9 120 - - -

TRACED10 121 - - -

TRACED11 122 - - -

TRACED12 148 - - -

TRACED13 149 - - -

TRACED14 150 - - -

TRACED15 151 - - -

TRSTX J-TAG test reset Input pin 164 134 110 B13




Pin Number

LQFP

216

LQFP

176

LQFP

144

LBE

192

External

bus

MAD00_0

External bus interface address bus

81 66 56 J6

MAD01_0 82 67 57 L8

MAD02_0 83 68 58 K8

MAD03_0 84 69 59 J8

MAD04_0 91 76 60 K9

MAD05_0 92 77 61 P10

MAD06_0 93 78 62 N10

MAD07_0 96 79 63 L10

MAD08_0 97 80 64 K10

MAD09_0 98 81 65 M10

MAD10_0 142 116 92 G10

MAD11_0 143 117 93 G9

MAD12_0 144 118 94 F10

MAD13_0 145 119 95 F11

MAD14_0 146 120 96 F12

MAD15_0 147 121 97 F13

MAD16_0 152 122 98 E10

MAD17_0 153 123 99 E11

MAD18_0 154 124 100 E12

MAD19_0 50 40 35 L1

MAD20_0 49 39 34 K4

MAD21_0 48 38 33 K3

MAD22_0 47 37 32 K2

MAD23_0 46 36 31 K1

MAD24_0 45 35 30 J2

MCSX0_0

External bus interface chip select

output pin

71 56 48 M5

MCSX1_0 70 55 47 L5

MCSX2_0 61 51 43 N4

MCSX3_0 60 50 42 M4

MCSX4_0 59 49 41 L4

MCSX5_0 58 48 40 M3

MCSX6_0 57 47 39 N3

MCSX7_0 56 46 38 N2

MCSX8_0 88 73 - P9




Pin Number

LQFP

216

LQFP

176

LQFP

144

LBE

192

External

bus

MADATA00_0

External bus interface data bus

(address/data multiplex bus)

2 2 2 B2

MADATA01_0 3 3 3 C2

MADATA02_0 4 4 4 C3

MADATA03_0 5 5 5 D5

MADATA04_0 6 6 6 D2

MADATA05_0 7 7 7 D1

MADATA06_0 8 8 8 D3

MADATA07_0 9 9 9 D4

MADATA08_0 14 13 10 E5

MADATA09_0 15 14 11 F1

MADATA10_0 16 15 12 F2

MADATA11_0 17 16 13 F3

MADATA12_0 18 17 14 F4

MADATA13_0 23 18 15 F5

MADATA14_0 24 19 16 F6

MADATA15_0 25 20 17 G2

MADATA16_0 10 - - -

MADATA17_0 11 - - -

MADATA18_0 12 - - -

MADATA19_0 13 - - -

MADATA20_0 19 - - -

MADATA21_0 20 - - -

MADATA22_0 21 - - -

MADATA23_0 22 - - -

MADATA24_0 26 - - -

MADATA25_0 27 - - -

MADATA26_0 28 - - -

MADATA27_0 29 - - -

MADATA28_0 33 - - -

MADATA29_0 51 - - -

MADATA30_0 52 - - -

MADATA31_0 53 - - -

MDQM0_0

External bus interface byte mask signal

output pin

30 21 18 G3

MDQM1_0 31 22 19 G4

MDQM2_0 34 - - -

MDQM3_0 35 - - -

MALE_0 External bus interface address latch

enable output signal for multiplex 211 171 139 C4

MRDY_0 External bus interface external RDY

input signal 80 65 55 L6

MCLKOUT_0 External bus interface external clock

output pin 32 23 20 G5




Pin Number

LQFP

216

LQFP

176

LQFP

144

LBE

192

External

bus

MNALE_0 External bus interface ALE signal to

control NAND flash output pin 47 37 32 K2

MNCLE_0 External bus interface CLE signal to

control NAND flash output pin 48 38 33 K3

MNREX_0 External bus interface read enable signal

to control NAND flash 50 40 35 L1

MNWEX_0 External bus interface write enable signal

to control NAND flash 49 39 34 K4

MOEX_0 External bus interface read enable

signal for SRAM 209 169 137 C5

MWEX_0 External bus interface write enable

signal for SRAM 210 170 138 B4

MSDCLK_0 SDRAM interface

SDRAM clock output pin 90 75 - L9

MSDCKE_0 SDRAM interface

SDRAM clock enable pin 89 74 - M9

MRASX_0 SDRAM interface

SDRAM column active strobe pin 85 70 - N8

MCASX_0 SDRAM interface

SDRAM row active strobe pin 86 71 - M8

MSDWEX_0 SDRAM interface

SDRAM write enable pin 87 72 - N9

External

interrupt

INT00_0

External interrupt request 00 input pin

2 2 2 B2

INT00_1 38 28 23 H3

INT00_2 19 - - -

INT01_0


7 7 7 D1

INT01_1 41 31 26 H6

INT01_2 51 41 - L2

INT02_0


14 13 10 E5

INT02_1 42 32 27 J5

INT02_2 26 - - -

INT03_0


17 16 13 F3

INT03_1 43 33 28 J4

INT03_2 34 24 - G6

INT04_0


59 49 41 L4

INT04_1 100 83 67 M11

INT04_2 65 - - -

INT05_0


70 55 47 L5

INT05_1 86 71 - M8

INT05_2 68 - - -




Pin Number

LQFP

216

LQFP

176

LQFP

144

LBE

192

External

interrupt

INT06_0


80 65 55 L6

INT06_1 87 72 - N9

INT06_2 103 - - -

INT07_0


82 67 57 L8

INT07_1 88 73 - P9

INT07_2 102 - - -

INT08_0


114 94 78 L11

INT08_1 127 103 - J9

INT08_2 119 - - -

INT09_0


123 99 83 J13

INT09_1 128 104 - H10

INT09_2 120 - - -

INT10_0


130 106 86 H9

INT10_1 138 112 - G13

INT10_2 149 - - -

INT11_0


133 109 89 G14

INT11_1 139 113 - F14

INT11_2 151 - - -

INT12_0


194 162 132 E7

INT12_1 169 139 - C11

INT12_2 175 - - -

INT13_0


184 152 122 E8

INT13_1 170 140 - D11

INT13_2 176 - - -

INT14_0


192 160 130 A6

INT14_1 171 141 - B10

INT14_2 201 - - -

INT15_0


193 161 131 D7

INT15_1 172 142 - C10

INT15_2 206 - - -

INT16_0 External interrupt request 16 input pin

25 20 17 G2

INT16_1 45 35 30 J2


30 21 18 G3

INT17_1 46 36 31 K1


31 22 19 G4

INT18_1 47 37 32 K2


36 26 21 H2

INT19_1 48 38 33 K3


91 76 60 K9

INT20_1 89 74 - M9




Pin Number

LQFP

216

LQFP

176

LQFP

144

LBE

192

External

interrupt


96 79 63 L10

INT21_1 90 75 - L9


99 82 66 N11

INT22_1 78 63 - K5


56 46 38 N2

INT23_1 79 64 - K6


147 121 97 F13

INT24_1 131 107 87 H12


153 123 99 E11

INT25_1 117 97 81 K14


156 126 102 D12

INT26_1 142 116 92 G10


157 127 103 D13

INT27_1 143 117 93 G9


190 158 128 A7

INT28_1 207 167 - E6


198 166 136 D6

INT29_1 208 168 - B5


209 169 137 C5

INT30_1 195 163 133 F7


212 172 140 B3

INT31_1 196 164 134 B6

NMIX Non-maskable interrupt input pin 158 128 104 C13




Pin Number

LQFP

216

LQFP

176

LQFP

144

LBE

192

GPIO

P00

General-purpose I/O port 0

164 134 110 B13

P01 165 135 111 A12

P02 166 136 112 C12

P03 167 137 113 B12

P04 168 138 114 B11

P08 30 21 18 G3

P09 31 22 19 G4

P0A 32 23 20 G5

P10


114 94 78 L11

P11 115 95 79 K13

P12 116 96 80 K12

P13 117 97 81 K14

P14 118 98 82 K11

P15 123 99 83 J13

P16 124 100 84 J12

P17 125 101 85 J11

P18 130 106 86 H9

P19 131 107 87 H12

P1A 132 108 88 H14

P1B 133 109 89 G14

P1C 134 110 90 H13

P1D 135 111 91 H11

P1E 142 116 92 G10

P1F 143 117 93 G9

P20


158 128 104 C13

P21 157 127 103 D13

P22 156 126 102 D12

P23 155 125 101 E13

P24 154 124 100 E12

P25 153 123 99 E11

P26 152 122 98 E10

P27 147 121 97 F13

P28 146 120 96 F12

P29 145 119 95 F11

P2A 144 118 94 F10




Pin Number

LQFP

216

LQFP

176

LQFP

144

LBE

192

GPIO

P30


34 24 - G6

P31 35 25 - H4

P32 36 26 21 H2

P33 37 27 22 J1

P34 38 28 23 H3

P35 41 31 26 H6

P36 42 32 27 J5

P37 43 33 28 J4

P38 44 34 29 J3

P39 45 35 30 J2

P3A 46 36 31 K1

P3B 47 37 32 K2

P3C 48 38 33 K3

P3D 49 39 34 K4

P3E 50 40 35 L1

P40


56 46 38 N2

P41 57 47 39 N3

P42 58 48 40 M3

P43 59 49 41 L4

P44 60 50 42 M4

P45 61 51 43 N4

P46 73 58 50 P5

P47 74 59 51 P6

P48 76 61 53 N6

P49 77 62 54 M6

P4A 65 - - -

P4B 66 - - -

P4C 67 - - -

P4D 68 - - -

P4E 69 - - -




Pin Number

LQFP

216

LQFP

176

LQFP

144

LBE

192

GPIO

P50


10 10 - E2

P51 11 11 - E3

P52 12 12 - E4

P53 13 - - -

P54 19 - - -

P55 20 - - -

P56 21 - - -

P57 22 - - -

P58 26 - - -

P59 27 - - -

P5A 28 - - -

P5B 29 - - -

P5C 33 - - -

P5D 51 41 - L2

P5E 52 42 - L3

P5F 53 43 - M2

P60


212 172 140 B3

P61 211 171 139 C4

P62 210 170 138 B4

P63 209 169 137 C5

P64 208 168 - B5

P65 207 167 - E6

P66 206 - - -

P67 205 - - -

P68 204 - - -

P69 203 - - -

P6A 202 - - -

P6B 201 - - -

P6C 200 - - -

P6D 199 - - -

P6E 198 166 136 D6




Pin Number

LQFP

216

LQFP

176

LQFP

144

LBE

192

GPIO

P70


80 65 55 L6

P71 81 66 56 J6

P72 82 67 57 L8

P73 83 68 58 K8

P74 84 69 59 J8

P75 91 76 60 K9

P76 92 77 61 P10

P77 93 78 62 N10

P78 96 79 63 L10

P79 97 80 64 K10

P7A 98 81 65 M10

P7B 99 82 66 N11

P7C 100 83 67 M11

P7D 70 55 47 L5

P7E 71 56 48 M5

P80


214 174 142 A3

P81 215 175 143 A2

P82 160 130 106 D14

P83 161 131 107 C14

P90


169 139 - C11

P91 170 140 - D11

P92 171 141 - B10

P93 172 142 - C10

P94 173 143 - D10

P95 174 144 - B9

P96 175 - - -

P97 176 - - -




Pin Number

LQFP

216

LQFP

176

LQFP

144

LBE

192

GPIO

PA0

General-purpose I/O port A

2 2 2 B2

PA1 3 3 3 C2

PA2 4 4 4 C3

PA3 5 5 5 D5

PA4 6 6 6 D2

PA5 7 7 7 D1

PA6 8 8 8 D3

PA7 9 9 9 D4

PA8 14 13 10 E5

PA9 15 14 11 F1

PAA 16 15 12 F2

PAB 17 16 13 F3

PAC 18 17 14 F4

PAD 23 18 15 F5

PAE 24 19 16 F6

PAF 25 20 17 G2

PB0

General-purpose I/O port B

126 102 - J10

PB1 127 103 - J9

PB2 128 104 - H10

PB3 129 105 - J14

PB4 138 112 - G13

PB5 139 113 - F14

PB6 140 114 - G12

PB7 141 115 - G11

PB8 119 - - -

PB9 120 - - -

PBA 121 - - -

PBB 122 - - -

PBC 148 - - -

PBD 149 - - -

PBE 150 - - -

PBF 151 - - -




Pin Number

LQFP

216

LQFP

176

LQFP

144

LBE

192

GPIO

PC0

General-purpose I/O port C

177 145 115 C9

PC1 178 146 116 B8

PC2 179 147 117 D9

PC3 180 148 118 E9

PC4 181 149 119 F9

PC5 182 150 120 C8

PC6 183 151 121 D8

PC7 184 152 122 E8

PC8 185 153 123 A10

PC9 186 154 124 F8

PCA 187 155 125 B7

PCB 190 158 128 A7

PCC 191 159 129 C7

PCD 192 160 130 A6

PCE 193 161 131 D7

PCF 194 162 132 E7

PD0

General-purpose I/O port D

195 163 133 F7

PD1 196 164 134 B6

PD2 197 165 135 C6

PE0

General-purpose I/O port E

104 84 68 N13

PE2 106 86 70 P12

PE3 107 87 71 P13

PF0

General-purpose I/O port F

78 63 - K5

PF1 79 64 - K6

PF2 85 70 - N8

PF3 86 71 - M8

PF4 87 72 - N9

PF5 88 73 - P9

PF6 89 74 - M9

PF7 90 75 - L9

PF8 94 - - -

PF9 95 - - -

PFA 101 - - -

PFB 102 - - -

PFC 103 - - -




Pin Number

LQFP

216

LQFP

176

LQFP

144

LBE

192

Multi-

Function

Serial

0

SIN0_0 Multi-function serial interface ch 0 input pin

157 127 103 D13

SIN0_1 151 - - -

SOT0_0

(SDA0_0)

Multi-function serial interface ch 0 output

pin

This pin operates as SOT0 when it is used

in a UART/CSIO/LIN (operation modes 0 to

3) and as SDA0 when it is used in an I2C

(operation mode 4).

156 126 102 D12

SOT0_1

(SDA0_1) 150 - - -

SCK0_0

(SCL0_0)

Multi-function serial interface ch 0 clock I/O

pin

This pin operates as SCK0 when it is used

in a CSIO (operation mode 2) and as SCL0

when it is used in an I2C (operation mode

4)

155 125 101 E13

SCK0_1

(SCL0_1) 149 - - -

Multi-

Function

Serial

1


7 7 7 D1

SIN1_1 80 65 55 L6

SOT1_0

(SDA1_0)


pin




(operation mode 4).

8 8 8 D3

SOT1_1

(SDA1_1) 81 66 56 J6

SCK1_0

(SCL1_0)


pin



when it is used in an I2C

(operation mode 4).

9 9 9 D4

SCK1_1

(SCL1_1) 70 55 47 L5

Multi-

Function

Serial

2


130 106 86 H9

SIN2_1 45 35 30 J2

SOT2_0

(SDA2_0)


pin




(operation mode 4).

131 107 87 H12

SOT2_1

(SDA2_1) 46 36 31 K1

SCK2_0

(SCL2_0)


pin




4).

132 108 88 H14

SCK2_1

(SCL2_1) 47 37 32 K2




Pin Number

LQFP

216

LQFP

176

LQFP

144

LBE

192

Multi-

Function

Serial

3


25 20 17 G2

SIN3_1 56 46 38 N2

SOT3_0

(SDA3_0)


pin




(operation mode 4).

24 19 16 F6

SOT3_1

(SDA3_1) 57 47 39 N3

SCK3_0

(SCL3_0)


pin


in a CSIO (operation modes 2) and as

SCL3 when it is used in an I2C (operation

mode 4).

23 18 15 F5

SCK3_1

(SCL3_1) 58 48 40 M3

Multi-

Function

Serial

4


212 172 140 B3

SIN4_1 193 161 131 D7

SOT4_0

(SDA4_0)


pin




(operation mode 4).

211 171 139 C4

SOT4_1

(SDA4_1) 192 160 130 A6

SCK4_0

(SCL4_0)


pin




4).

210 170 138 B4

SCK4_1

(SCL4_1) 198 166 136 D6

CTS4_0 Multi-function serial interface ch 4 CTS

input pin

208 168 - B5

CTS4_1 197 165 135 C6

RTS4_0 Multi-function serial interface ch 4 RTS

output pin

209 169 137 C5

RTS4_1 194 162 132 E7




Pin Number

LQFP

216

LQFP

176

LQFP

144

LBE

192

Multi-

Function

Serial

5


147 121 97 F13

SIN5_1 170 140 - D11

SOT5_0

(SDA5_0)


pin




(operation mode 4).

146 120 96 F12

SOT5_1

(SDA5_1) 171 141 - B10

SCK5_0

(SCL5_0)


pin

This pin operates as SCK5 when it is

used in a CSIO (operation mode 2)

and as SCL5 when it is used in an I2C

(operation mode 4).

145 119 95 F11

SCK5_1

(SCL5_1) 172 142 - C10

CTS5_0 Multi-function serial interface ch 5 CTS

input pin

144 118 94 F10

CTS5_1 173 143 - D10

RTS5_0 Multi-function serial interface ch 5 RTS

output pin

143 117 93 G9

RTS5_1 174 144 - B9

Multi-

Function

Serial

6


96 79 63 L10

SIN6_1 117 97 81 K14

SOT6_0

(SDA6_0)


pin




(operation mode 4).

97 80 64 K10

SOT6_1

(SDA6_1) 118 98 82 K11

SCK6_0

(SCL6_0)


pin




4).

98 81 65 M10

SCK6_1

(SCL6_1) 126 102 - J10

SCS60_0 Multi-function serial interface ch 6 chip

select 0 input/output pin

99 82 66 N11

SCS60_1 127 103 - J9


select1 input/output pin

100 83 67 M11

SCS61_1 128 104 - H10



79 64 - K6

SCS62_1 129 105 - J14



78 63 - K5

SCS63_1 119 - - -




Pin Number

LQFP

216

LQFP

176

LQFP

144

LBE

192

Multi-

Function

Serial

7


14 13 10 E5

SIN7_1 103 - - -

SOT7_0

(SDA7_0)


pin




(operation mode 4).

15 14 11 F1

SOT7_1

(SDA7_1) 102 - - -

SCK7_0

(SCL7_0)

Multi-function serial interface ch 7

clock I/O pin




4).

16 15 12 F2

SCK7_1

(SCL7_1) 101 - - -



17 16 13 F3

SCS70_1 94 - - -



18 17 14 F4

SCS71_1 95 - - -



10 10 - E2

SCS72_1 68 - - -



11 11 - E3

SCS73_1 69 - - -

Multi-

Function

Serial

8


91 76 60 K9

SIN8_1 138 112 - G13

SOT8_0

(SDA8_0)


pin




(operation mode 4).

92 77 61 P10

SOT8_1

(SDA8_1) 139 113 - F14

SCK8_0

(SCL8_0)


pin




4).

93 78 62 N10

SCK8_1

(SCL8_1) 140 114 - G12




Pin Number

LQFP

216

LQFP

176

LQFP

144

LBE

192

Multi-

Function

Serial

9


82 67 57 L8

SIN9_1 120 - - -

SOT9_0

(SDA9_0)


pin




(operation mode 4).

83 68 58 K8

SOT9_1

(SDA9_1) 121 - - -

SCK9_0

(SCL9_0)


pin




4).

84 69 59 J8

SCK9_1

(SCL9_1) 122 - - -

Multi-

Function

Serial

10

SIN10_0 Multi-function serial interface ch 10 input

pin

114 94 78 L11

SIN10_1 51 41 - L2

SOT10_0

(SDA10_0)


pin

This pin operates as SOT10 when it is

used in a UART/CSIO/LIN (operation

modes 0 to 3) and as SDA10 when it is

used in an I2C (operation mode 4).

115 95 79 K13

SOT10_1

(SDA10_1) 52 42 - L3

SCK10_0

(SCL10_0)

Multi-function serial interface ch 10 clock

I/O pin


used in a CSIO (operation mode 2) and as


mode 4).

116 96 80 K12

SCK10_1

(SCL10_1) 53 43 - M2

Multi-

Function

Serial

11


pin

123 99 83 J13

SIN11_1 26 - - -

SOT11_0

(SDA11_0)


pin





124 100 84 J12

SOT11_1

(SDA11_1) 27 - - -

SCK11_0

(SCL11_0)


I/O pin




mode 4).

125 101 85 J11

SCK11_1

(SCL11_1) 28 - - -




Pin Number

LQFP

216

LQFP

176

LQFP

144

LBE

192

Multi-

Function

Serial

12


pin

133 109 89 G14

SIN12_1 65 - - -

SOT12_0

(SDA12_0)


pin





134 110 90 H13

SOT12_1

(SDA12_1) 66 - - -

SCK12_0

(SCL12_0)


I/O pin




mode 4).

135 111 91 H11

SCK12_1

(SCL12_1) 67 - - -

Multi-

Function

Serial

13


pin

48 38 33 K3

SIN13_1 206 - - -

SOT13_0

(SDA13_0)


pin





49 39 34 K4

SOT13_1

(SDA13_1) 205 - - -

SCK13_0

(SCL13_0)


I/O pin




mode 4).

50 40 35 L1

SCK13_1

(SCL13_1) 204 - - -

Multi-

Function

Serial

14


pin

30 21 18 G3

SIN14_1 201 - - -

SOT14_0

(SDA14_0)


pin





31 22 19 G4

SOT14_1

(SDA14_1) 200 - - -

SCK14_0

(SCL14_0)


I/O pin




mode 4).

32 23 20 G5

SCK14_1

(SCL14_1) 199 - - -




Pin Number

LQFP

216

LQFP

176

LQFP

144

LBE

192

Multi-

Function

Serial

15


pin

59 49 41 L4

SIN15_1 19 - - -

SOT15_0

(SDA15_0)


pin





60 50 42 M4

SOT15_1

(SDA15_1) 20 - - -

SCK15_0

(SCL15_0)


I/O pin




mode 4).

61 51 43 N4

SCK15_1

(SCL15_1) 21 - - -




Pin Number

LQFP

216

LQFP

176

LQFP

144

LBE

192

Multi-

Function

Timer 0

DTTI0X_0 Input signal controlling waveform

generator outputs RTO00 to RTO05 of

Multi-Function Timer 0.

44 34 29 J3

DTTI0X_1 21 - - -

FRCK0_0 16-bit free-run timer ch 0 external

clock input pin

37 27 22 J1

FRCK0_1 29 - - -

IC00_0

16-bit input capture input pin of


ICxx describes channel number.

43 33 28 J4

IC00_1 22 - - -

IC01_0 42 32 27 J5

IC01_1 26 - - -

IC02_0 41 31 26 H6

IC02_1 27 - - -

IC03_0 38 28 23 H3

IC03_1 28 - - -

RTO00_0

(PPG00_0)

Waveform generator output pin of


This pin operates as PPG00 when it is

used in PPG0 output modes.

45 35 30 J2

RTO00_1

(PPG00_1) 10 10 - E2

RTO01_0

(PPG00_0)





46 36 31 K1

RTO01_1

(PPG00_1) 11 11 - E3

RTO02_0

(PPG02_0)





47 37 32 K2

RTO02_1

(PPG02_1) 12 12 - E4

RTO03_0

(PPG02_0)





48 38 33 K3

RTO03_1

(PPG02_1) 13 - - -

RTO04_0

(PPG04_0)





49 39 34 K4

RTO04_1

(PPG04_1) 19 - - -

RTO05_0

(PPG04_0)





50 40 35 L1

RTO05_1

(PPG04_1) 20 - - -




Pin Number

LQFP

216

LQFP

176

LQFP

144

LBE

192

Multi-

Function

Timer 1




70 55 47 L5

DTTI1X_1 94 - - -


clock input pin

71 56 48 M5

FRCK1_1 78 63 - K5

IC10_0




96 79 63 L10

IC10_1 95 - - -

IC11_0 97 80 64 K10

IC11_1 101 - - -

IC12_0 98 81 65 M10

IC12_1 102 - - -

IC13_0 99 82 66 N11

IC13_1 103 - - -

RTO10_0

(PPG10_0)





56 46 38 N2

RTO10_1

(PPG10_1) 85 70 - N8

RTO11_0

(PPG10_0)





57 47 39 N3

RTO11_1

(PPG10_1) 86 71 - M8

RTO12_0

(PPG12_0)





58 48 40 M3

RTO12_1

(PPG12_1) 87 72 - N9

RTO13_0

(PPG12_0)





59 49 41 L4

RTO13_1

(PPG12_1) 88 73 - P9

RTO14_0

(PPG14_0)





60 50 42 M4

RTO14_1

(PPG14_1) 89 74 - M9

RTO15_0

(PPG14_0)





61 51 43 N4

RTO15_1

(PPG14_1) 90 75 - L9




Pin Number

LQFP

216

LQFP

176

LQFP

144

LBE

192

Multi-

Function

Timer 2




8 8 8 D3

DTTI2X_1 202 - - -


clock input pin

17 16 13 F3

FRCK2_1 197 165 135 C6

IC20_0




9 9 9 D4

IC20_1 201 - - -

IC21_0 14 13 10 E5

IC21_1 200 - - -

IC22_0 15 14 11 F1

IC22_1 199 - - -

IC23_0 16 15 12 F2

IC23_1 198 166 136 D6

RTO20_0

(PPG20_0)





2 2 2 B2

RTO20_1

(PPG20_1) 203 - - -

RTO21_0

(PPG20_0)





3 3 3 C2

RTO21_1

(PPG20_1) 204 - - -

RTO22_0

(PPG22_0)





4 4 4 C3

RTO22_1

(PPG22_1) 205 - - -

RTO23_0

(PPG22_0)





5 5 5 D5

RTO23_1

(PPG22_1) 206 - - -

RTO24_0

(PPG24_0)





6 6 6 D2

RTO24_1

(PPG24_1) 207 167 - E6

RTO25_0

(PPG24_0)





7 7 7 D1

RTO25_1

(PPG24_1) 208 168 - B5




Pin Number

LQFP

216

LQFP

176

LQFP

144

LBE

192

Quadrature

Position/

Revolution

Counter

0

AIN0_0

QPRC ch 0 AIN input pin

56 46 38 N2

AIN0_1 65 - - -

AIN0_2 114 94 78 L11

BIN0_0

QPRC ch 0 BIN input pin

57 47 39 N3

BIN0_1 66 - - -

BIN0_2 115 95 79 K13

ZIN0_0

QPRC ch 0 ZIN input pin

58 48 40 M3

ZIN0_1 67 - - -

ZIN0_2 116 96 80 K12

Quadrature

Position/

Revolution

Counter

1

AIN1_0


91 76 60 K9

AIN1_1 94 - - -

AIN1_2 123 99 83 J13

BIN1_0


92 77 61 P10

BIN1_1 45 - - -

BIN1_2 124 100 84 J12

ZIN1_0


93 78 62 N10

ZIN1_1 101 - - -

ZIN1_2 125 101 85 J11

Quadrature

Position/

Revolution

Counter

2

AIN2_0


2 2 2 B2

AIN2_1 32 23 20 G5

AIN2_2 120 - - -

BIN2_0


3 3 3 C2

BIN2_1 36 26 21 H2

BIN2_2 121 - - -

ZIN2_0


4 4 4 C3

ZIN2_1 37 27 22 J1

ZIN2_2 122 - - -

Quadrature

Position/

Revolution

Counter

3

AIN3_0


18 17 14 F4

AIN3_1 45 35 30 J2

AIN3_2 149 - - -

BIN3_0


23 18 15 F5

BIN3_1 46 36 31 K1

BIN3_2 150 - - -

ZIN3_0


24 19 16 F6

ZIN3_1 47 37 32 K2

ZIN3_2 151 - - -

Real-time

clock

RTCCO_0 0.5 seconds pulse output pin of

real-time clock

211 171 139 C4

RTCCO_1 33 - - -

SUBOUT_0 Sub-clock output pin

211 171 139 C4

SUBOUT_1 33 - - -




Pin Number

LQFP

216

LQFP

176

LQFP

144

LBE

192

USB0

UDM0 USB ch 0 function/host D – pin 214 174 142 A3

UDP0 USB ch 0 function/host D + pin 215 175 143 A2

UHCONX0 USB ch 0 external pull-up control pin 211 171 139 C4

USB1

UDM1 USB ch 1 function/host D – pin 160 130 106 D14

UDP1 USB ch 1 function/host D + pin 161 131 107 C14

UHCONX1 USB ch 1 external pull-up control pin 155 125 101 E13

Low power

consump-

tion

mode

WKUP0 Deep standby mode return signal input

pin 0 158 128 104 C13


pin 1 14 13 10 E5


pin 2 70 55 47 L5


pin 3 212 172 140 B3

D/A

converter

DA0 D/A converter ch 0 analog output pin 100 83 67 M11

DA1 D/A converter ch 1 analog output pin 99 82 66 N11

VBAT

VREGCTL On-board regulator control pin 76 61 53 N6

VWAKEUP The return signal input pin from a

hibernation state 77 62 54 M6

SD I/F

S_CLK_0 SD memory card interface

SD memory card clock output pin 38 28 23 H3

S_CMD_0 SD memory card interface

SD memory card command output 41 31 26 H6

S_DATA1_0

SD memory card interface

SD memory card data bus

36 26 21 H2

S_DATA0_0 37 27 22 J1

S_DATA3_0 42 32 27 J5

S_DATA2_0 43 33 28 J4

S_CD_0 SD memory card interface

SD memory card detection pin 45 35 30 J2

S_WP_0 SD memory card interface

SD memory card write protection 44 34 29 J3




Pin Number

LQFP

216

LQFP

176

LQFP

144

LBE

192

Ethernet

E_COL Collision detection 186 154 124 F8

E_COUT Clock output for Ethernet PHY 190 158 128 A7

E_CRS Carrier detection 187 155 125 B7

E_MDC Management clock 184 152 122 E8

E_MDIO Management data I/O 183 151 121 D8

E_PPS PTP counter monitor 198 166 136 D6

E_RX00 Received data0 181 149 119 F9

E_RX01 Received data1 180 148 118 E9

E_RX02 Received data2 179 147 117 D9

E_RX03 Received data3 178 146 116 B8

E_RXCK_RE

FCK

Received clock input/

Reference clock 185 153 123 A10

E_RXDV Received data enable 182 150 120 C8

E_RXER Received data error detection 177 145 115 C9

E_TCK Transition clock input 191 159 129 C7

E_TX00 Transition data0 196 164 134 B6

E_TX01 Transition data1 195 163 133 F7

E_TX02 Transition data2 194 162 132 E7

E_TX03 Transition data3 193 161 131 D7

E_TXEN Transition data enable 197 165 135 C6

E_TXER Transition data error detection 192 160 130 A6

HDMI-CEC/

remote

control

reception

CEC0_0 HDMI-CEC/remote control

reception ch 0 input/output pin 80 65 55 L6

CEC1_0 HDMI-CEC/remote control

reception ch 1 input/output pin 212 172 140 B3

I2S

I2SMCLK_0 I2S external clock pin 51 41 - L2

I2SDO_0 I2S serial transition data output pin 52 42 - L3

I2SWS_0 I2S frame synchronization signal pin 53 43 - M2

I2SDI_0 I2S serial received data input pin 34 24 - G6

I2SCK_0 I2S bit clock pin 35 25 - H4

High-speed

quad SPI

Q_SCK_0 SPI clock output pin 173 143 - D10

Q_IO0_0

SPI data input/output pin

172 142 - C10

Q_IO1_0 171 141 - B10

Q_IO2_0 170 140 - D11

Q_IO3_0 169 139 - C11

Q_CS0_0

SPI chip select output pin

174 144 - B9

Q_CS1_0 175 - - -

Q_CS2_0 176 - - -




Pin Number

LQFP

216

LQFP

176

LQFP

144

LBE

192

Reset INITX External reset Input pin

A reset is valid when INITX = "L.” 72 57 49 N5

Mode

MD1

Mode 1 pin

During serial programming to flash

memory, MD1 = "L" must be input.

104 84 68 N13

MD0

Mode 0 pin

During normal operation, MD0 = "L" must

be input. During serial programming to

flash memory, MD0 = "H" must be input.

105 85 69 N12

Power

VCC Power supply pin

1 1 1 C1

39 29 24 H1

55 45 37 N1

64 54 46 P4

109 89 73 M14

137 - - -

163 133 109 A13

USBVCC0 3.3V power supply port for USB I/O

213 173 141 A4

USBVCC1 159 129 105 E14

ETHVCC Power supply pin for Ethernet I/O 188 156 126 A9

GND VSS GND pin

40 30 25 H5

54 44 36 M1

63 53 45 P3

108 88 72 N14

136 - - -

162 132 108 B14

189 157 127 A8

216 176 144 B1

- - - E1

- - - G1

- - - P7

- - - P11

- - - L14

- - - A11

- - - A5

- - - N7

- - - M7

- - - K7

- - - J7

- - - G7

- - - H7

- - - H8

- - - G8




Pin Number

LQFP

216

LQFP

176

LQFP

144

LBE

192

Clock

X0 Main clock (oscillation) input pin 106 86 70 P12

X1 Main clock (oscillation) I/O pin 73 58 50 P5

X0A Sub clock (oscillation) input pin 107 87 71 P13

X1A Sub clock (oscillation) I/O pin 74 59 51 P6

CROUT_0 Built-in high-speed CR-oscillation clock

output port

157 127 103 D13

CROUT_1 184 152 122 E8

Analog

power

AVCC A/D converter and D/A converter

analog power-supply pin 110 90 74 M13

AVRL A/D converter analog reference voltage

input pin 112 92 76 L13

AVRH A/D converter analog reference voltage

input pin 113 93 77 L12

VBAT

power VBAT

VBAT power supply pin

Backup power supply (battery etc.) and

system power supply

75 60 52 P8

Analog

GND AVSS

A/D converter and D/A converter

GND pin 111 91 75 M12

C pin C Power supply stabilization capacity pin 62 52 44 P2



7. I/O Circuit Type

Type Circuit Remarks

A

It is possible to select the main

oscillation/GPIO function.

When the main oscillation

is selected:

・ Oscillation feedback resistor:

approximately 1 MΩ

・ Standby mode control

When the GPIO is selected:

・ CMOS level output.

・ CMOS level hysteresis input

・ Pull-up resistor control


・ Pull-up resistor:

approximately 50 kΩ

・ IOH = -4 mA, IOL = 4 mA

B




P-chP-ch

N-ch

R

R

P-chP-ch

N-ch

X0

X1

Standby mode control

Digital input


Digital output

Digital output

Clock input

Digital input


Pull-up resistor control


Digital output

Digital output

Pull-up resistor

Digital input




C

・ Open drain output


E

・ CMOS level output







F



・ Input control

・ Analog input






N-ch

P-chP-ch

N-ch

R

P-chP-ch

N-ch

R

Digital input

Digital output

Digital output

Digital output


Digital input


Digital output

Digital output


Digital input


Analog input

Input control




G







・ IOH = -12 mA, IOL = 12 mA

H

It is possible to select either USB

I/O or GPIO function.

When the USB I/O is selected:

・ Full-speed, low-speed control





・ IOH = -20.5 mA, IOL = 18.5 mA

P-chP-ch

N-ch

R

UDP/Pxx

UDM/Pxx

Differential



Digital input

Digital output

Digital output

GPIO Digital output

GPIO Digital input/output direction

GPIO Digital input

GPIO Digital input circuit control

UDP output

USB Full-speed/Low-speed control

UDP input

Differential input

USB/GPIO select

UDM input

UDM output

USB Digital input/output direction GPIO Digital output

GPIO Digital input/output direction GPIO Digital input

GPIO Digital input circuit control




I



・ 5V tolerant






・ Available to control of PZR

registers (pseudo-open drain

control)

J

CMOS level hysteresis input

K


・ TTL level hysteresis input


・Standby mode control



・ IOH = -4mA, IOL = 4mA

P-chP-ch

N-ch

R

P-chP-ch

N-ch

R



Digital input

Digital output

Digital output

Mode input

Digital output

Digital output


Digital input





L








N







・ IOH = -4 mA, IOL = 4 mA (GPIO)

・ IOL = 20mA (Fast mode Plus)


register (pseudo-open drain

control)

・ For PZR registers, refer to GPIO

in the “FM4 Family Peripheral

Manual Main Part

(MN709-00001)”.

P-chP-ch

N-ch

R

P-chP-ch

N-ch

R

Digital output

Digital output

Digital input


Digital output

Digital output


Digital input






O



・ 5V tolerant






register (pseudo-open drain

control)

・ For PZR registers, refer to GPIO

in the “FM4 Family Peripheral

Manual Main Part

(MN709-00001)”.

・ For I/O setting, refer to VBAT

Domain in the "FM4 Family

Peripheral Manual Main Part

(MN709-00001).”

P










(MN709-00001).”

P-ch

P-ch

N-ch

R

P-ch

P-ch

N-ch

R

Digital output

Digital output

Digital input



Digital output

Digital output

Digital input



OSC

X0A




Q

It is possible to select the sub

oscillation/GPIO function.

When the sub oscillation

is selected:

・ Oscillation feedback resistor:

approximately 10 MΩ


・ CMOS level output.









(MN709-00001).”

R



・ Analog output






(4.5V to 5.5V)


(2.7V to 4.5V)

P-ch

P-ch

N-ch

R

RX

P-ch

N-ch

R

P-ch

X1A Digital output

Digital output

Digital input


Standby mode control OSC


Clock input


Digital input


Analog output

Digital output

Digital output




S


・ (It is possible to select by port

drive capability. Select register

[PDSR])






・ IOH = -12 mA, IOL = 12 mA (PDSR

= 1)

・ IOH = -4 mA, IOL = 4 mA (PDSR =

0)

P-ch

P-ch

N-ch

R

Digital output

Port Drive Select

Digital input

Standby mode Control




8. Handling Precautions

Every semiconductor device has a characteristic, inherent rate of failure. The possibility of failure is greatly

affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This

page describes precautions that must be observed to minimize the chance of failure and to obtain higher

reliability from your Spansion semiconductor devices.

8.1 Precautions for Product Design

This section describes precautions when designing electronic equipment using semiconductor devices.

Absolute Maximum Ratings

Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature,

etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings.

Recommended Operating Conditions

Recommended operating conditions are normal operating ranges for the semiconductor device. All the

device's electrical characteristics are warranted when operated within these ranges.

Always use semiconductor devices within the recommended operating conditions. Operation outside these

ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on the data

sheet. Users considering application outside the listed conditions are advised to contact their sales

representative beforehand.

Processing and Protection of Pins

These precautions must be followed when handling the pins that connect semiconductor devices to power

supply and I/O functions.

1. Preventing Over-Voltage and Over-Current Conditions

Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause

deterioration within the device, and in extreme cases leads to permanent damage of the device. Try

to prevent such overvoltage or over-current conditions at the design stage.

2. Protection of Output Pins

Shorting of output pins to supply pins or other output pins, or connection to large capacitance can

cause large current flows. Such conditions, if present for extended periods of time, can damage the

device; therefore, avoid this type of connection.

3. Handling of Unused Input Pins

Unconnected input pins with very high impedance levels can adversely affect stability of operation.

Such pins should be connected through an appropriate resistance to a power-supply pin or ground

pin.

Code: DS00-00004-3E



Latch-Up

Semiconductor devices are constructed by the formation of p-type and n-type areas on a substrate. When

subjected to abnormally high voltages, internal parasitic pnpn junctions (called thyristor structures) may be

formed, causing large current levels in excess of several hundred milliamps to flow continuously at the

power supply pin. This condition is called latch-up.

CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but

can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the

following:

1. Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should

include attention to abnormal noise, surge levels, etc.

2. Be sure that abnormal current flows do not occur during the power-on sequence.

Observance of Safety Regulations and Standards

Most countries in the world have established standards and regulations regarding safety, protection from

electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards

in the design of products.

Fail-Safe Design

As previously mentioned, all semiconductor devices have inherent rates of failure. You must protect against

injury, damage or loss from such failures by incorporating safety design measures into your facility and

equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal

operating conditions.

Precautions Related to Usage of Devices

Spansion semiconductor devices are intended for use in standard applications (computers, office

automation and other office equipment, industrial, communications, and measurement equipment, personal

or household devices, etc.).

CAUTION: Customers considering the use of our products in special applications where failure or abnormal

operation may directly affect human lives or cause physical injury or property damage, or where extremely

high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor

repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with

sales representatives before such use. The company will not be responsible for damages arising from such

use without prior approval.

8.2 Precautions for Package Mounting

Package mounting may be either lead insertion type or surface mount type. In either case, for heat

resistance during soldering, you should only mount under Spansion's recommended conditions. For detailed

information about mount conditions, contact your sales representative.

Lead Insertion Type

Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct

soldering on the board, or mounting by using a socket.

Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board

and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the soldering

process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage

temperature. Mounting processes should conform to Spansion recommended mounting conditions.



If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can

lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment

of socket contacts and IC leads be verified before mounting.

Surface Mount Type

Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads

are more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results

in increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges.

You must use appropriate mounting techniques. Spansion recommends the solder reflow method, and has

established a ranking of mounting conditions for each product. Users are advised to mount packages in

accordance with Spansion ranking of recommended conditions.

Lead-Free Packaging

CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic

soldering, junction strength may be reduced under some conditions of use.

Storage of Semiconductor Devices

Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions

will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed

moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To

prevent this, do the following:

1. Avoid exposure to rapid temperature changes, which can cause moisture to condense inside the

product. Store products in locations where temperature changes are slight.

2. Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at

temperatures between 5°C and 30°C.

3. When Dry Packages are opened, it is recommended to have humidity between 40% and 70%.

4. When necessary, Spansion packages semiconductor devices in highly moisture-resistant aluminum

laminate bags, with a silica gel desiccant. Devices should be sealed in these aluminum laminate

bags for storage.

5. Avoid storing packages where they are exposed to corrosive gases or high levels of dust.

Baking

Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Spansion

recommended conditions for baking.

Condition: 125°C/24 h

Static Electricity

Because semiconductor devices are particularly susceptible to damage by static electricity, you must take

the following precautions:

1. Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus

for ion generation may be needed to remove electricity.

2. Electrically ground all conveyors, solder vessels, soldering irons, and peripheral equipment.

3. Eliminate static body electricity by the use of rings or bracelets connected to ground through high

resistance (on the level of 1 MΩ). Wearing of conductive clothing and shoes, and the use of

conductive floor mats and other measures to minimize shock loads is recommended.

4. Ground all fixtures and instruments, or protect with anti-static measures.

5. Avoid the use of Styrofoam or other highly static-prone materials for storage of completed board

assemblies.



8.3 Precautions for Use Environment

Reliability of semiconductor devices depends on ambient temperature and other conditions as described

above.

For reliable performance, do the following:

1. Humidity

Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If

high humidity levels are anticipated, consider anti-humidity processing.

2. Discharge of static electricity

When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal

operation. In such cases, use anti-static measures or processing to prevent discharges.

3. Corrosive gases, dust, or oil

Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will

adversely affect the device. If you use devices in such conditions, consider ways to prevent such

exposure or to protect the devices.

4. Radiation, including cosmic radiation

Most devices are not designed for environments involving exposure to radiation or cosmic radiation.

Users should provide shielding as appropriate.

5. Smoke, flame

CAUTION: Plastic molded devices are flammable and therefore should not be used near

combustible substances. If devices begin to smoke or burn, there is danger of the release of toxic

gases.

Customers considering the use of Spansion products in other special environmental conditions should

consult with sales representatives.

Please check the latest handling precautions at the following URL.

http://www.spansion.com/fjdocuments/fj/datasheet/e-ds/DS00-00004.pdf



9. Handling Devices

Power-Supply Pins

In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected within

the device in order to prevent malfunctions such as latch-up. All of these pins should be connected

externally to the power supply or ground lines, however, in order to reduce electromagnetic emission levels,

to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the

total output current rating.

Be sure to connect the current-supply source with the power pins and GND pins of this device at low

impedance. It is also advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass

capacitor between VCC and VSS near this device.

A malfunction may occur when the power-supply voltage fluctuates rapidly even though the fluctuation is

within the guaranteed operating range of the VCC power supply voltage. As a rule of voltage stabilization,

suppress voltage fluctuation so that the fluctuation in VCC ripple (peak-to-peak value) at the commercial

frequency (50 Hz/60 Hz) does not exceed 10% of the standard VCC value, and the transient fluctuation rate

does not exceed 0.1V/μs at a momentary fluctuation such as switching the power supply.

Crystal Oscillator Circuit

Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit

board so that X0/X1, X0A/X1A pins, the crystal oscillator (or ceramic oscillator), and the bypass capacitor to

ground are located as close to the device as possible.

It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins

are surrounded by ground plane, as this is expected to produce stable operation.

Evaluate the oscillation introduced by the use of the crystal oscillator by your mount board.

Sub Crystal Oscillator

The sub-oscillator circuit for devices in this family is low gain to keep current consumption low. To stabilize

the oscillation, Spansion recommends a crystal oscillator that meets the following conditions:

Surface mount type

Size: More than 3.2 mm × 1.5 mm

Load capacitance: approximately 6 pF to 7 pF

Lead type

Load capacitance: approximately 6 pF to 7 pF



Using an External Clock

When using an external clock as an input of the main clock, set X0/X1 to the external clock input, and input

the clock to X0. X1(PE3) can be used as a general-purpose I/O port. Similarly, when using an external clock

as an input of the sub clock, set X0A/X1A to the external clock input and input the clock to X0A. X1A (P47)

can be used as a general-purpose I/O port.

Handling When Using Multi-Function Serial Pin As I2C Pin

If the application uses the multi-function serial pin as an I2C pin, the P-channel transistor of the digital output

must be disabled. I2C pins need to conform to electrical limitations like other pins, however, and avoid

connecting to live external systems with the MCU power off.

C Pin

Devices in this series contain a regulator. Be sure to connect a smoothing capacitor (CS) for the regulator

between the C pin and the GND pin. Please use a ceramic capacitor or a capacitor of equivalent frequency

characteristics as a smoothing capacitor. Some laminated ceramic capacitors have a large capacitance

variation due to thermal fluctuation. Please select a capacitor that meets the specifications in the operating

conditions to use by evaluating the temperature characteristics of the device. A smoothing capacitor of about

4.7 μF would be recommended for this series.

Mode Pins (MD0)

Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the

pull-up/down resistance stays low, the distance between the mode pins and VCC pins or VSS pins is as

short as possible, and the connection impedance is low when the pins are pulled up/down such as for

switching the pin level and rewriting the flash memory data. This is important to prevent the device from

erroneously switching to test mode as a result of noise.

Example of Using an External Clock

Device

X0(X0A)

X1(PE3), X1A (P47)

Can be used as

general-purpose

I/O ports.

Set as external clock

input

Device

C

VSS

CS

GND



Notes On Power-On

Turn power on/off in the sequence shown below or at the same time. If not using the A/D converter and D/A

converter, connect AVCC = VCC and AVSS = VSS.

Turning on: VBAT → VCC → USBVCC0

VBAT → VCC → USBVCC1

VBAT →VCC →ETHVCC

VCC → AVCC → AVRH

Turning off: USBVCC0 → VCC → VBAT

USBVCC1 → VCC → VBAT

ETHVCC → VCC → VBAT

AVRH → AVCC → VCC

Serial Communication

There is a possibility of receiving incorrect data as a result of noise or other issues introduced by the serial

communication. Take care to design the printed circuit board to minimize noise.

Consider the case of introducing error as a result of noise, perform error detection such as by applying a

checksum of data at the end. If an error is detected, retransmit the data.

Differences In Characteristics Within the Product Line

The electric characteristics including power consumption, ESD, latch-up, noise, and oscillation differ among

members of the product line because chip layout and memory structures are not the same; for example,

different sizes, flash versus ROM, etc. If you are switching to a different product of the same series, please

make sure to evaluate the electric characteristics.

Pull-Up Function of 5V Tolerant I/O

Please do not input the signal more than VCC voltage at the time of Pull-Up function use of 5V tolerant I/O.

Pin Doubled As Debug Function

The pin doubled as TDO/TMS/TDI/TCK/TRSTX, SWO/SWDIO/SWCLK should be used as output only. Do

not use as input.



10. Block Diagram

Cortex-M4　Core

@200 MHz(Max)

MainFlash I/F

Clock Reset

Generator

Dual-Timer

Watchdog Timer

(Hardware)

Watch Counter

Unit 0

CSV

External Interrupt

Controller

32-pin + NMI

Power-On

Reset

SRAM096/144/192 Kbytes

AH

B-A

PB

Brid

ge

: A

PB

1 (

Ma

x 2

00

MH

z)

SRAM1

32 Kbytes

AH

B-A

PB

Brid

ge

:

AP

B0

(Ma

x 1

00

MH

z)

I

D

Sys

CLK

S6E2CCAH/J/L, S6E2CC9H/J/L, S6E2CC8H/J/L

AH

B-A

PB

Brid

ge

: A

PB

2 (

Ma

x 1

00

MH

z)

NVIC

Watchdog Timer

(Software)

Security

Unit 1

TRSTX,TCK,

TDI,TMS

TRACEDx,

TRACECLK

X0

AVCC,

AVSS,

AVRH,

AVRL

ANxx

TIOAx

TIOBx

C

TDO

X1

X0A

X1A

SCKx

SINx

SOTx

INTx

NMIX

P0x,

P1x,.

.

.

PFx

INITX

MODE-Ctrl

IRQ-Monitor

MD0,

MD1

Regulator

CRC Accelerator

AH

B-A

HB

Brid

ge

(Sla

ve)

ADTGx

RTSx

CTSx

MADx

MADATAx

MainFlash/DualFlash

2 Mbytes(1M+1M)/

1.5 Mbytes(1M+0.5M)/

1 Mbytes(MainOnly)

Multi-function Serial I/F

16ch.

(with FIFO ch.0 to ch.7)

HW flow control(ch.4,5)

External Bus I/F

LVD

Mu

lti-la

ye

r A

HB

(M

ax 2

00

MH

z)

TPIU/ETB*ROM

Table

ETM/HTM*SWJ-DP

Main

OscPLL

CR

100 kHz

LVD Ctrl

Base Timer

16-bit 32ch./

32-bit 16ch.

Peripheral Clock Gating

Low-speed CR Prescaler

RTCCO,

SUBOUT

Deep Standby Ctrl WKUPx

16-bit Free-run Timer

3ch.

16-bit Output Compare

6ch.

16-bit Input Capture

4ch.

A/D Activation Compare

6ch.

16-bit PPG

3ch.

DTTI0X

FRCK0

QPRC

4ch.BINx

ZINx

IC0x

RTO0x

AINx

12-bit A/D Converter

Multi-function Timer × 3

MCSXx,MDQMx,

MOEX,MWEX,

MALE,MRDY,

MNALE,MNCLE,

MNWEX,MNREX,

MCLKOUT,MSDWEX,

MSDCLK,MSDCKE,

MRASX,MCASX

Waveform Generator

3ch.

MPUFPU

12-bit D/A Converter

2units

SRAM2

32 Kbytes

Trace Buffer

(16 Kbytes)

USBVCC0

UDP0,UDM0

UHCONX0

TX0,RX0

TX1,RX1

S_CLK,S_CMD

S_DATAx

S_CD,S_WP

CAN Prescaler

I2S Clock Ctrl PLL

VREGCTL

VWAKEUP

Unit 2

DAx

Real-Time Clock

Port Ctrl.

Sub

Osc

VBAT Domain

VBAT DomainCR

4 MHz

CROUT

Source Clock

USB Clock Ctrl PLL

HDMI-CEC/Remote

Receiver ControlCECx

USBVCC1

UDP1,UDM1

UHCONX1

CAN ch.0

CAN ch.1

CAN ch.2 TX2,RX2

PRG-CRC

Accelerator

I2SMCLK,

I2SWS,

I2SCKI2SDI

I2SDO

Q_SCK, Q_CSx

Q_IOx

AH

B-A

HB

Brid

ge

(Ma

ste

r)

GPIO

PIN-Function-Ctrl

E_TXx,

E_RXx,

E_MDx

DMAC

8ch.

DSTC

Hi-Speed Quad SPI

PHY

PHY

USB2.0

(Host/

Func)

USB2.0

(Host/

Func)

SD-CARD I/F

VBAT

ETHVCCEthernet-MAC

ch.0

DualFlash I/F

I2S

1unit



11. Memory Size

See "Memory size" in "3. Product Lineup" to confirm the memory size.

12. Memory Map

Memory Map (1)

Peripherals Area

0x41FF_FFFF

0x4008_1000

0x4008_0000 Programmable-CRC

0x4007_0000 CAN-FD (CAN ch.2)

0x4006_F000 GPIO

0x4006_E000 SD-Card I/F

0xFFFF_FFFF 0x4006_D000 Reserved

0x4006_C000 I2S

0xE010_0000

0xE000_0000

0x4006_7000

0xD000_0000 0x4006_6000 Ether-Control-Reg.

0x4006_4000 Ether-MAC ch.0

0x4006_3000 CAN ch.1

0x4006_2000 CAN ch.0

0x4006_1000 DSTC

0x4006_0000 DMAC

0x6000_0000 0x4005_0000 USB ch.1

0x4004_0000 USB ch.0

0x4003_F000 EXT-bus I/F

0x4400_0000 0x4003_E000 Reserved

0x4003_D000 I2S prescaler

0x4200_0000 0x4003_C800 Reserved

0x4003_C100 Peripheral Clock Gating

0x4003_C000 Low Speed CR Prescaler

0x4000_0000 0x4003_B000 RTC/Port Ctrl

0x4003_A000 Watch Counter

0x4003_9000 CRC

0x2400_0000 0x4003_8000 MFS

0x4003_7000 CAN prescaler

0x2200_0000 0x4003_6000 USB Clock ctrl

0x4003_5000 LVD/DS mode

0x4003_4000 HDMI-CEC

0x200F_0000 0x4003_3000 D/AC

0x4003_2000 Reserved

0x4003_1000 Int-Req.Read

0x4003_0000 EXTI

0x2004_8000 0x4002_F000 Reserved

0x2004_0000 SRAM2 0x4002_E000 CR Trim

0x2003_8000 SRAM1


0x1FFF_0000 SRAM0 0x4002_8000

0x0050_0000 Reserved 0x4002_7000 A/DC

0x0040_0000 Security/CR Trim 0x4002_6000 QPRC

0x4002_5000 Base Timer

0x4002_4000 PPG


0x0000_0000 0x4002_2000 MFT Unit2

0x4002_1000 MFT Unit1

0x4002_0000 MFT Unit0

0x4001_6000

0x4001_5000 Dual Timer

0x4001_3000

0x4001_2000 SW WDT

0x4001_1000 HW WDT

0x4001_0000 Clock/Reset

0x4000_1000

0x4000_0000 MainFlash I/F

Reserved

Reg. Area

32 Mbytes

Bit band alias

32 Mbytes

Bit band alias

Reserved

Reserved

Reserved

DualFlash

Reserved

Reserved

メモリサイズの詳細は

次項の「●メモリマップ(2)」

を参照してください。

Reserved

Cortex-M4 Private

Peripherals

Peripherals

Reserved

Reserved

External Device

Area

MainFlash

Reserved

See "Memory Map

(2) and (3)" for

memory size

details.



Memory Map (2)

* See "S6E2CC/S6E2C5/S6E2C4/S6E2C3/S6E2C2/S6E2C1 Series Flash Programming Manual” to confirm

the detail of flash Memory.

S6E2CCAH/J/L S6E2CC9H/J/L S6E2CC8H/J/L

0x2020_0000 0x2020_0000 0x2020_0000

0x2004_8000 0x2004_8000 0x2004_8000

0x2004_0000 0x2004_0000 0x2004_0000

0x2003_8000 0x2003_8000 0x2003_8000

0x2000_0000 0x2000_0000 0x2000_0000

0x1FFF_0000

0x1FFE_0000

0x1FFD_0000

0x0041_0000 0x0041_0000 0x0041_0000

0x0040_8000 0x0040_8000 0x0040_8000

0x0040_6000 SA3(#0) (8KB) 0x0040_6000 SA3(#0) (8KB) 0x0040_6000 SA3(#0) (8KB)

0x0040_4000 General purpose 0x0040_4000 General purpose 0x0040_4000 General purpose

0x0040_2000 CR trimming 0x0040_2000 CR trimming 0x0040_2000 CR trimming

0x0040_0000 Security 0x0040_0000 Security 0x0040_0000 Security

0x0020_0000

0x0018_0000

SA9-15(#1) (64KBx7)

SA8(#1) (32KB) SA8(#1) (32KB)

0x0010_0000 SA4-7(#1) (8KBx4) 0x0010_0000 SA4-7(#1) (8KBx4) 0x0010_0000

SA8(#0) (32KB) SA8(#0) (32KB) SA8(#0) (32KB)

0x0000_0000 SA4-7(#0) (8KBx4) 0x0000_0000 SA4-7(#0) (8KBx4) 0x0000_0000 SA4-7(#0) (8KBx4)

Reserved Reserved Reserved

SRAM2

32 Kbytes

SRAM2

32 Kbytes

SRAM2

32 Kbytes

SRAM1

32 Kbytes

SRAM1

32 Kbytes

SRAM1

32 Kbytes


SRAM0

192 Kbytes

SRAM0

128 Kbytes

SRAM0

64 Kbytes

ReservedReserved

Reserved

SA0-3(#1) (8KBx4)

Main

Fla

sh

40 K

byte

s

SA0-3(#1) (8KBx4)

Main

Fla

sh

40 K

byte

s

SA0-3(#1) (8KBx4)

Main

Fla

sh

40 K

byte

s

Reserved

Reserved

Reserved

SA9-23(#1) (64KBx15)

Main

Fla

sh

2 M

byte

s

Main

Fla

sh

1.5

Mbyte

s

SA9-23(#0) (64KBx15) SA9-23(#0) (64KBx15) SA9-23(#0) (64KBx15)

Main

Fla

sh

1 M

byte

s



Memory Map (2) During Dual Flash Mode

S6E2CCAH/J/L S6E2CC9H/J/L S6E2CC8H/J/L

0x2020_0000 0x2020_0000 0x2020_0000

0x2018_0000

SA8(#1) (32KB) SA8(#1) (32KB)

0x2010_0000 SA4-7(#1) (8KBx4) 0x2010_0000 SA4-7(#1) (8KBx4) 0x2010_0000

0x200F_8000 SA0-3(#1) (8KBx4) 0x200F_8000 SA0-3(#1) (8KBx4) 0x200F_8000 SA0-3(#1) (8KBx4)

0x2004_8000 0x2004_8000 0x2004_8000

0x2004_0000 0x2004_0000 0x2004_0000

0x2003_8000 0x2003_8000 0x2003_8000

0x2000_0000 0x2000_0000 0x2000_0000

0x1FFF_0000

0x1FFE_0000

0x1FFD_0000

0x0041_0000 0x0041_0000 0x0041_0000

0x0040_8000 0x0040_8000 0x0040_8000

0x0040_6000 SA3(#0) (8KB) 0x0040_6000 SA3(#0) (8KB) 0x0040_6000 SA3(#0) (8KB)

0x0040_4000 General purpose 0x0040_4000 General purpose 0x0040_4000 General purpose

0x0040_2000 CR trimming / HTM 0x0040_2000 CR trimming / HTM 0x0040_2000 CR trimming / HTM

0x0040_0000 Security 0x0040_0000 Security 0x0040_0000 Security

0x0010_0000 0x0010_0000 0x0010_0000

SA8(#0) (32KB) SA8(#0) (32KB) SA8(#0) (32KB)

0x0000_0000 SA4-7(#0) (8KBx4) 0x0000_0000 SA4-7(#0) (8KBx4) 0x0000_0000 SA4-7(#0) (8KBx4)

DualF

lash

32 K

byte

s

SA9-15(#1) (64KBx7)

Reserved Reserved

SA9-23(#1) (64KBx15) DualF

lash

1 M

byte

s +

32 K

byte

s

Reserved

Reserved

SRAM2

32 Kbytes

DualF

lash

512 K

byte

s +

32 K

byte

s

Reserved

SRAM2

32 Kbytes

SRAM2

32 Kbytes

Reserved

SRAM1

32 Kbytes

SRAM1

32 Kbytes

SRAM1

32 Kbytes

Reserved Reserved

SRAM0

192 Kbytes

SRAM0

128 Kbytes

SRAM0

64 Kbytes

ReservedReserved

Reserved

Reserved

Reserved

SA9-23(#0) (64KBx15)

Main

Fla

sh

8 K

byte

s


Main

Fla

sh

8 K

byte

s

Reserved

Main

Fla

sh

8 K

byte

s

Main

Fla

sh

1 M

byte

s

SA9-23(#0) (64KBx15)

Main

Fla

sh

1 M

byte

s

SA9-23(#0) (64KBx15)

Main

Fla

sh

1 M

byte

s



Memory Map (3)

S6E2CCAH S6E2CCAJ S6E2CCAL

0xD000_0000 0xD000_0000 0xD000_0000

0xC000_0000 0xC000_0000 0xC000_0000

0x8000_0000 0x8000_0000 0x8000_0000

0x7000_0000 0x7000_0000 0x7000_0000

0x6000_0000 0x6000_0000 0x6000_0000

SRAM

/NOR Flash Memory

/NAND Flash Memory

256 Mbytes

SDRAM

256 Mbytes

Reserved Reserved

SDRAM

256 Mbytes

Reserved

SRAM

/NOR Flash Memory

/NAND Flash Memory

256 Mbytes

SRAM

/NOR Flash Memory

/NAND Flash Memory

256 Mbytes

Hi-Speed Quad SPI

256 Mbytes

Hi-Speed Quad SPI

256 Mbytes



Peripheral Address Map

Start Address End Address Bus Peripherals

0x4000_0000 0x4000_0FFF AHB

MainFlash I/F register

0x4000_1000 0x4000_FFFF Reserved

0x4001_0000 0x4001_0FFF

APB0

Clock/reset control

0x4001_1000 0x4001_1FFF Hardware watchdog timer

0x4001_2000 0x4001_2FFF Software watchdog timer

0x4001_3000 0x4001_4FFF Reserved

0x4001_5000 0x4001_5FFF Dual-timer

0x4001_6000 0x4001_FFFF Reserved

0x4002_0000 0x4002_0FFF

APB1

Multi-Function Timer unit 0

0x4002_1000 0x4002_1FFF Multi-Function Timer unit 1

0x4002_2000 0x4002_2FFF Multi-Function Timer unit 1


0x4002_4000 0x4002_4FFF PPG

0x4002_5000 0x4002_5FFF Base timer

0x4002_6000 0x4002_6FFF Quadrature position/revolution counter

0x4002_7000 0x4002_7FFF A/D converter

0x4002_8000 0x4002_DFFF Reserved

0x4002_E000 0x4002_EFFF Internal CR trimming

0x4002_F000 0x4002_FFFF Reserved

0x4003_0000 0x4003_0FFF

APB2

External interrupt controller

0x4003_1000 0x4003_1FFF Interrupt request batch-read function


0x4003_3000 0x4003_3FFF D/A converter

0x4003_4000 0x4003_4FFF HDMI-CEC

0x4003_5000 0x4003_57FF Low voltage detector

0x4003_5800 0x4003_5FFF Deep standby mode Controller

0x4003_6000 0x4003_6FFF USB clock generator

0x4003_7000 0x4003_7FFF CAN prescaler

0x4003_8000 0x4003_8FFF Multi-function serial interface

0x4003_9000 0x4003_9FFF CRC

0x4003_A000 0x4003_AFFF Watch counter

0x4003_B000 0x4003_BFFF RTC/port control

0x4003_C000 0x4003_C0FF Low-speed CR prescaler

0x4003_C100 0x4003_C7FF Peripheral clock gating

0x4003_C800 0x4003_CFFF Reserved

0x4003_D000 0x4003_DFFF I2S prescaler

0x4003_E000 0x4003_EFFF Reserved

0x4003_F000 0x4003_FFFF External memory interface



Start Address End Address Bus Peripherals

0x4004_0000 0x4004_FFFF

AHB

USB ch 0

0x4005_0000 0x4005_FFFF USB ch 1

0x4006_0000 0x4006_0FFF DMAC register

0x4006_1000 0x4006_1FFF DSTC register

0x4006_2000 0x4006_2FFF CAN ch 0

0x4006_3000 0x4006_3FFF CAN ch 1

0x4006_4000 0x4006_5FFF Ethernet-MAC ch 0

0x4006_6000 0x4006_6FFF Ethernet-MAC setting register

0x4006_7000 0x4006_BFFF Reserved

0x4006_C000 0x4006_CFFF I2S

0x4006_D000 0x4006_DFFF Reserved

0x4006_E000 0x4006_EFFF SD card I/F

0x4006_F000 0x4006_FFFF GPIO

0x4007_0000 0x4007_FFFF CAN-FD (CAN ch 2)

0x4008_0000 0x4008_0FFF Programmable-CRC

0x4008_1000 0x41FF_FFFF Reserved

0x200E_0000 0x200E_FFFF Workflash I/F register

0xD000_0000 0xDFFF_FFFF High-speed quad SPI control register



13. Pin Status In Each CPU State

The terms used for pin status have the following meanings:

INITX = 0

This is the period when the INITX pin is at the "L" level.

INITX = 1

This is the period when the INITX pin is at the "H" level.

SPL = 0

This is the status that the standby pin level setting bit (SPL) in the standby mode control register

(STB_CTL) is set to "0."

SPL = 1

This is the status that the standby pin level setting bit (SPL) in the standby mode control register

(STB_CTL) is set to "1."

Input enabled

Indicates that the input function can be used.

Internal input fixed at 0

This is the status that the input function cannot be used. Internal input is fixed at "L."

Hi-Z

Indicates that the pin drive transistor is disabled and the pin is put in the Hi-Z state.

Setting disabled

Indicates that the setting is disabled.

Maintain previous state

Maintains the state that was immediately prior to entering the current mode.

If a built-in peripheral function is operating, the output follows the peripheral function.

If the pin is being used as a port, that output is maintained.

Analog input is enabled

Indicates that the analog input is enabled.

Trace output

Indicates that the trace function can be used.

GPIO selected

In Deep standby mode, pins switch to the general-purpose I/O port.

Setting prohibition

Prohibition of a setting by specification limitation



List of Pin Behavior By Mode State

Pin

Sta

tus

Typ

e

Function

Group

Power-On

Reset or

Low-

Voltage

Detection

State

INITX

Input

State

Device

Internal

Reset

State

Run Mode

or Sleep

Mode State

Timer Mode,

RTC Mode, or

Stop Mode State

Deep Standby RTC

Mode or Deep Standby

Stop Mode State

Return From

Deep

Standby

Mode State

Power

Supply

Unstable

Power Supply

Stable

Power

Supply

Stable

Power Supply

Stable

Power Supply

Stable

Power

Supply

Stable

‐ INITX=0 INITX=1 INITX=1 INITX=1 INITX=1 INITX=1

‐ ‐ ‐ ‐ SPL=0 SPL=1 SPL=0 SPL=1 -

A

GPIO

selected

Setting

disabled

Setting

disabled

Setting

disabled

Maintain

previous

state

Maintain

previous

state

Hi-Z/internal

input fixed

at 0

GPIO

selected,

internal

input fixed

at 0

Hi-Z/internal

input fixed

at 0

GPIO

selected

Main crystal

oscillator

input pin/

external main

clock input

selected

Input

enabled

Input

enabled

Input

enabled

Input

enabled

Input

enabled

Input

enabled

Input

enabled

Input

enabled

Input

Enabled

B

GPIO

selected

Setting

disabled

Setting

disabled

Setting

disabled

Maintain

previous

state

Maintain

previous

state

Hi-Z/internal

input fixed

at 0

GPIO

selected,

internal

input fixed

at 0

Hi-Z/internal

input fixed

at 0

GPIO

selected

External main

clock input

selected

Setting

disabled

Setting

disabled

Setting

disabled

Maintain

previous

state

Maintain

previous

state

Hi-Z/internal

input fixed

at 0

Maintain

previous

state

Hi-Z/internal

input fixed

at 0

Maintain

previous

State

Main crystal

oscillator

output pin

Hi-Z/

internal

input fixed

at 0/

or input

enable

Hi-Z/

internal

input

fixed

at 0

Hi-Z/

internal

input

fixed

at 0

Maintain previous state while oscillator active/

When oscillation stops*1, it will be Hi-Z/

Internal input fixed at 0

C INITX

input pin

Pull-up/

input

enabled

Pull-up/

Input

enabled

Pull-up/

Input

enabled

Pull-up/

Input

enabled

Pull-up/

Input

enabled

Pull-up/

Input

enabled

Pull-up/

Input

enabled

Pull-up/

Input

enabled

Pull-up/

Input

enabled

D Mode

input pin

Input

enabled

Input

enabled

Input

enabled

Input

enabled

Input

enabled

Input

enabled

Input

enabled

Input

enabled

Input

enabled

E

Mode

input pin

Input

enabled

Input

enabled

Input

enabled

Input

enabled

Input

enabled

Input

enabled

Input

enabled

Input

enabled

Input

enabled

GPIO

selected

Setting

disabled

Setting

disabled

Setting

disabled

Maintain

previous

state

Maintain

previous

state

Hi-Z/

input

enabled

GPIO

selected

Hi-Z/

input

enabled

GPIO

selected



Pin

Sta

tus

Typ

e

Function

Group

Power-On

Reset or

Low-

Voltage

Detection

State

INITX

Input

State

Device

Internal

Reset

State

Run Mode

or Sleep

Mode State

Timer Mode,

RTC Mode, or

Stop Mode State

Deep Standby RTC


Stop Mode State

Return From

Deep

Standby

Mode State

Power

Supply

Unstable

Power Supply

Stable

Power

Supply

Stable

Power Supply

Stable

Power Supply

Stable

Power

Supply

Stable


‐ ‐ ‐ ‐ SPL=0 SPL=1 SPL=0 SPL=1 -

F

NMIX

selected

Setting

disabled

Setting

disabled

Setting

disabled

Maintain

previous

state

Maintain

previous

state

Maintain

previous

state

WKUP

input

enabled

Hi-Z/

WKUP

input enabled

Maintain

previous

state

Resource

other than

above

selected Hi-Z

Hi-Z/

input

enabled

Hi-Z/

input

enabled

Hi-Z/

internal

input fixed

at 0

GPIO

selected

GPIO

selected

G

JTAG

selected Hi-Z

Pull-up/

input

enabled

Pull-up/

input

enabled Maintain

previous

state

Maintain

previous

state

Maintain

previous

state

Maintain

previous

state

Maintain

previous

state

Maintain

previous

state

GPIO

selected

Setting

disabled

Setting

disabled

Setting

disabled

Hi-Z/

internal

input fixed

at 0

GPIO

selected,

internal

input fixed

at 0

Hi-Z/

internal input

fixed

at 0

GPIO

selected

H

JTAG

selected Hi-Z

Pull-up/

input

enabled

Pull-up/

input

enabled

Maintain

previous

state

Maintain

previous

state

Maintain

previous

state

Maintain

previous

state

Maintain

previous

state

Maintain

previous

state

Resource

other than

above

selected

Setting

disabled

Setting

disabled

Setting

disabled

Hi-Z/Internal

input fixed

at 0

GPIO

selected,

internal

input fixed

at 0

Hi-Z/Internal

input fixed

at 0

GPIO

selected

GPIO

selected

I

Resource

selected

Hi-Z

Hi-Z/

input

enabled

Hi-Z/

input

enabled

Maintain

previous

state

Maintain

previous

state

Hi-Z/Internal

input fixed

at 0

GPIO

selected,

internal

input fixed

at 0

Hi-Z/internal

input fixed

at 0

GPIO

selected GPIO

selected



Pin

Sta

tus

Typ

e

Function

Group

Power-On

Reset or

Low-

Voltage

Detection

State

INITX

Input

State

Device

Internal

Reset

State

Run Mode

or Sleep

Mode State

Timer Mode,

RTC Mode, or

Stop Mode State

Deep Standby RTC


Stop Mode State

Return From

Deep

Standby

Mode State

Power

Supply

Unstable

Power Supply

Stable

Power

Supply

Stable

Power Supply

Stable

Power Supply

Stable

Power

Supply

Stable


‐ ‐ ‐ ‐ SPL=0 SPL=1 SPL=0 SPL=1 -

J

Analog

output

selected

Hi-Z

Hi-Z/

input

enabled

Hi-Z/

input

enabled

Maintain

previous

state

*2 *3

GPIO

selected,

internal

input fixed

at 0

Hi-Z/internal

input fixed

at 0

GPIO

selected

External

interrupt

enable

selected Maintain

previous

state

Maintain

previous

state

Resource

other than

above

selected

Hi-Z/internal

input fixed

at 0 GPIO

selected

K

External

interrupt

enable

selected

Setting

disabled

Setting

disabled

Setting

disabled

Maintain

previous

state

Maintain

previous

state

Maintain

previous

state GPIO

selected,

internal

input fixed

at 0

Hi-Z/internal

input fixed

at 0

GPIO

selected

Resource

other than

above

selected Hi-Z

Hi-Z/

input

enabled

Hi-Z/

input

enabled

Hi-Z/internal

input fixed

at 0 GPIO

selected

L

Analog input

selected Hi-Z

Hi-Z/

internal

input

fixed at

0/

analog

input

enabled

Hi-Z/

internal

input

fixed at

0/

analog

input

enabled

Hi-Z/

internal input

fixed

at 0/

analog

input enabled

Hi-Z/

internal

input fixed

at 0/

analog

input

enabled

Hi-Z/

internal input

fixed

at 0/

analog

input enabled

Hi-Z/

internal

input fixed

at 0/

analog

input

enabled

Hi-Z/

internal input

fixed

at 0/

analog

input enabled

Hi-Z/

internal input

fixed

at 0/

analog

input

enabled

Resource

other than

above

selected

Setting

disabled

Setting

disabled

Setting

disabled

Maintain

previous

state

Maintain

previous

state

Hi-Z/internal

input fixed

at 0

GPIO

selected,

internal

input fixed

at 0

Hi-Z/internal

input fixed

at 0

GPIO

selected

GPIO

selected



Pin

Sta

tus

Typ

e

Function

Group

Power-On

Reset or

Low-

Voltage

Detection

State

INITX

Input

State

Device

Internal

Reset

State

Run Mode

or Sleep

Mode State

Timer Mode,

RTC Mode, or

Stop Mode State

Deep Standby RTC


Stop Mode State

Return From

Deep

Standby

Mode State

Power

Supply

Unstable

Power Supply

Stable

Power

Supply

Stable

Power Supply

Stable

Power Supply

Stable

Power

Supply

Stable


‐ ‐ ‐ ‐ SPL=0 SPL=1 SPL=0 SPL=1 -

M

Analog input

selected Hi-Z

Hi-Z/

internal

input

fixed

at 0/

analog

input

enabled

Hi-Z/

internal

input

fixed

at 0/

analog

input

enabled

Hi-Z/

internal input

fixed

at 0/

analog

input enabled

Hi-Z/

internal

input fixed

at 0/

analog

input

enabled

Hi-Z/

internal input

fixed

at 0/

analog

input enabled

Hi-Z/

internal

input fixed

at 0/

analog

input

enabled

Hi-Z/

internal input

fixed

at 0/

analog

input enabled

Hi-Z/

internal input

fixed

at 0/

analog

input

enabled

External

interrupt

enable

selected

Setting

disabled

Setting

disabled

Setting

disabled

Maintain

previous

state

Maintain

previous

state

Maintain

previous

state GPIO

selected,

internal

input fixed

at 0

Hi-Z/internal

input fixed

at 0

GPIO

selected

Resource

other than

above

selected

Hi-Z/internal

input fixed

at 0 GPIO

selected

N

Analog input

selected Hi-Z

Hi-Z/

internal

input

fixed

at0/

analog

input

enabled

Hi-Z/

internal

input

fixed

at 0/

analog

input

enabled

Hi-Z/

internal input

fixed

at 0/

analog

input enabled

Hi-Z/

internal

input fixed

at 0/

analog

input

enabled

Hi-Z/

internal input

fixed

at 0/

analog

input enabled

Hi-Z/

internal

input fixed

at 0/

analog

input

enabled

Hi-Z/

internal input

fixed

at 0/

analog

input enabled

Hi-Z/

internal input

fixed

at 0/

analog

input

enabled

Trace

selected

Setting

disabled

Setting

disabled

Setting

disabled

Maintain

previous

state

Maintain

previous

state

Trace

output GPIO

selected,

internal

input fixed

at 0

Hi-Z/internal

input fixed

at 0

GPIO

selected

Resource

other than

above

selected

Hi-Z/internal

input fixed

at 0 GPIO

selected



Pin

Sta

tus

Typ

e

Function

Group

Power-On

Reset or

Low-

Voltage

Detection

State

INITX

Input

State

Device

Internal

Reset

State

Run Mode

or Sleep

Mode State

Timer Mode,

RTC Mode, or

Stop Mode State

Deep Standby RTC


Stop Mode State

Return From

Deep

Standby

Mode State

Power

Supply

Unstable

Power Supply

Stable

Power

Supply

Stable

Power Supply

Stable

Power Supply

Stable

Power

Supply

Stable


‐ ‐ ‐ ‐ SPL=0 SPL=1 SPL=0 SPL=1 -

O

Analog input

selected Hi-Z

Hi-Z/

internal

input

fixed

at 0/

analog

input

enabled

Hi-Z/

internal

input

fixed

at 0/

analog

input

enabled

Hi-Z/

internal input

fixed

at 0/

analog

input enabled

Hi-Z/

internal

input fixed

at 0/

analog

input

enabled

Hi-Z/

internal input

fixed

at 0/

analog

input enabled

Hi-Z/

internal

input fixed

at 0/

analog

input

enabled

Hi-Z/

internal input

fixed

at 0/

analog

input enabled

Hi-Z/

internal input

fixed

at 0/

analog

input

enabled

Trace

selected

Setting

disabled

Setting

disabled

Setting

disabled

Maintain

previous

state

Maintain

previous

state

Trace

output

GPIO

selected,

internal

input fixed

at 0

Hi-Z/internal

input fixed

at 0

GPIO

selected

External

interrupt

enable

selected

Maintain

previous

state

Resource

other than

above

selected

Hi-Z/internal

input fixed

at 0 GPIO

selected

P

Analog input

selected Hi-Z

Hi-Z/

internal

input

fixed at

0/

analog

input

enabled

Hi-Z/

internal

input

fixed at

0/

analog

input

enabled

Hi-Z/

internal input

fixed

at 0/

analog

input enabled

Hi-Z/

internal

input fixed

at 0/

analog

input

enabled

Hi-Z/

internal input

fixed

at 0/

analog

input enabled

Hi-Z/

internal

input fixed

at 0/

analog

input

enabled

Hi-Z/

internal input

fixed

at 0/

analog

input enabled

Hi-Z/

internal input

fixed

at 0/

analog

input

enabled

WKUP

enabled

Setting

disabled

Setting

disabled

Setting

disabled

Maintain

previous

state

Maintain

previous

state

Maintain

previous

state

WKUP

input

enabled

Hi-Z/

WKUP input

enabled

GPIO

selected

Resource

other than

above

selected

Hi-Z/internal

input fixed

at 0

GPIO

selected,

internal

input fixed

at 0

Hi-Z/internal

input fixed

at 0 GPIO

selected



Pin

Sta

tus

Typ

e

Function

Group

Power-On

Reset or

Low-

Voltage

Detection

State

INITX

Input

State

Device

Internal

Reset

State

Run Mode

or Sleep

Mode State

Timer Mode,

RTC Mode, or

Stop Mode State

Deep Standby RTC


Stop Mode State

Return From

Deep

Standby

Mode State

Power

Supply

Unstable

Power Supply

Stable

Power

Supply

Stable

Power Supply

Stable

Power Supply

Stable

Power

Supply

Stable


‐ ‐ ‐ ‐ SPL=0 SPL=1 SPL=0 SPL=1 -

Q

WKUP

enabled

Setting

disabled

Setting

disabled

Setting

disabled

Maintain

previous

state

Maintain

previous

state

Maintain

previous

state

WKUP input

enabled

Hi-Z/

WKUP

input enabled

WKUP input

enabled

External

interrupt

enable

selected GPIO

selected,

internal

input fixed

at 0

Hi-Z/internal

input fixed

at 0

GPIO

selected

Resource

other than

above

selected Hi-Z

Hi-Z/

input

enabled

Hi-Z/

input

enabled

Hi-Z/internal

input fixed

at 0 GPIO

selected

R

GPIO

selected Hi-Z

Hi-Z/

input

enabled

Hi-Z/

input

enabled

Maintain

previous

state

Maintain

previous

state

Hi-Z/internal

input fixed

at 0

GPIO

selected,

internal

input fixed

at 0

Hi-Z/internal

input fixed

at 0

GPIO

selected

USB I/O pin Setting

disabled

Setting

disabled

Setting

disabled

Hi-Z at

trans-

mission/

input

enabled/

internal input

fixed

at 0 at

reception

Hi-Z at

trans-

mission/

input

enabled/

internal

input fixed

at 0 at

reception

Hi-Z at

trans-

mission/

input

enabled/

internal input

fixed

at 0 at

reception

Hi-Z/

input

enabled

Hi-Z/

input enabled

Hi-Z/

input enabled

V

Ethernet I/O

selected

*4

Setting

disabled

Setting

disabled

Setting

disabled

Maintain

previous

state

Maintain

previous

state

Maintain

previous

state GPIO

selected,

internal

input fixed

at 0

Hi-Z/internal

input fixed

at "0

GPIO

selected

Resource

other than

above

selected Hi-Z

Hi-Z/

input

enabled

Hi-Z/

input

enabled

Hi-Z/internal

input fixed

at 0 GPIO

selected



Pin

Sta

tus

Typ

e

Function

Group

Power-On

Reset or

Low-

Voltage

Detection

State

INITX

Input

State

Device

Internal

Reset

State

Run Mode

or Sleep

Mode State

Timer Mode,

RTC Mode, or

Stop Mode State

Deep Standby RTC


Stop Mode State

Return From

Deep

Standby

Mode State

Power

Supply

Unstable

Power Supply

Stable

Power

Supply

Stable

Power Supply

Stable

Power Supply

Stable

Power

Supply

Stable


‐ ‐ ‐ ‐ SPL=0 SPL=1 SPL=0 SPL=1 -

W

Ethernet

input/output

selected*4

Setting

disabled

Setting

disabled

Setting

disabled

Maintain

previous

state

Maintain

previous

state

Maintain

previous

state GPIO

selected,

internal

input fixed

at 0

Hi-Z/internal

input fixed

at 0

GPIO

selected

External

interrupt

enable

selected

Resource

other than

above

selected Hi-Z

Hi-Z/

input

enabled

Hi-Z/

input

enabled

Hi-Z/internal

input fixed

at 0 GPIO

selected

X

CEC enabled

Setting

disabled

Setting

disabled

Setting

disabled

Maintain

previous

state

Maintain

previous

state

Maintain

previous

state

Maintain

previous

state

Maintain

previous

state

Maintain

previous

state

External

interrupt

enable

selected GPIO

selected,

internal

input fixed

at 0

Hi-Z/internal

input fixed

at 0

GPIO

selected

Resource

other than

above

selected Hi-Z

Hi-Z/

input

enabled

Hi-Z/

input

enabled

Hi-Z/internal

input fixed

at 0 GPIO

selected



Pin

Sta

tus

Typ

e

Function

Group

Power-On

Reset or

Low-

Voltage

Detection

State

INITX

Input

State

Device

Internal

Reset

State

Run Mode

or Sleep

Mode State

Timer Mode,

RTC Mode, or

Stop Mode State

Deep Standby RTC


Stop Mode State

Return From

Deep

Standby

Mode State

Power

Supply

Unstable

Power Supply

Stable

Power

Supply

Stable

Power Supply

Stable

Power Supply

Stable

Power

Supply

Stable


‐ ‐ ‐ ‐ SPL=0 SPL=1 SPL=0 SPL=1 -

Y

CEC enabled

Setting

disabled

Setting

disabled

Setting

disabled

Maintain

previous

state

Maintain

previous

state

Maintain

previous

state

Maintain

previous

state

Maintain

previous

state

Maintain

previous

state

WKUP

enabled

WKUP

input

enabled

Hi-Z/

WKUP

input enabled

GPIO

selected

External

interrupt

enable

selected GPIO

selected,

internal

input fixed

at 0

Hi-Z/internal

input fixed

at 0

Resource

other than

above

selected Hi-Z

Hi-Z/

input

enabled

Hi-Z/

input

enabled

Hi-Z/internal

input fixed

at 0 GPIO

selected

1: Oscillation is stopped at sub timer mode, sub CR timer mode, RTC mode, Stop mode, Deep standby RTC mode,

and Deep standby Stop mode.

2: Maintain previous state at timer mode. GPIO selected internal input fixed at 0 at RTC mode, Stop mode.

3: Maintain previous state at timer mode. Hi-Z/internal input fixed at 0 at RTC mode, Stop mode.

4: It shows the case selected by EPFR14.E_SPLC register.



List of VBAT Domain Pin Status

VB

AT

Pin

Sta

tus

Typ

e

Function

Group

VBAT

Power-

On

Reset

INITX

Input

State

Device

Internal

Reset

State

Run

Mode or

Sleep

Mode

State

Timer Mode,

RTC Mode, or

Stop Mode State

Deep Standby

RTC Mode or Deep

Standby Stop Mode

State

Return

From

Deep

Standby

Mode

State

VBAT

RTC

Mode

State

Return

From

VBAT

RTC

Mode

State

Power

Supply

Unstable

Power Supply

Stable

Power

Supply

Stable

Power Supply Stable Power Supply Stable

Power

Supply

Stable

Power

Supply

Stable

Power

Supply

Stable

‐ INITX=0 INITX=1 INITX=1 INITX=1 INITX=1 INITX=1 - -

‐ ‐ ‐ ‐ SPL=0 SPL=1 SPL=0 SPL=1 - - -

S

GPIO

selected

Setting

disabled

Maintain

previous

state

Maintain

previous

state

Maintain

previous

state

Maintain

previous

state

Maintain

previous

state

Maintain

previous

state

Maintain

previous

state

Maintain

previous

state

Setting

prohibition -

Sub

crystal

oscillator

input pin/

external

sub clock

input

selected

Input

enabled

Input

enabled

Input

enabled

Input

enabled

Input

enabled

Input

enabled

Input

enabled

Input

enabled

Input

enabled

Maintain

previous

state

Maintain

previous

state

T

GPIO

selected

Setting

disabled

Maintain

previous

state

Maintain

previous

state

Maintain

previous

state

Maintain

previous

state

Maintain

previous

state

Maintain

previous

state

Maintain

previous

state

Maintain

previous

state

Setting

prohibition -

External

sub clock

input

selected

Setting

disabled

Maintain

previous

state

Maintain

previous

state

Maintain

previous

state

Maintain

previous

state

Maintain

previous

state

Maintain

previous

state

Maintain

previous

state

Maintain

previous

state

Maintain

previous

state

Maintain

previous

state

Sub

crystal

oscillator

output pin

Hi-Z/

internal

input

fixed at 0/

or input

enable

Maintain

previous

state

Maintain

previous

state

Maintain

previous

state

Maintain

previous

state/

When

oscillation

stops,

Hi-Z*

Maintain

previous

state/

When

oscillation

stops,

Hi-Z*

Maintain

previous

state/

When

oscillation

stops,

Hi-Z*

Maintain

previous

state/

When

oscillation

stops,

Hi-Z*

Maintain

previous

state

Maintain

previous

state

Maintain

previous

state

U

Resource

selected

Hi-Z

Maintain

previous

state

Maintain

previous

state

Maintain

previous

state

Maintain

previous

state

Maintain

previous

state

Maintain

previous

state

Maintain

previous

state

Maintain

previous

state

Maintain

previous

state

Maintain

previous

state GPIO

selected

*: When the SOSCNTL bit in the WTOSCCNT register is 0, the sub crystal oscillator output pin is maintained in the

previous state. When the SOSCNTL bit in the WTOSCCNT register is 1, oscillation is stopped at Stop mode and Deep

standby Stop mode



14. Electrical Characteristics

14.1 Absolute Maximum Ratings

Parameter Symbol Rating

Unit Remarks Min Max

Power supply voltage*1,*2

VCC VSS - 0.5 VSS + 6.5 V

Power supply voltage (for USB) *1,*3

USBVCC0 VSS - 0.5 VSS + 6.5 V

Power supply voltage (for USB) *1,*3

USBVCC1 VSS - 0.5 VSS + 6.5 V

Power supply voltage (for Ethernet-MAC) *1, *4

ETHVCC VSS - 0.5 VSS + 6.5 V

Power supply voltage (VBAT) *1 ,*5

VBAT VSS - 0.5 VSS + 6.5 V

Analog power supply voltage *1 ,*6

AVCC VSS - 0.5 VSS + 6.5 V

Analog reference voltage *1 ,*6

AVRH VSS - 0.5 VSS + 6.5 V

Input voltage *1

VI

VSS - 0.5 VCC + 0.5

(≤ 6.5V) V

Except for USB and

Ethernet-MAC pin

VSS - 0.5 USBVCC0 + 0.5

(≤ 6.5V) V USB ch 0 pin

VSS - 0.5 USBVCC1 + 0.5

(≤ 6.5V) V USB ch 1 pin

VSS - 0.5 ETHVCC + 0.5

(≤ 6.5V) V Ethernet-MAC Pin

VSS - 0.5 VSS + 6.5 V 5V tolerant

Analog pin input voltage *1

VIA VSS - 0.5 AVCC + 0.5

(≤ 6.5V) V

Output voltage *1

VO VSS - 0.5 VCC + 0.5

(≤ 6.5V) V

"L" level maximum output current *7 IOL -

10 mA 4 mA type

20 mA 8 mA type

20 mA 12 mA type

22.4 mA I2C Fm+

"L" level average output current *8

IOLAV -

4 mA 4 mA type

8 mA 8 mA type

12 mA 12 mA type

20 mA I2C Fm+

"L" level total maximum output current ∑IOL - 100 mA

"L" level total maximum output current*9

∑IOLAV - 50 mA

"H" level maximum output current *7

IOH -

- 10 mA 4 mA type

-20 mA 8 mA type

- 20 mA 12 mA type

"H" level average output current *8

IOHAV -

- 4 mA 4 mA type

-8 mA 8 mA type

- 12 mA 12 mA type

"H" level total maximum output current ∑IOH - - 100 mA

"H" level total average output current *9

∑IOHAV - - 50 mA

Power consumption PD - 200 mW

Storage temperature TSTG - 55 + 150 °C

1: These parameters are based on the condition that VSS = AVSS = 0.0V.

2: VCC must not drop below VSS - 0.5V.

3: USBVCC0, USBVCC1 must not drop below VSS - 0.5V.

4: ETHVCC must not drop below VSS - 0.5V.

5: VBAT must not drop below VSS - 0.5V.



6: Ensure that the voltage does not exceed VCC + 0.5V, for example, when the power is turned on.

7: The maximum output current is defined as the value of the peak current flowing through any one of the corresponding

pins.

8: The average output current is defined as the average current value flowing through any one of the corresponding pins

for a 100-ms period.

9: The total average output current is defined as the average current value flowing through all of corresponding pins for a

100-ms period.

WARNING:

− Semiconductor devices may be permanently damaged by application of stress (including, without

limitation, voltage, current or temperature) in excess of absolute maximum ratings. Do not exceed

any of these ratings.



14.2 Recommended Operating Conditions

Parameter Symbol Conditions Value


Power supply voltage VCC - 2.7 *9

5.5 V

Power supply voltage (for USB ch 0) USBVCC0 -

3.0 3.6

( ≤VCC) V

*1

2.7 5.5

( ≤VCC) *2

Power supply voltage (for USB ch 1) USBVCC1 -

3.0 3.6

( ≤VCC) V

*3

2.7 5.5

( ≤VCC) *4

Power supply voltage (for Ethernet-MAC) ETHVCC -

3.0 3.6

( ≤VCC)

V

*5

4.5 5.5

( ≤VCC) *5

2.7 5.5

( ≤VCC) *6

Power supply voltage (VBAT) VBAT - 1.65 5.5 V

Analog power supply voltage AVCC - 2.7 5.5 V AVCC = VCC

Analog reference voltage AVRH - *8 AVCC V

Operating

temperature

Junction temperature Tj - 40 + 125 °C

Ambient temperature Ta -40 *7 °C

1: When P81/UDP0 and P80/UDM0 pins are used as USB (UDP0, UDM0)

2: When P81/UDP0 and P80/UDM0 pins are used as GPIO (P81, P80)

3: When P83/UDP1 and P82/UDM1 pins are used as USB (UDP1, UDM1)

4: When P83/UDP1 and P82/UDM1 pins are used as GPIO (P83, P82)

5: When the pins in "Ethernet-MAC Pins," except P6E/ADTG_5/SCK4_1/IC23_1/INT29_0/E_PPS pin, are used

as Ethernet-MAC pin

6: When the pins in "Ethernet-MAC Pins," except P6E/ADTG_5/SCK4_1/IC23_1/INT29_0/E_PPS pin, are used

as Ethernet-MAC pin

7: The maximum temperature of the ambient temperature (Ta) can guarantee a range that does not exceed the

junction temperature (Tj).

The calculation formula of the ambient temperature (Ta) is:

Ta (Max) = Tj(Max) - Pd(Max) × θja

Pd : Power dissipation (W)

θja : Package thermal resistance (°C/W)

Pd (Max) = VCC × ICC (Max) + Σ (IOL×VOL) + Σ ((VCC-VOH) × (- IOH))

IOL : "L" level output current

IOH : "H" level output current

VOL : "L" level output voltage

VOH : "H" level output voltage

8: The minimum value of analog reference voltage depends on the value of compare clock cycle (Tcck). See "14.5.

12-bit A/D Converter" for the details.

9: For the voltage range between Vcc(min) and the low voltage detection reset (VDH), the MCU must be clocked from

either the high-speed CR or the low-speed CR.”



Package thermal resistance and maximum permissible power for each package are shown below.

The operation is guaranteed maximum permissible power or less for semiconductor devices.

Table 14-1 Table For Package Thermal Resistance and Maximum Permissible Power

Package Printed

Circuit Board

Thermal

Resistance

θja

(°C/W)

Maximum Permissible Power

(mW)

Ta = +85°C Ta = +105°C

FPT-144P-M08

(0.5-mm pitch)

Single-layered

both sides 48 833 417

4 layers 33 1212 606

FPT-176P-M07

(0.5-mm pitch)

Single-layered


4 layers 31 1290 645

FPT-216P-M01

(0.4-mm pitch)

Single-layered


4 layers 32 1250 625

LBE192

(0.8-mm pitch)

Single-layered

both sides - - -

4 layers 35 1143 571

WARNING:

1. The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device's electrical characteristics are warranted when the device is

operated within these ranges.

2. Always use semiconductor devices within their recommended operating condition ranges. Operation

outside these ranges may adversely affect reliability and could result in device failure.

3. No warranty is made with respect to uses, operating conditions, or combinations not represented on the

data sheet.

4. Users considering application outside the listed conditions are advised to contact their representatives

beforehand.



Ethernet-MAC Pins

Pin Name Ethernet-MAC

Function

Except For

Ethernet-MAC

Function

Power

Supply

Type

P6E/ADTG_5/SCK4_1/IC23_1/INT29_0/E_PPS E_PPS * P6E/ADTG_5/SCK4_1/IC23_1/INT29_0 VCC

PC0/E_RXER E_RX03 PC0

ETHVCC

PC1/TIOB6_0/E_RX03 E_RX02 PC1/TIOB6_0

PC2/TIOA6_0/E_RX02 E_RX01 PC2/TIOA6_0

PC3/TIOB7_0/E_RX01 E_RX00 PC3/TIOB7_0

PC4/TIOA7_0/E_RX00 E_RXDV PC4/TIOA7_0

PC5/TIOB14_0/E_RXDV E_MDIO PC5/TIOB14_0

PC6/TIOA14_0/E_MDIO E_MDC PC6/TIOA14_0

PC7/INT13_0/E_MDC/CROUT_1 E_RXCK_REFCK PC7/INT13_0/CROUT_1

PC8/E_RXCK_REFCK E_COL PC8

PC9/TIOB15_0/E_COL E_CRS PC9/TIOB15_0

PCA/TIOA15_0/E_CRS E_COUT PCA/TIOA15_0

PCB/INT28_0/E_COUT E_TCK PCB/INT28_0

PCC/E_TCK E_TXER PCC

PCD/SOT4_1/INT14_0/E_TXER E_TX03 PCD/SOT4_1/INT14_0

PCE/SIN4_1/INT15_0/E_TX03 E_TX02 PCE/SIN4_1/INT15_0

PCF/RTS4_1/INT12_0/E_TX02 E_TX01 PCF/RTS4_1/INT12_0

PD0/INT30_1/E_TX01 E_TX00 PD0/INT30_1

PD1/INT31_1/E_TX00 E_TXEN PD1/INT31_1

PD2/CTS4_1/FRCK2_1/E_TXEN E_RX03 PD2/CTS4_1/FRCK2_1

*: It is used to confirm the PTP counter cycle in Ethernet-MAC by waveforms.



Calculation Method of Power Dissipation (Pd)

The power dissipation is shown in the following formula.

Pd = VCC × ICC + Σ (IOL × VOL) + Σ ((VCC-VOH) × (-IOH))

IOL: "L" level output current

IOH: "H" level output current

VOL: "L" level output voltage

VOH: "H" level output voltage

ICC is the current drawn by the device.

It can be analyzed as follows.

ICC = ICC (INT) + ΣICC (IO)

ICC (INT): Current drawn by internal logic and memory, etc. through the regulator

ΣICC (IO): Sum of current (I/O switching current) drawn by the output pin

For ICC (INT), it can be anticipated by "(1) Current Rating" in "14.3. DC Characteristics" (This rating value

does not include ICC (IO) for a value at pin fixed).

For Icc (IO), it depends on system used by customers.

The calculation formula is shown below.

ICC (IO) = (CINT + CEXT) × VCC × fsw

CINT: Pin internal load capacitance

CEXT: External load capacitance of output pin

fSW: Pin switching frequency

Parameter Symbol Conditions Capacitance Value

Pin internal load capacitance CINT

4 mA type 1.93 pF

8 mA type 3.45 pF

12 mA type 3.42 pF

Calculate ICC (Max) as follows when the power dissipation can be evaluated by yourself:

Measure current value ICC (Typ) at normal temperature (+25°C).

Add maximum leakage current value ICC (leak_max) at operating on a value in (1).

ICC(Max) = ICC (Typ) + ICC (leak_max)

Parameter Symbol Conditions Current Value

Maximum leakage current at

operating ICC (leak_max)

Tj = +125°C TBD

Tj = +105°C TBD

Tj = +85°C TBD



Current Explanation Diagram

A

V

・・・

・・・

・・・

V A

A

Regulator

Logic

Flash

RAM

ICC

ICC (INT)

ΣICC (IO)

IOL

VOL

VOH

IOH

ICC (IO)

Chip

VCC

CEXT

Pd=VCC×ICC + Σ(IOL×VOL)＋Σ((VCC-VOH)×(－IOH))

ICC=ICC (INT)＋ΣICC (IO)



14.3 DC Characteristics

14.3.1 Current Rating

Table 14-2 Typical and maximum current consumption in Normal operation(PLL), code running from Flash memory (Flash accelerator mode and trace buffer function enabled)

Parameter Symbol Pin

Name Conditions Frequency*

4

Value Unit Remarks

Typ*1 Max*

2

Power

supply

current

ICC VCC

Normal

operation

*7,*8

(PLL)

*5

200 MHz 119 180 mA

*3

When all peripheral

clocks are on

192 MHz 115 TBD mA

180 MHz 108 TBD mA

*6

160 MHz 98 TBD mA

144 MHz 89 TBD mA

120 MHz 75 TBD mA

100 MHz 64 TBD mA

80 MHz 52 TBD mA

60 MHz 40 TBD mA

40 MHz 28 TBD mA

20 MHz 16 TBD mA

8 MHz 8.9 TBD mA

4 MHz 6.5 TBD mA

*5

200 MHz 73 TBD mA

*3

When all peripheral

clocks are off

192 MHz 70 TBD mA

180 MHz 66 TBD mA

*6

160 MHz 61 TBD mA

144 MHz 55 TBD mA

120 MHz 47 TBD mA

100 MHz 40 TBD mA

80 MHz 33 TBD mA

60 MHz 26 TBD mA

40 MHz 18 TBD mA

20 MHz 11 TBD mA

8 MHz 6.5 TBD mA

4 MHz 5.1 TBD mA

1: Ta = +25°C, VCC = 3.3V

2: Tj = +125°C, VCC = 5.5V

3: When all ports are fixed

4: Frequency is a value of HCLK when PCLK0 = PCLK1 = PCLK2 = HCLK

5: When stopping flash accelerator mode and trace buffer function (FRWTR.RWT = 11, FBFCR.BE = 1)


7: Firmware being executed during data collection for this table is not being accessed from the MainFlash memory.”

8: When using the crystal oscillator of 4 MHz (including the current consumption of the oscillation circuit)



Table 14-2 Typical and maximum current consumption in Normal operation(PLL), code with data accessing running from Flash memory (Flash accelerator mode and trace buffer function disabled)



4

Value Unit Remarks

Typ*1 Max*

2

Power

supply

current

ICC VCC

Normal

operation

*7,*8

(PLL)

*5

200 MHz 128 220 mA

*3

When all peripheral

clocks are on

192 MHz 123 TBD mA

180 MHz 116 TBD mA

*6

160 MHz 102 TBD mA

144 MHz 93 TBD mA

120 MHz 79 TBD mA

100 MHz 67 TBD mA

80 MHz 54 TBD mA

60 MHz 42 TBD mA

40 MHz 30 TBD mA

20 MHz 17 TBD mA

8 MHz 9.2 TBD mA

4 MHz 6.7 TBD mA

*5

200 MHz 74 TBD mA

*3

When all peripheral

clocks are off

192 MHz 71 TBD mA

180 MHz 67 TBD mA

*6

160 MHz 59 TBD mA

144 MHz 53 TBD mA

120 MHz 45 TBD mA

100 MHz 39 TBD mA

80 MHz 32 TBD mA

60 MHz 25 TBD mA

40 MHz 18 TBD mA

20 MHz 11 TBD mA

8 MHz 6.5 TBD mA

4 MHz 5.1 TBD mA

1: Ta = +25°C, VCC = 3.3V

2: Tj = +125°C, VCC = 5.5V





7: With data access to a MainFlash memory.




Table 14-3 Typical and maximum current consumption in Normal operation(PLL), code with data accessing running from Flash memory (flash 0 wait-cycle mode and read access 0 wait)



4

Value Unit Remarks

Typ*1 Max*

2

Power

supply

current

ICC VCC

Normal

operation

*6,*7

(PLL)

*5

72 MHz 71 TBD mA

*3

When all peripheral

clocks are on

60 MHz 62 TBD mA

48 MHz 51 TBD mA

36 MHz 40 TBD mA

24 MHz 29 TBD mA

12 MHz 17 TBD mA

8 MHz 13 TBD mA

4 MHz 8.4 TBD mA

*5

72 MHz 46 TBD mA

*3

When all peripheral

clocks are off

60 MHz 41 TBD mA

48 MHz 34 TBD mA

36 MHz 27 TBD mA

24 MHz 20 TBD mA

12 MHz 12 TBD mA

8 MHz 9.4 TBD mA

4 MHz 6.5 TBD mA

1: Ta = +25°C, VCC = 3.3V

2: Tj = +125°C, VCC = 5.5V



5: When operating flash 0 wait-cycle mode and read access 0 wait (FRWTR.RWT = 00, FBFCR.SD = 000)





Table 14-4 Typical and maximum current consumption in Normal operation(other than PLL), code with data accessing running from Flash memory (flash 0 wait-cycle mode and read access 0 wait)



4

Value Unit Remarks

Typ*1 Max*

2

Power

supply

current

ICC VCC

Normal

operation

*6

(built-in

high-speed

CR)

*5 4 MHz

3.0 TBD mA

*3

When all peripheral

clocks are on

2.1 TBD mA

*3

When all peripheral

clocks are off

Normal

operation

*6, *7

(sub

oscillation)

*5 32 kHz

0.78 TBD mA

*3

When all peripheral

clocks are on

0.77 TBD mA

*3

When all peripheral

clocks are off

Normal

operation

*6

(built-in

low-speed CR)

*5 100 kHz

0.81 TBD mA

*3

When all peripheral

clocks are on

0.78 TBD mA

*3

When all peripheral

clocks are off

1: Ta = +25°C, VCC = 3.3V

2: Tj = +125°C, VCC = 5.5V


4: Frequency is a value of HCLK when PCLK0 = PCLK1 = PCLK2 = HCLK/2

5: When operating flash 0 wait-cycle mode and read access 0 wait (FRWTR.RWT = 00, FBFCR.SD = 000)


7: When using the crystal oscillator of 32kHz (including the current consumption of the oscillation circuit)



Table 14-5 Typical and maximum current consumption in Sleep operation(PLL), when PCLK0 = PCLK1 = PCLK2 = HCLK/2



4

Value Unit Remarks

Typ*1 Max*

2

Power

supply

current

ICCS VCC

Sleep

operation*5

(PLL)

200 MHz 88 TBD mA

*3

When all peripheral clocks

are on

192 MHz 85 TBD mA

180 MHz 80 TBD mA

160 MHz 72 TBD mA

144 MHz 65 TBD mA

120 MHz 55 TBD mA

100 MHz 47 TBD mA

80 MHz 38 TBD mA

60 MHz 30 TBD mA

40 MHz 21 TBD mA

20 MHz 12 TBD mA

8 MHz 7.4 TBD mA

4 MHz 5.8 TBD mA

200 MHz 44 TBD mA

*3


are off

192 MHz 42 TBD mA

180 MHz 40 TBD mA

160 MHz 36 TBD mA

144 MHz 33 TBD mA

120 MHz 28 TBD mA

100 MHz 24 TBD mA

80 MHz 20 TBD mA

60 MHz 16 TBD mA

40 MHz 12 TBD mA

20 MHz 7.6 TBD mA

8 MHz 5.2 TBD mA

4 MHz 4.4 TBD mA

1: Ta = +25°C, VCC = 3.3V

2: Tj = +125°C, VCC = 5.5V






Table 14-6 Typical and maximum current consumption in Sleep operation(PLL), when PCLK0 = PCLK1 = PCLK2 = HCLK



4

Value Unit Remarks

Typ*1 Max*

2

Power

supply

current

ICCS VCC

Sleep

operation*5

(PLL)

72 MHz 45 TBD mA

*3


are on

60 MHz 38 TBD mA

48 MHz 31 TBD mA

36 MHz 24 TBD mA

24 MHz 18 TBD mA

12 MHz 11 TBD mA

8 MHz 8.6 TBD mA

4 MHz 6.3 TBD mA

72 MHz 20 TBD mA

*3


are off

60 MHz 18 TBD mA

48 MHz 15 TBD mA

36 MHz 12 TBD mA

24 MHz 9.1 TBD mA

12 MHz 6.5 TBD mA

8 MHz 5.5 TBD mA

4 MHz 4.6 TBD mA

1: Ta = +25°C, VCC = 3.3V

2: Tj = +125°C, VCC = 5.5V






Table 14-7 Typical and maximum current consumption in Sleep operation(other than PLL), when PCLK0 = PCLK1 = PCLK2 = HCLK/2



4

Value Unit Remarks

Typ*1 Max*

2

Power

supply

current

ICCS VCC

Sleep

operation

(built-in

high-speed CR)

4 MHz

2.5 TBD mA

*3


are on

1.7 TBD mA

*3


are off

Sleep

operation*5

(sub oscillation)

32 kHz

0.75 TBD mA

*3


are on

0.74 TBD mA

*3


are off

Sleep

operation

(built-in

low-speed CR)

100 kHz

0.79 TBD mA

*3


are on

0.76 TBD mA

*3


are off

1: Ta = +25°C, VCC = 3.3V

2: Tj = +125°C, VCC = 5.5V

3: When all ports are fixed.





Table 14-8 Typical and maximum current consumption in STOP mode, TIMER mode and RTC mode


Name Conditions Frequency

Value Unit Remarks

Typ*1 Max*

2

Power

supply

current

ICCH

VCC

Stop mode -

0.56 TBD mA *3, *4

Ta = +25°C

- TBD mA *3, *4

Ta = +85°C

- TBD mA *3, *4

Ta = +105°C

ICCT

Timer mode

(built-in

high-speed CR)

4 MHz

1.43 TBD mA *3, *4

Ta = +25°C

- TBD mA *3, *4

Ta = +85°C

- TBD mA *3, *4

Ta = +105°C

Timer mode*5

(sub oscillation) 32 kHz

0.57 TBD mA *3, *4

Ta = +25°C

- TBD mA *3, *4

Ta = +85°C

- TBD mA *3, *4

Ta = +105°C

Timer mode

(built-in

low-speed CR)

100 kHz

0.58 TBD mA *3, *4

Ta = +25°C

- TBD mA *3, *4

Ta = +85°C

- TBD mA *3, *4

Ta = +105°C

ICCR RTC mode

*5

(sub oscillation) 32 kHz

0.57 TBD mA *3, *4

Ta = +25°C

- TBD mA *3, *4

Ta = +85°C

- TBD mA *3, *4

Ta = +105°C

1: VCC = 3.3V

2: VCC = 5.5V


4: When LVD is off




Table 14-9 Typical and maximum current consumption in Deep Standby STOP mode, Deep Standby RTC mode and VBAT


Name Conditions Frequency

Value Unit Remarks

Typ*1 Max*

2

Power

supply

current

ICCHD

VCC

Deep standby

Stop mode

(When RAM

is off)

-

96 TBD μA *3, *4

Ta = +25°C

- TBD μA *3, *4

Ta = +85°C

- TBD μA *3, *4

Ta = +105°C

Deep standby

Stop mode

(When RAM

is on)

-

106 TBD μA *3, *4

Ta = +25°C

- TBD μA *3, *4

Ta = +85°C

- TBD μA *3, *4

Ta = +105°C

ICCRD

Deep standby

RTC mode*6

(When RAM

is off)

32 kHz

96 TBD μA *3, *4

Ta = +25°C

- TBD μA *3, *4

Ta = +85°C

- TBD μA *3, *4

Ta = +105°C

Deep standby

RTC mode*6

(When RAM

is on)

106 TBD μA *3, *4

Ta = +25°C

- TBD μA *3, *4

Ta = +85°C

- TBD μA *3, *4

Ta = +105°C

ICCVBAT VBAT

RTC stop

-

7 TBD nA *3, *4, *5

Ta = +25°C

- TBD μA *3, *4, *5

Ta = +85°C

- TBD μA *3, *4, *5

Ta = +105°C

RTC

operation*6

1.0 TBD μA *3, *4

Ta = +25°C

- TBD μA *3, *4

Ta = +85°C

- TBD μA *3, *4

Ta = +105°C

1: VCC = 3.3V

2: VCC = 5.5V


4: When LVD is off

5: When sub oscillation is off




Table 14-10 Typical and maximum current consumption in Low-voltage detection circuit, Main flash memory write/erase


Name Conditions

Value Unit Remarks

Min Typ Max

Low-voltage

detection

circuit (LVD)

power supply

current

ICCLVD

VCC

At operation - 4 7 μA For occurrence of

interrupt

MainFlash

memory

write/erase

current

ICCFLASH At

write/erase - 13.4 15.9 mA

Peripheral Current Dissipation

Clock

system Peripheral Unit

Frequency (MHz) Unit Remarks

50 100 200

HCLK

GPIO All ports 0.39 0.81 1.56

mA

DMAC - 0.99 1.97 3.82

DSTC - 0.73 1.49 2.86

External bus I/F - 0.25 0.48 0.97

SD card I/F - 0.74 1.47 2.90

CAN 1 ch 0.06 0.08 0.16

CAN-FD 1 ch 0.77 1.50 2.95

USB 1 ch 0.48 0.95 1.89

Ethernet-MAC - 1.85 3.63 7.20

I2S - 0.51 1.02 1.99

High-Speed Quad SPI - 0.48 0.97 1.49

Programmable CRC - 0.05 0.10 0.22

PCLK1

Base timer 4 ch 0.21 0.42 0.83

mA

Multi-functional

timer/PPG 1 unit/4 ch 0.83 1.65 3.25

Quadrature

position/revolution

counter

1 unit 0.07 0.13 0.27

A/D converter 1 unit 0.31 0.60 1.17

PCLK2

Multi-function serial 1 ch 0.41 0.81 -

mA HDMI-CEC/

Remote control receiver 1 ch 0.20 0.39 -



14.3.2 Pin Characteristics (VCC = USBVCC0 = USBVCC1 = ETHVCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V)

Parameter Symbol Pin Name Conditions Value

Unit Remarks Min Typ Max

"H" level input

voltage

(hysteresis

input)

VIHS

CMOS hysteresis

input pin, MD0, MD1 -

VCC×0.8 - VCC + 0.3 V

ETHVCC×0.8 - ETHVCC + 0.3 V

5V tolerant input pin - VCC×0.8 - VSS + 5.5 V

Input pin doubled as

I2C Fm+

- VCC×0.7 - VSS + 5.5 V

TTL Schmitt

input pin - 2.0 - ETHVCC+0.3 V

"L" level input

voltage

(hysteresis

input)

VILS

CMOS hysteresis

input pin, MD0, MD1 -

VSS - 0.3 - VCC×0.2 V

VSS - 0.3 - ETHVCC×0.2 V

5V tolerant input pin - VSS - 0.3 - VCC×0.2 V

Input pin doubled as

I2C Fm+

- VSS - VCC×0.3 V

TTL Schmitt

input pin - VSS - 0.3 - 0.8 V

"H" level

output voltage VOH

4 mA type

VCC ≥ 4.5V,

IOH = - 4 mA VCC - 0.5 - VCC V

VCC < 4.5V,

IOH = - 2 mA

ETHVCC ≥ 4.5V,

IOH = - 4 mA VCC - 0.5 - ETHVCC V

ETHVCC < 4.5V,

IOH = - 2 mA

8 mA type

VCC ≥ 4.5V,

IOH = - 8 mA VCC - 0.5 - VCC V

VCC < 4.5V,

IOH = - 4 mA

ETHVCC ≥ 4.5V,

IOH = - 8 mA ETHVCC - 0.5 - ETHVCC V

ETHVCC < 4.5V,

IOH = - 4 mA

12 mA type

VCC ≥ 4.5V,

IOH = - 12 mA VCC - 0.5 - VCC V

VCC < 4.5V,

IOH = - 8 mA

The pin

doubled as USB I/O

USBVCC ≥ 4.5V,

IOH = - 20.5 mA USBVCC - 0.4 - USBVCC V *1

USBVCC < 4.5V,

IOH = - 13.0 mA

The pin

doubled as I2C Fm+

VCC ≥ 4.5V,

IOH = - 4 mA VCC - 0.5 - VCC V At GPIO

VCC < 4.5V,

IOH = - 3 mA





"L" level

output voltage VOL

4 mA type

VCC ≥ 4.5V,

IOL = 4 mA VSS - 0.4 V

VCC < 4.5V,

IOL = 2 mA

ETHVCC ≥ 4.5V,


RTHVCC < 4.5V,

IOL = 2 mA

8 mA type

VCC ≥ 4.5V,


VCC < 4.5V,

IOL = 4 mA

ETHVCC ≥ 4.5V,


RTHVCC < 4.5V,

IOL = 4 mA

12 mA type

VCC ≥ 4.5V,

IOL = 12 mA VSS - 0.4 V

VCC < 4.5V,

IOL = 8 mA

The pin doubled

as USB I/O

USBVCC ≥ 4.5V,

IOL = 18.5 mA VSS - 0.4 V *1

USBVCC < 4.5V,

IOL = 10.5 mA

The pin doubled

as I2C Fm+

VCC ≥ 4.5V,

IOL = 4 mA

VSS - 0.4 V

At GPIO VCC < 4.5V,

IOL = 3 mA

VCC ≤ 4.5V,

IOL = 20 mA

At I2C

Fm+

Input leak

current IIL - - - 5 - + 5 μA

Pull-up

resistor value RPU Pull-up pin

VCC ≥ 4.5V 25 50 100 kΩ

VCC < 4.5V 30 80 200

Input

capacitance CIN

Other than

VCC,

USBVCC0,

USBVCC1,

ETHVCC,

VBAT, VSS,

AVCC, AVSS,

AVRH

- - 5 15 pF

1: USBVcc0 and USBVcc1 are described as USBVcc.



14.4 AC Characteristics

14.4.1 Main Clock Input Characteristics (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, Ta = -40C to +105C)


Name Conditions

Value Unit Remarks

Min Max

Input frequency FCH

X0,

X1

VCC ≥4.5V 4 48 MHz

When crystal oscillator is

connected VCC < 4.5V 4 20

VCC ≥4.5V 4 48 MHz When using external clock

VCC < 4.5V 4 20

Input clock cycle tCYLH VCC ≥4.5V 20.83 250

ns When using external clock VCC < 4.5V 50 250

Input clock pulse width - PWH/tCYLH,

PWL/tCYLH 45 55 % When using external clock

Input clock rise time and fall

time

tCF,

tCR - - 5 ns When using external clock

Internal operating clock *1

frequency

FCC - - - 200 MHz Base clock (HCLK/FCLK)

FCP0 - - - 100 MHz APB0bus clock *2



Internal operating clock *1

cycle time

tCYCC - - 5 - ns Base clock (HCLK/FCLK)

tCYCP0 - - 10 - ns APB0bus clock *2



1: For more information about each internal operating clock, see "CHAPTER 2-1: Clock" in "FM4 Family Peripheral

Manual Main Part (MN709-00001).”

2: For more about each APB bus to which each peripheral is connected, see "10. Block Diagram" in this data sheet.

X0



14.4.2 Sub Clock Input Characteristics (VBAT = 1.65V to 5.5V, VSS = 0V)


Name Conditions

Value Unit Remarks

Min Typ Max

Input frequency 1/tCYLL

X0A,

X1A

- - 32.768 - kHz When crystal oscillator

is connected *

- 32 - 100 kHz When using external

clock

Input clock cycle tCYLL - 10 - 31.25 μs When using external

clock

Input clock pulse width - PWH/tCYLL,

PWL/tCYLL 45 - 55 %

When using external

clock

*: For more information about crystal oscillator, see “Sub crystal oscillator” in “9. Handling Devices.”

14.4.3 Built-In CR Oscillation Characteristics

Built-In High-Speed CR

(VCC = 2.7V to 5.5V, VSS = 0V)



Clock frequency FCRH

Tj = - 20°C to + 105°C 3.92 4 4.08

MHz

When trimming *1

Tj = - 40°C to + 125°C 3.88 4 4.12

Tj = - 40°C to + 125°C 3 4 5 When not trimming

Frequency

stabilization

time

tCRWT - - - 30 μs *2

1: In the case of using the values in CR trimming area of flash memory at shipment for frequency/temperature trimming

2: This is the time to stabilize the frequency of the high-speed CR clock after setting trimming value. During this period, it

is able to use the high-speed CR clock as a source clock.

Built-In Low-speed CR

(VCC = 2.7V to 5.5V, VSS = 0V)

Parameter Symbol Condition Value


Clock frequency FCRL - 50 100 150 kHz

0.8 × VBAT

t CYLL

0.8 × VBAT

0.2 × VBAT 0.2 × VBAT

0.8 × VBAT

P WL P WH

X0A



14.4.4 Operating Conditions of Main PLL (in the case of using main clock for input clock of PLL)

(VCC = 2.7V to 5.5V, VSS = 0V)

Parameter Symbol Value


PLL oscillation stabilization wait time*1

(lock up time) tLOCK 100 - - μs

PLL input clock frequency FPLLI 4 - 16 MHz

PLL multiplication rate - 13 - 100 multiplier

PLL macro oscillation clock frequency FPLLO 200 - 400 MHz

Main PLL clock frequency*2 FCLKPLL - - 200 MHz

1: Time from when the PLL starts operating until the oscillation stabilizes

2: For more information about Main PLL clock (CLKPLL), see "Chapter 2-1: Clock" in "FM4 Family Peripheral Manual

Main Part (MN709-00001).”

14.4.5 Operating Conditions of USB/Ethernet PLL・I2S PLL (in the case of

using main clock for input clock of PLL) (VCC = 2.7V to 5.5V, VSS = 0V)





PLL input clock frequency FPLLI 4 - 16 MHz


PLL macro oscillation clock frequency FPLLO 200 - 400 MHz USB/Ethernet

307.2 MHz I2S

USB/Ethernet clock frequency *2

FCLKPLL - - 50 MHz After the M

frequency division

I2S clock frequency

*3 FCLKPLL - - 12.288 MHz

After the M

frequency division


2: For more information about USB/Ethernet clock, see "Chapter 2-2: USB/Ethernet Clock Generation" in "FM4 Family

Peripheral Manual Communication Macro Part (MN709-00004).”

3: For more information about I2S clock, see "Chapter 7-1: I

2S Clock Generation" in "FM4 Family Peripheral Manual

Communication Macro Part (MN709-00004).”



14.4.6 Operating Conditions of Main PLL (in the case of using built-in high-speed CR clock for input clock of main PLL)

(VCC = 2.7V to 5.5V, VSS = 0V)





PLL input clock frequency FPLLI 3.8 4 4.2 MHz


PLL macro oscillation clock frequency FPLLO 190 - 400 MHz

Main PLL clock frequency *2

FCLKPLL - - 200 MHz


2: For more information about main PLL clock (CLKPLL), see "Chapter 2-1: Clock" in "FM4 Family Peripheral

Manual Main Part (MN709-00001).”

Note:

− The high-speed CR clock (CLKHC) should be set with frequency/temperature trimming to act as the

source clock of the main PLL.

14.4.7 Reset Input Characteristics (VCC = 2.7V to 5.5V, VSS = 0V)


Name Conditions

Value Unit Remarks

Min Typ

Reset input time tINITX INITX - 500 - ns



14.4.8 Power-On Reset Timing (VCC = 2.7V to 5.5V, VSS = 0V)

Parameter Symbol Pin Name Value

Unit Remarks Min Typ

Power supply rise time Tr

VCC

0 - ms

Power supply shut down time Toff 1 - ms

Time until releasing Power-on reset Tprt 0.33 0.60 ms

0.2V

VDH_minimum

VCC_minimum

Tprt

Internal RST

VCC

CPU Operation start

RST Active Release

Tr

0.2V 0.2V

Toff

Glossary

− VCC_minimum: minimum VCC of recommended operating conditions

− VDH_minimum: minimum release voltage of low-voltage detection reset

See "14.8. Low-Voltage Detection Characteristics.”

14.4.9 GPIO Output Characteristics (VCC = 2.7V to 5.5V, VSS = 0V)


Name Conditions

Value Unit Remarks

Min Typ

Output frequency tPCYCLE Pxx*

VCC ≥ 4.5V - 50 MHz

VCC < 4.5V - 32 MHz

*: GPIO is a target.

Pxx

tPCYCLE



14.4.10 External Bus Timing

External Bus Clock Output Characteristics


Unit Remarks Min Typ

Output frequency tCYCLE MCLKOUT *1

- 50 *2

MHz

1: The external bus clock (MCLKOUT) is a divided clock of HCLK.

For more information about setting of clock divider, see "Chapter 14: External Bus Interface" in "FM4 Family

Peripheral Manual Main Part (MN709-00001)."

2: Generate MCLKOUT at setting more than four divisions when the AHB bus clock exceeds 100 MHz.

External bus signal I/O characteristics

(VCC = 2.7V to 5.5V, VSS = 0V)

Parameter Symbol Conditions Value Unit Remarks

Signal input characteristics

VIH

-

0.8 × VCC V

VIL 0.2 × VCC V

Signal output characteristics

VOH 0.8 × VCC V

VOL 0.2 × VCC V

0.8 × Vcc0.8 × Vcc

tCYCLE

VIH

VIL VIL

VIH

VOH

VOL VOL

VOH

MCLK

Input signal



Separate Bus Access Asynchronous SRAM Mode

(VCC = 2.7V to 5.5V, VSS = 0V)



MOEX

Minimum pulse width tOEW MOEX - MCLK×n-3 - ns

MCSX↓→Address output

delay time tCSL – AV

MCSX[7: 0],

MAD[24: 0] - -9 +9 ns

MOEX↑→Address

hold time tOEH - AX

MOEX,

MAD[24: 0] - 0 MCLK×m+9 ns

MCSX↓→

MOEX↓delay time tCSL - OEL

MOEX,

MCSX[7: 0]

- MCLK×m-9 MCLK×m+9 ns

MOEX↑→

MCSX↑time tOEH - CSH - 0 MCLK×m+9 ns

MCSX↓→

MDQM↓delay time tCSL - RDQML

MCSX,

MDQM[3: 0] - MCLK×m-9 MCLK×m+9 ns

Data set up→MOEX↑

time tDS - OE

MOEX,

MADATA[31: 0] - 20 - ns

MOEX↑→

Data hold time tDH - OE

MOEX,

MADATA[31: 0] - 0 - ns

MWEX

Minimum pulse width tWEW MWEX - MCLK×n-3 - ns

MWEX↑→Address

output delay time tWEH - AX

MWEX,

MAD[24: 0] - 0 MCLK×m+9 ns

MCSX↓→

MWEX↓delay time tCSL - WEL

MWEX,

MCSX[7: 0]

- MCLK×n-9 MCLK×n+9 ns

MWEX↑→

MCSX↑delay time tWEH - CSH - 0 MCLK×m+9 ns

MCSX↓→

MDQM↓delay time tCSL-WDQML

MCSX,

MDQM[3: 0] - MCLK×n-9 MCLK×n+9 ns

MCSX↓→

Data output time tCSL-DX

MCSX,

MADATA[31: 0] - MCLK-9 MCLK+9 ns

MWEX↑→

Data hold time tWEH - DX

MWEX,

MADATA[31: 0] - 0 MCLK×m+9 ns

Note:

− When the external load capacitance CL = 30 pF (m = 0 to 15, n = 1 to 16)



Invalid

Address

tCSL-OEL

tCSL-AV

RD

Address

WD

tDH-OEtDS-OE

tWEH-DX

tOEW

tOEH-AX

tOEH-CSH

tWEW

tCYCLE

tCSL-WEL

tCSL-AV

tWEH-CSH

tWEH-AX

tCSL-WDQMLtCSL-RDQML

tCSL-DX

MCLK

MCSX[7: 0]

MAD[24: 0]

MDQM[1: 0]

MWEX

MADATA[15: 0]

MOEX



Separate Bus Access Synchronous SRAM Mode

(VCC = 2.7V to 5.5V, VSS = 0V)



Address delay time tAV MCLK,

MAD[24: 0] - 1 9 ns

MCSX delay time tCSL MCLK,

MCSX[7: 0]

- 1 9 ns

tCSH - 1 9 ns

MOEX delay time tREL MCLK,

MOEX

- 1 9 ns

tREH - 1 9 ns

Data set up

→MCLK↑ time tDS

MCLK,

MADATA[31: 0] - 19 - ns

MCLK↑→

Data hold time tDH

MCLK,

MADATA[31: 0] - 0 - ns

MWEX delay time tWEL MCLK,

MWEX

- 1 9 ns

tWEH - 1 9 ns

MDQM[1: 0]

delay time

tDQML MCLK,

MDQM[3: 0]

- 1 9 ns

tDQMH - 1 9 ns

MCLK↑→

Data output time tODS

MCLK,

MADATA[31: 0] - MCLK+1 MCLK+18 ns

MCLK↑→

Data hold time tOD

MCLK,

MADATA[31: 0] - 1 18 ns

Note:

− When the external load capacitance CL = 30 pF

Invalid

tDQML

tREH

Address

tCSL

tAV

tREL

RD

Address

WD

tDQMH

tWEHtWEL

tDHtDS

tOD

tAV

tCSH

tCYCLE

tDQML tDQMH

tODS

MCLK

MCSX[7: 0]

MAD[24: 0]

MOEX

MWEX

MADATA[31: 0]

MDQM[3: 0]



Multiplexed Bus Access Asynchronous SRAM Mode

(VCC = 2.7V to 5.5V, VSS = 0V)



Multiplexed

address delay time tALE-CHMADV

MALE,

MAD[24: 0]

- 0 10 ns

Multiplexed address hold

time tCHMADH - MCLK×n+0 MCLK×n+10 ns

Note:


MCLK

MCSX[7: 0]

MALE

MOEX

MWEX

MADATA[31: 0]

MAD [24: 0]

MDQM [3: 0]



Multiplexed Bus Access Synchronous SRAM Mode

(VCC = 2.7V to 5.5V, VSS = 0V)



MALE delay time

tCHAL MCLK,

MALE

- 1 9

tCHAH - 1 9

MCLK↑→Multiplexed

address delay time tCHMADV

MCLK,

MADATA[31: 0]

- 1 tOD ns

MCLK↑→Multiplexed

data output time tCHMADX - 1 tOD ns

Note:


MCLK

MCSX[7: 0]

MALE

MOEX

MWEX

MADATA[31: 0]

MAD [24: 0]

MDQM [3: 0]



NAND flash Mode

(VCC = 2.7V to 5.5V, VSS = 0V)



MNREX

Min pulse width tNREW MNREX - MCLK×n-3 - ns

Data set up

→MNREX↑time tDS – NRE

MNREX,

MADATA[31: 0] - 20 - ns

MNREX↑→

Data hold time tDH – NRE

MNREX,

MADATA[31: 0] - 0 - ns

MNALE↑→

MNWEX delay time tALEH - NWEL

MNALE,

MNWEX - MCLK×m-9 MCLK×m+9 ns

MNALE↓→

MNWEX delay time tALEL - NWEL

MNALE,


MNCLE↑→

MNWEX delay time tCLEH - NWEL

MNCLE,


MNWEX↑→

MNCLE delay time tNWEH - CLEL

MNCLE,

MNWEX - 0 MCLK×m+9 ns

MNWEX

Min pulse width tNWEW MNWEX - MCLK×n-3 - ns

MNWEX↓→

Data output time tNWEL – DV

MNWEX,

MADATA[31: 0] - -9 9 ns

MNWEX↑→

Data hold time tNWEH – DX

MNWEX,

MADATA[31: 0] - 0 MCLK×m+9 ns

Note:


NAND Flash Read

MCLK

MNREX

MADATA[31: 0] Read



NAND Flash Address Write

NAND Flash Command Write

MCLK

MNALE

MNCLE

MADATA[31: 0]

MNWEX

Write

Write

MCLK

MNALE

MNCLE

MADATA[31: 0]

MNWEX



External Ready Input Timing

(VCC = 2.7V to 5.5V, VSS = 0V)



MCLK↑

MRDY input

setup time

tRDYI MCLK,

MRDY - 19 - ns

When RDY is input

When RDY is released

· · ·

Over 2cycle

tRDYI

· · · · · ·

2 cycles

tRDYI

0.5×VCC

MCLK

Original

MOEX

MWEX

MRDY

MCLK

Extended

MOEX

MWEX

MRDY



SDRAM Mode

(VCC = 2.7V to 3.6V, VSS = 0V)

Parameter Symbol Pin Name Value Unit


Output frequency tCYCSD MSDCLK - - 50 MHz

Address delay time tAOSD MSDCLK,

MAD[15: 0] - 2 12 ns

MSDCLK↑→

Data output delay time tDOSD

MSDCLK,

MADATA[31: 0] - 2 12 ns

MSDCLK↑→

Data output Hi-Z time tDOZSD

MSDCLK,

MADATA[31: 0] - 2 19.5 ns

MDQM[3: 0] delay time tWROSD MSDCLK,

MDQM[1: 0] - 1 12 ns

MCSX delay time tMCSSD MSDCLK,

MCSX8 - 2 12 ns

MRASX delay time tRASSD MSDCLK,

MRASX - 2 12 ns

MCASX delay time tCASSD MSDCLK,

MCASX - 2 12 ns

MSDWEX delay time tMWESD MSDCLK,

MSDWEX - 2 12 ns

MSDCKE delay time tCKESD MSDCLK,

MSDCKE - 2 12 ns

Data set up time tDSSD MSDCLK,

MADATA[31: 0] - 19 - ns

Data hold time tDHSD MSDCLK,

MADATA[31: 0] - 0 - ns

Note:




RD

WD

MSDCLK

MDQM[1:0]

MCSX

MRASX

MCASX

MSDWEX

MSDCKE

MADATA[15:0]

Address

MADATA[15:0]

MAD[24:0]

tCYCSD

tAOSD

tWROSD

tMCSSD

tRASSD

tCASSD

tMWESD

tCKESD

tDOSD tDOZSD

tDSSD tDHSD

SDRAM Access



14.4.11 Base Timer Input Timing

Timer Input Timing

(VCC = 2.7V to 5.5V, VSS = 0V)

Parameter Symbol Pin Name Condi

tions

Value Unit Remarks

Min Max

Input pulse width tTIWH, tTIWL TIOAn/TIOBn

(when using as ECK, TIN) - 2tCYCP - ns

Trigger Input Timing

(VCC = 2.7V to 5.5V, VSS = 0V)

Parameter Symbol Pin Name Condi

tions

Value Unit Remarks

Min Max

Input pulse width tTRGH, tTRGL TIOAn/TIOBn

(when using as TGIN) - 2tCYCP - ns

Note:

− tCYCP indicates the APB bus clock cycle time. Fore more information about the APB bus number to

which the base timer is connected, see "10. Block Diagram" in this data sheet.

tTIWH

VIHS VIHS

VILS VILS

tTIWL

tTRGH

VIHS VIHS

VILS VILS

tTRGL

ECK

TIN

TGIN



14.4.12 CSIO (SPI) Timing

Synchronous serial (SPI = 0, SCINV = 0)

(VCC = 2.7V to 5.5V, VSS = 0V)


Name Conditions

VCC < 4.5V VCC ≥ 4.5V Unit

Min Max Min Max

Baud rate - - - 8 - 8 Mbps

Serial clock cycle time tSCYC SCKx

Internal shift

clock operation

4tCYCP - 4tCYCP - ns

SCK↓→SOT delay time tSLOVI SCKx,

SOTx - 30 + 30 - 20 + 20 ns

SIN→SCK↑

setup time tIVSHI

SCKx,

SINx 50 - 30 - ns

SCK↑→SIN hold time tSHIXI SCKx,

SINx 0 - 0 - ns

Serial clock "L" pulse width tSLSH SCKx

External shift

clock

operation

2tCYCP - 10 - 2tCYCP - 10 - ns

Serial clock "H" pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns

SCK↓→SOT delay time tSLOVE SCKx,

SOTx - 50 - 30 ns

SIN→SCK↑

setup time tIVSHE

SCKx,

SINx 10 - 10 - ns

SCK↑→SIN hold time tSHIXE SCKx,

SINx 20 - 20 - ns

SCK fall time tF SCKx - 5 - 5 ns

SCK rise time tR SCKx - 5 - 5 ns

Notes:

− The above characteristics apply to CLK synchronous mode.

− tCYCP indicates the APB bus clock cycle time. For more information about the APB bus number to

which the multi-function serial is connected, see "10. Block Diagram" in this data sheet.

− These characteristics only guarantee the same relocate port number; for example, the combination

of SCLKx_0 and SOTx_1 is not guaranteed.

− When the external load capacitance CL = 30 pF.



MS bit = 0

MS bit = 1

tSCYC

VOH

VOH

VOL

VOL

VOL

VIH

VIL

VIH

VIL

tSLOVI

tIVSHI tSHIXI

tSLSH tSHSL

VIH

tF tR

VIH

VOH

VIH

VIL VIL

VOL

VIH

VIL

VIH

VIL

tSLOVE

tIVSHE tSHIXE

SCK

SOT

SIN

SCK

SOT

SIN



Synchronous Serial (SPI = 0, SCINV = 1)

(VCC = 2.7V to 5.5V, VSS = 0V)


Name Conditions


Min Max Min Max

Baud rate - - - - 8 - 8 Mbps


Internal shift

clock operation


SCK↑→SOT delay time tSHOVI SCKx,

SOTx - 30 + 30 - 20 + 20 ns

SIN→SCK↓ setup time tIVSLI SCKx,

SINx 50 - 30 - ns

SCK↓→SIN hold time tSLIXI SCKx,

SINx 0 - 0 - ns


External shift

clock operation



SCK↑→SOT delay time tSHOVE SCKx,

SOTx - 50 - 30 ns

SIN→SCK↓ setup time tIVSLE SCKx,

SINx 10 - 10 - ns

SCK↓→SIN hold time tSLIXE SCKx,

SINx 20 - 20 - ns



Notes:









MS bit = 0

MS bit = 1

tSCYC

VOH VOH

VOH

VOL

VOL

VIH

VIL

VIH

VIL

tSHOVI

tIVSLI tSLIXI

tSHSL tSLSH

VIH

tFtR

VIH

VOH

VILVIL VIL

VOL

VIH

VIL

VIH

VIL

tSHOVE

tIVSLE tSLIXE

SCK

SOT

SIN

SCK

SOT

SIN




(VCC = 2.7V to 5.5V, VSS = 0V)


Name Conditions


Min Max Min Max



Internal shift

clock operation



SOTx - 30 + 30 - 20 + 20 ns

SIN→SCK↓

setup time tIVSLI

SCKx,

SINx 50 - 30 - ns


SINx 0 - 0 - ns

SOT→SCK↓ delay time tSOVLI SCKx,

SOTx 2tCYCP - 30 - 2tCYCP - 30 - ns


External shift

clock operation




SOTx - 50 - 30 ns

SIN→SCK↓

setup time tIVSLE

SCKx,

SINx 10 - 10 - ns


SINx 20 - 20 - ns



Notes:









MS bit = 0

MS bit = 1

* Changes when writing to TDR register

tSOVLI

tSCYC

tSHOVIVOL VOL

VOH

VOH

VOL

VOH

VOL

VIH

VIL

VIH

VIL

tIVSLI tSLIXI

tF tR

tSLSH tSHSL

tSHOVE

VIL VIL

VIH VIH VIH

VOH

*

VOL

VOH

VOL

VIH

VIL

VIH

VIL

tIVSLE tSLIXE

SCK

SOT

SIN

SCK

SOT

SIN




(VCC = 2.7V to 5.5V, VSS = 0V)


Name Conditions


Min Max Min Max



Internal shift

clock operation



SOTx - 30 + 30 - 20 + 20 ns

SIN→SCK↑ setup time tIVSHI SCKx,

SINx 50 - 30 - ns


SINx 0 - 0 - ns

SOT→SCK↑ delay time tSOVHI SCKx,



External shift

clock operation




SOTx - 50 - 30 ns

SIN→SCK↑ setup time tIVSHE SCKx,

SINx 10 - 10 - ns


SINx 20 - 20 - ns



Notes:









MS bit = 0

MS bit = 1

tSCYC

tSLOVI

VOL

VOH VOH

VOH

VOL

VOH

VOL

VIH

VIL

VIH

VIL

tIVSHI tSHIXI

tSOVHI

tSHSLtR tSLSH tF

tSLOVE

VIL VILVIL

VIH VIHVIH

VOH

VOL

VOH

VOL

VIH

VIL

VIH

VIL

tIVSHE tSHIXE

SCK

SOT

SIN

SCK

SOT

SIN



When Using Synchronous Serial Chip Select (SPI = 1, SCINV = 0, MS = 0, CSLVL = 1)

(VCC = 2.7V to 5.5V, VSS = 0V)

Parameter Symbol Conditions VCC < 4.5V VCC ≥ 4.5V

Unit Min Max Min Max

SCS↓→SCK↓ setup time tCSSI Internal shift

clock

operation

(*1)-50 (*1)+0 (*1)-50 (*1)+0 ns

SCK↑→SCS↑ hold time tCSHI ( *2)+0 ( *2)+50 ( *2)+0 ( *2)+50 ns

SCS deselect time tCSDI (*3)-50

+5tCYCP

(*3)+50

+5tCYCP

(*3)-50

+5tCYCP

(*3)+50

+5tCYCP ns

SCS↓→SCK↓ setup time tCSSE

External shift

clock

operation

3tCYCP+30 - 3tCYCP+30 - ns

SCK↑→SCS↑ hold time tCSHE 0 - 0 - ns

SCS deselect time tCSDE 3tCYCP+30 - 3tCYCP+30 - ns

SCS↓→SOT delay time tDSE - 40 - 40 ns

SCS↑→SOT delay time tDEE 0 - 0 - ns

(*1): CSSU bit value×serial chip select timing operating clock cycle [ns]

(*2): CSHD bit value×serial chip select timing operating clock cycle [ns]

(*3): CSDS bit value×serial chip select timing operating clock cycle [ns]

Notes:



− For more information about CSSU, CSHD, CSDS, and the serial chip select timing operating

clock, see "FM4 Family Peripheral Manual Main Part (MN709-00001).”




tCSSI tCSHI

tCSDI

tCSSE tCSHE

tCSDE

tDEE

tDSE

SCS output

SCK output

SOT

(SPI=0)

SOT

(SPI=1)

SCS input

SCK input

SOT

(SPI=0)

SOT

(SPI=1)




(VCC = 2.7V to 5.5V, VSS = 0V)




clock

operation

(*1)-50 (*1)+0 (*1)-50 (*1)+0 ns

SCK↑→SCS↑ hold time tCSHI ( *2)+0 ( *2)+50 ( *2)+0 ( *2)+50 ns


+5tCYCP

(*3)+50

+5tCYCP

(*3)-50

+5tCYCP

(*3)+50

+5tCYCP ns


External shift

clock

operation









Notes:








tCSSI tCSHI

tCSDI

tCSSE tCSHE

tCSDE

tDEE

tDSE

SOT

(SPI=0)

SOT

(SPI=1)

SCK

input

SOT

(SPI=0)

SOT

(SPI=1)

SCS input

SCS output

SCK output




(VCC = 2.7V to 5.5V, VSS = 0V)



SCS↑→SCK↓ setup time tCSSI Internal shift

clock

operation

(*1)-50 (*1)+0 (*1)-50 (*1)+0 ns

SCK↑→SCS↓ hold time tCSHI ( *2)+0 ( *2)+50 ( *2)+0 ( *2)+50 ns


+5tCYCP

(*3)+50

+5tCYCP

(*3)-50

+5tCYCP

(*3)+50

+5tCYCP ns

SCS↑→SCK↓ setup time tCSSE

External shift

clock

operation


SCK↑→SCS↓ hold time tCSHE 0 - 0 - ns


SCS↑→SOT delay time tDSE - 40 - 40 ns

SCS↓→SOT delay time tDEE 0 - 0 - ns




Notes:








tCSSI tCSHI

tCSDI

tCSSEtCSHE

tCSDE

tDEE

tDSE

SCS

output

SCK

output

SOT

(SPI=0)

SOT

(SPI=1)

SCS

input

SCK

input

SOT

(SPI=0)

SOT

(SPI=1)




(VCC = 2.7V to 5.5V, VSS = 0V)

Parameter Symbol Conditions VCC < 4.5V VCC≧4.5V

Units Min Max Min Max

SCS↑→SCK↑setup time tCSSI Internal

shift

clock

operation

(*1)-50 (*1)+0 (*1)-50 (*1)+0 ns

SCK↓→SCS↓hold time tCSHI ( *2)+0 (

*2)+50 (

*2)+0 (

*2)+50 ns


+5tCYCP

(*3)+50

+5tCYCP

(*3)-50

+5tCYCP

(*3)+50

+5tCYCP ns

SCS↑→SCK↑setup time tCSSE

External

shift clock

operation


SCK↓→SCS↓hold time tCSHE 0 - 0 - ns







Notes:








tCSSI tCSHI

tCSDI

tCSSEtCSHE

tCSDE

tDEE

tDSE

SCS output

SCK output

SOT

(SPI=0)

SOT

(SPI=1)

SCS input

SCK input

SOT

(SPI=0)

SOT

(SPI=1)



High-Speed Synchronous Serial (SPI = 0, SCINV = 0)

(VCC = 2.7V to 5.5V, VSS = 0V)


Name Conditions

VCC < 4.5V VCC ≥4.5V Unit

Min Max Min Max



Internal shift

clock operation



SOTx - 10 + 10 - 10 + 10 ns


SINx

14 - 12.5 - ns

12.5*


SINx 5 - 5 - ns


External shift

clock operation




SOTx - 15 - 15 ns


SINx 5 - 5 - ns


SINx 5 - 5 - ns



Notes:




− These characteristics only guarantee the following pins:

No chip select: SIN4_0, SOT4_0, SCK4_0

Chip select: SIN6_0, SOT6_0, SCK6_0, SCS60_0, SCS61_0, SCS62_0, SCS63_0

− When the external load capacitance CL = 30 pF. (For *, when CL = 10 pF)



MS bit = 0

MS bit = 1

tSCYC

VOH

VOH

VOL

VOL

VOL

VIH

VIL

VIH

VIL

tSLOVI

tIVSHI tSHIXI

tSLSH tSHSL

VIH

tF tR

VIH

VOH

VIH

VIL VIL

VOL

VIH

VIL

VIH

VIL

tSLOVE

tIVSHE tSHIXE

SCK

SOT

SIN

SCK

SOT

SIN




(VCC = 2.7V to 5.5V, VSS = 0V)


Name Conditions


Min Max Min Max



Internal shift

clock operation



SOTx - 10 + 10 - 10 + 10 ns


SINx

14 - 12.5 - ns

12.5*


SINx 5 - 5 - ns


External shift

clock operation




SOTx - 15 - 15 ns


SINx 5 - 5 - ns


SINx 5 - 5 - ns



Notes:







− When the external load capacitance CL = 30 pF. (For *, when CL = 10 pF)



MS bit = 0

MS bit = 1

tSCYC

VOH VOH

VOH

VOL

VOL

VIH

VIL

VIH

VIL

tSHOVI

tIVSLI tSLIXI

tSHSL tSLSH

VIH

tFtR

VIH

VOH

VILVIL VIL

VOL

VIH

VIL

VIH

VIL

tSHOVE

tIVSLE tSLIXE

SCK

SOT

SIN

SCK

SOT

SIN




(VCC = 2.7V to 5.5V, VSS = 0V)


Name Conditions


Min Max Min Max



Internal shift

clock operation



SOTx - 10 + 10 - 10 + 10 ns


SINx

14 - 12.5 - ns

12.5*


SINx 5 - 5 - ns

SOT→SCK↓ delay time tSOVLI SCKx,



External shift

clock operation




SOTx - 15 - 15 ns


SINx 5 - 5 - ns


SINx 5 - 5 - ns



Notes:







− When the external load capacitance CL = 30 pF. (for *, when CL = 10 pF)



MS bit = 0

MS bit = 1

* Changes when writing to TDR register

tSOVLI

tSCYC

tSHOVIVOL VOL

VOH

VOH

VOL

VOH

VOL

VIH

VIL

VIH

VIL

tIVSLI tSLIXI

tF tR

tSLSH tSHSL

tSHOVE

VIL VIL

VIH VIH VIH

VOH

*

VOL

VOH

VOL

VIH

VIL

VIH

VIL

tIVSLE tSLIXE

SCK

SOT

SIN

SCK

SOT

SIN




(VCC = 2.7V to 5.5V, VSS = 0V)


Name Conditions


Min Max Min Max



Internal shift

clock operation



SOTx - 10 + 10 - 10 + 10 ns


SINx

14 - 12.5 - ns

12.5*


SINx 5 - 5 - ns

SOT→SCK↑ delay time tSOVHI SCKx,



External shift

clock operation




SOTx - 15 - 15 ns


SINx 5 - 5 - ns


SINx 5 - 5 - ns



Notes:







− When the external load capacitance CL = 30 pF. (for *, when CL = 10 pF)



MS bit = 0

MS bit = 1

tSCYC

tSLOVI

VOL

VOH VOH

VOH

VOL

VOH

VOL

VIH

VIL

VIH

VIL

tIVSHI tSHIXI

tSOVHI

tSHSLtR tSLSH tF

tSLOVE

VIL VILVIL

VIH VIHVIH

VOH

VOL

VOH

VOL

VIH

VIL

VIH

VIL

tIVSHE tSHIXE

SCK

SOT

SIN

SCK

SOT

SIN



When Using High-Speed Synchronous Serial chip select (SPI = 1, SCINV = 0, MS = 0,

CSLVL = 1)

(VCC = 2.7V to 5.5V, VSS = 0V)




clock

operation

(*1)-20 (*1)+0 (*1)-20 (*1)+0 ns

SCK↑→SCS↑ hold time tCSHI ( *2)+0 (

*2)+20 (

*2)+0 (

*2)+20 ns


+5tCYCP

(*3)+20

+5tCYCP

(*3)-20

+5tCYCP

(*3)+20

+5tCYCP ns


External shift

clock

operation









Notes:








tCSSI tCSHI

tCSDI

tCSSE tCSHE

tCSDE

tDEE

tDSE

SCS

output

SCK

output

SOT

(SPI=0)

SOT

(SPI=1)

SCS

input

SCK

input

SOT

(SPI=0)

SOT

(SPI=1)




CSLVL = 1)

(VCC = 2.7V to 5.5V, VSS = 0V)

Parameter Symbol Conditions VCC < 4.5V VCC≥ 4.5V

Unit Min Min Min Max


clock

operation

(*1)-20 (*1)+0 (*1)-20 (*1)+0 ns

SCK↑→SCS↑ hold time tCSHI ( *2)+0 (

*2)+20 (

*2)+0 (

*2)+20 ns


+5tCYCP

(*3)+20

+5tCYCP

(*3)-20

+5tCYCP

(*3)+20

+5tCYCP ns

SCS↓→SCK↑ setup time tCSSE

External shift

clock

operation









Notes:








tCSSI tCSHI

tCSDI

tCSSE tCSHE

tCSDE

tDEE

tDSE

SCS

output

SCK

output

SOT

(SPI=0)

SOT

(SPI=1)

SCS

intpu

SCK

input

SOT

(SPI=0)

SOT

(SPI=1)




CSLVL = 0)

(VCC = 2.7V to 5.5V, VSS = 0V)



SCS↑→SCK↓ setup time tCSSI Internal shift

clock

operation

(*1)-20 (*1)+0 (*1)-20 (*1)+0 ns

SCK↑→SCS↓ hold time tCSHI ( *2)+0 (

*2)+20 (

*2)+0 (

*2)+20 ns


+5tCYCP

(*3)+20

+5tCYCP

(*3)-20

+5tCYCP

(*3)+20

+5tCYCP ns

SCS↑→SCK↓ setup time tCSSE

External shift

clock

operation


SCK↑→SCS↓ hold time tCSHE 0 - 0 - ns







Notes:








tCSSI tCSHI

tCSDI

tCSSEtCSHE

tCSDE

tDEE

tDSE

SCS

output

SCK

output

SOT

(SPI=0)

SOT

(SPI=1)

SCS

input

SCK

input

SOT

(SPI=0)

SOT

(SPI=1)




CSLVL = 0)

(VCC = 2.7V to 5.5V, VSS = 0V)




clock

operation

(*1)-20 (*1)+0 (*1)-20 (*1)+0 ns

SCK↑→SCS↓ hold time tCSHI ( *2)+0 (

*2)+20 (

*2)+0 (

*2)+20 ns


+5tCYCP

(*3)+20

+5tCYCP

(*3)-20

+5tCYCP

(*3)+20

+5tCYCP ns

SCS↑→SCK↑ setup time tCSSE

External shift

clock

operation


SCK↓→SCS↓ hold time tCSHE 0 - 0 - ns







Notes:








tCSSI tCSHI

tCSDI

tCSSEtCSHE

tCSDE

tDEE

tDSE

SCS

output

SCK

output

SOT

(SPI=0)

SOT

(SPI=1)

SCS

input

SCK

input

SOT

(SPI=0)

SOT

(SPI=1)



External clock (EXT = 1): When in Asynchronous Mode Only

(VCC = 2.7V to 5.5V, VSS = 0V)

Parameter Symbol Condition Value


Serial clock "L" pulse width tSLSH

CL = 30 pF

tCYCP + 10 - ns

Serial clock "H" pulse width tSHSL tCYCP + 10 - ns

SCK fall time tF - 5 ns

SCK rise time tR - 5 ns

tSHSL

VIL VIL VIL

VIH VIH VIH

tR tFtSLSH

SCK



14.4.13 External Input Timing (VCC = 2.7V to 5.5V, VSS = 0V)



Input pulse

width tINH, tINL

ADTGx

- 2tCYCP

*1 - ns

A/D converter trigger input

FRCKx Free-run timer input clock

ICxx Input capture

DTTIxX - 2tCYCP

*1 - ns Waveform generator

INT00 to INT31,

NMIX -

2tCYCP + 100*1

- ns External interrupt,

NMI 500

*2 - ns

WKUPx - 500*3

- ns Deep standby wake up

1: tCYCP indicates the APB bus clock cycle time except stop when in Stop mode, in timer mode. For more information

about the APB bus number to which the A/D converter, multi-function timer, and external interrupt are connected, see

"10. Block Diagram" in this data sheet.

2: When in Stop mode, in timer mode

3: When in Deep standby RTC mode, in Deep standby Stop mode



14.4.14 Quadrature Position/Revolution Counter Timing (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, Ta = -40°C to +105°C)


Unit Min Max

AIN pin "H" width tAHL -

2tCYCP* - ns

AIN pin "L" width tALL -

BIN pin "H" width tBHL -

BIN pin "L" width tBLL -

BIN rise time from

AIN pin "H" level tAUBU PC_Mode2 or PC_Mode3

AIN fall time from

BIN pin "H" level tBUAD PC_Mode2 or PC_Mode3

BIN fall time from

AIN pin "L" level tADBD PC_Mode2 or PC_Mode3

AIN rise time from

BIN pin "L" level tBDAU PC_Mode2 or PC_Mode3

AIN rise time from

BIN pin "H" level tBUAU PC_Mode2 or PC_Mode3

BIN fall time from

AIN pin "H" level tAUBD PC_Mode2 or PC_Mode3

AIN fall time from

BIN pin "L" level tBDAD PC_Mode2 or PC_Mode3

BIN rise time from

AIN pin "L" level tADBU PC_Mode2 or PC_Mode3

ZIN pin "H" width tZHL QCR: CGSC = 0

ZIN pin "L" width tZLL QCR: CGSC = 0

AIN/BIN rise and fall time from

determined ZIN level tZABE QCR: CGSC = 1

Determined ZIN level from

AIN/BIN rise and fall time tABEZ QCR: CGSC = 1

*: tCYCP indicates the APB bus clock cycle time except when in Stop mode, in timer mode. For more information about the

APB bus number to which the quadrature position/revolution counter is connected, see "10. Block Diagram" in this

data sheet.

AIN

BIN

tAUBU tBUAD tADBD tBDAU

tAHL tALL

tBHL tBLL



BIN

tBUAU tAUBD tBDAD tADBU

tBHL tBLL

tAHL tALL

AIN

ZIN

ZIN

AIN/BIN



14.4.15 I2C Timing

Standard-mode, Fast-mode

(VCC = 2.7V to 5.5V, VSS = 0V)

Parameter Symbol Conditions Standard-mode Fast-mode

Unit Remarks Min Max Min Max

SCL clock frequency FSCL

CL = 30 pF,

R = (Vp/IOL)*1

0 100 0 400 kHz

(Repeated) START condition hold

time

SDA ↓ → SCL ↓

tHDSTA 4.0 - 0.6 - μs

SCL clock "L" width tLOW 4.7 - 1.3 - μs

SCL clock "H" width tHIGH 4.0 - 0.6 - μs

(Repeated) START condition

setup time

SCL ↑ → SDA ↓

tSUSTA 4.7 - 0.6 - μs

Data hold time

SCL ↓ → SDA ↓ ↑ tHDDAT 0 3.45

*2 0 0.9

*3 μs

Data setup time

SDA ↓ ↑ → SCL ↑ tSUDAT 250 - 100 - ns

Stop condition setup time

SCL ↑ → SDA ↑ tSUSTO 4.0 - 0.6 - μs

Bus free time between

"Stop condition" and

"START condition"

tBUF 4.7 - 1.3 - μs

Noise filter tSP

2 MHz ≤

tCYCP＜40 MHz 2 tCYCP

*4 - 2 tCYCP

*4 - ns

*5

40 MHz ≤

tCYCP ＜60 MHz 4 tCYCP

*4 - 4 tCYCP

*4 - ns

60 MHz ≤

tCYCP ＜80 MHz 6 tCYCP

*4 - 6 tCYCP

*4 - ns

80 MHz ≤

tCYCP ≤100 MHz 8 tCYCP

*4 - 8 tCYCP

*4 - ns

1: R and CL represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively. Vp indicates

the power supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current.

2: The maximum tHDDT must not extend beyond the low period (tLOW) of the device’s SCL signal.

3: Fast-mode I2C bus device can be used on a Standard-mode I

2C bus system as long as the device satisfies the

requirement of "tSUDAT ≥ 250 ns.”

4: tCYCP is the APB bus clock cycle time. For more information about the APB bus number to which the I2C is connected,

see "10.Block Diagram" in this data sheet.

5: When using Standard-mode, the peripheral bus clock must be set more than 2 MHz.

When using Fast-mode, the peripheral bus clock must be set more than 8 MHz.

6: The noise filter time can be changed by register settings. Change the number of the noise filter steps according to the

APB bus clock frequency.



Fast Mode Plus (Fm+)

(VCC = 2.7V to 5.5V, VSS = 0V)

Parameter Symbol Conditions Fast Mode Plus (Fm+)*6


SCL clock frequency FSCL

CL = 30 pF,

R = (Vp/IOL)*1

0 1000 kHz


time

SDA ↓ → SCL ↓

tHDSTA 0.26 - μs

SCL clock "L" width tLOW 0.5 - μs

SCL clock "H" width tHIGH 0.26 - μs

SCL clock frequency tSUSTA 0.26 - μs


time

SDA ↓ → SCL ↓

tHDDAT 0 0.45*2, *3

μs

Data setup time

SDA ↓ ↑ → SCL ↑ tSUDAT 50 - ns

Stop condition setup time

SCL ↑ → SDA ↑ tSUSTO 0.26 - μs

Bus free time between

"Stop condition" and

"START condition"

tBUF 0.5 - μs

Noise filter tSP

60 MHz ≤

tCYCP＜80 MHz 6 tCYCP

*4 - ns

*5 80 MHz ≤

tCYCP ≤100 MHz 8 tCYCP

*4 - ns

1: R and CL represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively. Vp indicates

the power supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current.

2: The maximum tHDDT must not extend beyond the low period (tLOW) of the device’s SCL signal.

3: The Fast mode I2C bus device can be used on a Standard-mode I

2C bus system as long as the device satisfies the

requirement of "tSUDAT ≥ 250 ns.”

4: tCYCP is the APB bus clock cycle time. For more information about the APB bus number to which the I2C is connected,

see "10.Block Diagram" in this data sheet.

5: To use fast mode plus (Fm+), set the peripheral bus clock at 64 MHz or more.

6: The noise filter time can be changed by register settings. Change the number of the noise filter steps according to the

APB bus clock frequency.

7: When using fast mode plus (Fm+), set the I/O pin to the mode corresponding to I2C Fm+ in the EPFR register.

See "Chapter12: I/O PORT" in "FM4 Family Peripheral Manual Main Part (MN709-00001)" for the details.



14.4.16 SD Card Interface Timing

Default-Speed Mode

Clock CLK (All values are referenced to VIH and VIL transition points)

(VCC = 2.7V to 3.6V, VSS = 0V)


Remarks Min Max

Clock frequency Data

Transfer Mode fPP S_CLK

CCARD ≤ 10 pF

(1card)

0 25 MHz

Clock frequency

Identification Mode fOD S_CLK 0/100 400 kHz

Clock low time tWL S_CLK 10 - ns

Clock high time tWH S_CLK 10 - ns

Clock rise time tTLH S_CLK - 10 ns

Clock fall time tTHL S_CLK - 10 ns

* 0 Hz means to stop the clock. The given minimum frequency range is for cases where a continuous clock is required.

Card Inputs CMD, DAT (referenced to Clock CLK)


Remarks Min Max

Input set-up time tISU S_CMD,

S_DATA3: 0 CCARD ≤ 10 pF

(1card)

5 - ns

Input hold time tIH S_CMD,

S_DATA3: 0 5 - ns

Card Outputs CMD, DAT (referenced to Clock CLK)


Remarks Min Max

Output Delay time during

Data Transfer Mode tODLY

S_CMD,

S_DATA3: 0 CCARD ≤ 40 pF

(1card)

0 14 ns

Output Delay time during

Identification Mode tODLY

S_CMD,

S_DATA3: 0 0 50 ns

Default-Speed Mode

Notes:

− The Card Input corresponds to the Host Output and the Card Output corresponds to the Host Input

because this model is the Host.

− For more information about clock frequency (fPP), see “Chapter 15: SD card Interface” in “FM4

Family Peripheral Manual Main Part (MN709-00001).”

VIL VIL

tWL tWH

VIH VIH VIH

tTHL tTLH tISU

VIH

VIL

VIH

VIL

tIH

VOH

VOL

VOH

VOL

tODLY(Max) tODLY(Min)

S_CMD,

S_DATA3: 0

(Card Output)

S_CMD,

S_DATA3: 0

(Card Input)

S_CLK

(SD Clock)



High-Speed Mode

Clock CLK (All values are referred to VIH and VIL)

(VCC = 2.7V to 3.6V, VSS = 0V)


Remarks Min Max

Clock frequency Data Transfer

Mode fPP S_CLK

CCARD ≤ 10

pF

(1card)

0 50 MHz

Clock low time tWL S_CLK 7 - ns

Clock high time tWH S_CLK 7 - ns

Clock rise time tTLH S_CLK - 3 ns

Clock fall time tTHL S_CLK - 3 ns

Card Inputs CMD, DAT (referenced to Clock CLK)


Remarks Min Max

Input set-up time tISU S_CMD,

S_DATA3: 0 CCARD ≤ 10

pF

(1card)

6 - ns

Input hold time tIH S_CMD,

S_DATA3: 0 2 - ns

Card Outputs CMD, DAT (referenced to Clock CLK)


Remarks Min Max

Output delay time during data

transfer mode tODLY

S_CMD,

S_DATA3: 0

CL ≤ 40 pF

(1card) 0 14 ns

Output hold time tOH S_CMD,

S_DATA3: 0

CL ≥ 15 pF

(1card) 2.5 - ns

Total system capacitance for

each line* CL - 1card - 40 pF

*: In order to satisfy severe timing, host shall drive only one card.

High-Speed Mode

Notes:

− The Card Input corresponds to the Host Output and the Card Output corresponds to the Host

Input because this model is the Host.

− For more information about clock frequency (fPP), see “Chapter 15: SD card Interface” in

“FM4 Family Peripheral Manual Main Part (MN709-00001).”

VIL VIL

tWL tWH

VIH VIH VIH

tTHL tTLH tISU

VIH

VIL

VIH

VIL

tIH

VOH

VOL

VOH

VOL

tODLY(Max) tOH(Min)

50%VCC 50%VCC

S_CMD,

S_DATA3: 0

(Card Output)

S_CMD,

S_DATA3: 0

(Card Input)

S_CLK

(SD Clock)



14.4.17 ETM/ HTM Timing (VCC = 2.7V to 5.5V, VSS = 0V)



Data hold tETMH TRACECLK,

TRACED[15: 0]

VCC ≥ 4.5V 2 9 ns

VCC ＜4.5V 2 15

TRACECLK

frequency 1/tTRACE

TRACECLK

VCC ≥ 4.5V 50 MHz

VCC ＜4.5V 32 MHz

TRACECLK

clock cycle tTRACE

VCC ≥ 4.5V 20 - ns

VCC ＜4.5V 31.25 - ns

Note:


HCLK

TRACECLK

TRACED[15: 0]



14.4.18 JTAG Timing (VCC = 2.7V to 5.5V, VSS = 0V)



TMS, TDI setup time tJTAGS TCK,

TMS, TDI

VCC ≥ 4.5V 15 - ns

VCC ＜4.5V

TMS, TDI hold time tJTAGH TCK,

TMS, TDI

VCC ≥ 4.5V 15 - ns

VCC ＜4.5V

TDO delay time tJTAGD TCK,

TDO

VCC ≥ 4.5V - 25 ns

VCC ＜4.5V - 45

Note:


TCK

TMS/TDI

TDO



14.4.19 Ethernet-MAC Timing

RMII transmission (100 Mbps/10 Mbps)

(ETHVCC = 3.0V to 3.6V, 4.5V to 5.5V*1

, VSS = 0V, CL = 25 pF)


Unit Min Max

Reference clock cycle time*2

tREFCYC E_RXCK_REFCK 20ns (typical) - - ns

Reference clock

High-pulse-width duty cycle tREFCYCH E_RXCK_REFCK tREFCYCH/tREFCYC 35 65 %

Reference clock

Low-pulse-width duty cycle tREFCYCL E_RXCK_REFCK tREFCYCL/tREFCYC 35 65 %

Transmitted data → REFCK ↑

delay time tRMIITX

E_TX03, E_RX02,

E_TX01, E_TX00,

E_TXEN

- - 12 ns

1: When ETHV = 4.5V to 5.5V, it is recommended to add a series resistor at the output pin to suppress the output

current.

2: The reference clock is fixed to 50 MHz in the RMII specifications. The clock accuracy should meet the PHY-device

specifications.

E_RXCK_REFCK

E_TXEN

E_TX01E_TX00

tREFCYC

tREFCYCH tREFCYCL

tRMIITX

VOH

VOL

VILS

VIHS VIHS

E_TX03E_TX02



RMII receiving (100 Mbps/10 Mbps

(ETHVCC = 3.0V to 3.6V, 4.5V to 5.5V, VSS = 0V, CL = 25 pF)


Unit Min Max

Reference clock

cycle time* tREFCYC E_RXCK_REFCK 20 ns (typical) - - ns

Reference clock

High-pulse-width duty cycle tREFCYCH E_RXCK_REFCK tREFCYCH/tREFCYC 35 65 %

Reference clock

Low-pulse-width duty cycle tREFCYCL E_RXCK_REFCK tREFCYCL/tREFCYC 35 65 %

Received data → REFCK↑

Setup time tRMIIRXS

E_RX03, E_RX02,

E_RX01, E_RX00,

E_RXDV

- 4 - ns

Received data → REFCK ↑

Hold time tRMIIRXH

E_RX03, E_RX02,

E_RX01, E_RX00,

E_RXDV

- 2 - ns

*: The reference clock is fixed to 50 MHz in the RMII specifications.

The clock accuracy should meet the PHY-device specifications.

E_RXCK_REFCK

E_RXDV

E_RX01E_RX00

tREFCYC

tREFCYCH tREFCYCL

tRMIIRXS tRMIIRXH

VIHS

VILS

VIHS

VILS

VILS

VIHS VIHS

E_RX03E_RX02



Management Interface



Unit Min Max

Management clock

cycle time* tMDCYC E_MDC - 400 - ns

Management clock

High pulse width duty cycle tMDCYCH E_MDC tMDCYCH/tMDCYC 35 65 %

Management clock

Low pulse width duty cycle tMDCYCL E_MDC tMDCYCL/tMDCYC 35 65 %

MDC ↓ → MDIO

Delay time tMDO E_MDIO - - 60 ns

MDIO → MDC ↑

Setup time tMDIS E_MDIO - 20 - ns

MDC ↑ → MDIO

Hold time tMDIH E_MDIO - 0 - ns

*: The clock time should be set to a value greater than the minimum value by setting the Ethernet-MAC setting register.

E_MDC (output)

tMDCYC

tMDCYCH tMDCYCL

tMDIS tMDIH

E_MDIO (input)

tMDO

E_MDIO (output)

tMDIS tMDIH

tMDO

VOL VOH VOL

VOH

VIHS

VILS

VIHS

VILS

VIHS

VILS

VIHS

VILS

VOH

VOL

VOH

VOL



MII Transmission (100 Mbps/10 Mbps)

(ETHVCC = 3.0V to 3.6V, 4.5V to 5.5V*1,

VSS = 0V, CL = 25 pF)


Unit Min Max

Transmission clock

Cycle time*2 tTXCYC E_TCK

100 Mbps

40 ns (typical) - - ns

100 Mbps


Transmission clock

High-pulse-width duty cycle tTXCYCH E_TCK tTXCYCH/tTXCYC 35 65 %

Transmission CLOCK

Low-pulse-width duty cycle tTXCYCL E_TCK tTXCYCL/tTXCYC 35 65 %

TXCK ↑ → Transmitted data delay

time tMIITX

E_TX03, E_TX02,

E_TX01, E_TX00,

E_TXEN

- - 24 ns

1: When ETHV = 4.5V to 5.5V, it is recommended to add a series resistor at the output pin to suppress the output current.

2: The transmission clock is fixed to 25 MHz or 2.5 MHz in the MII specifications. The clock accuracy should meet the

PHY-device specifications.

E_TCK

E_TXEN

E_TX01E_TX00

tTXCYC

tTXCYCH tTXCYCL

tMIITX

VOH

VOL

VILS

VIHS VIHS

E_TX03E_TX02



MII receiving (100 Mbps/10 Mbps)



Unit Min Max

Receiving clock

cycle time* tRXCYC E_RXCK_REFCK

100 Mbps


100 Mbps


Receiving clock

High pulse width duty cycle tRXCYCH E_RXCK_REFCK tRXCYCH/tRXCYC 35 65 %

Receiving clock

Low pulse width duty cycle tRXCYCL E_RXCK_REFCK tRXCYCL/tRXCYC 35 65 %

Received data →

REFCK ↑Setup time tMIIRXS

E_RX03, E_RX02,

E_RX01, E_RX00,

E_RXDV

- 5 - ns

REFCK ↑ →

Received data Hold time tMIIRXH

E_RX03, E_RX02,

E_RX01, E_RX00,

E_RXDV

- 2 - ns

*: The reference clock is fixed to 50 MHz in the RMII specifications.

The clock accuracy should meet the PHY-device specifications.

E_RXDV

E_RX01E_RX00

tRXCYC

tRXCYCH tRXCYCL

tMIIRXS tMIIRXH

E_RXCK_REFCK

VIHS

VILS

VIHS

VILS

VILS

VIHS VIHS

E_RX03E_RX02



14.4.20 I2S Timing

Master Mode Timing

(VCC = 2.7V to 5.5V, VSS = 0V)



Output frequency tmcyc I2SCK - - 12.288 MHz

Output clock pulse width tmhw

I2SCK - 45 55 %

tmlw 45 55 %

I2SCK→I2SWS

delay time tdfs I2SCK, I2SWS - 0 24.0 ns

I2SCK→I2SDO

delay time* tddo I2SCK, I2SDO - 0 24.0 ns

I2SDI→I2SCK

setup time thsdi

I2SCK, I2SDI

- 25.0 - ns

I2SDI→I2SCK

hold time thdi - 0 - ns

Input signal rise time tfi I2SDI

- - 5 ns

Input signal fall time tfi - - 5 ns

*: Except for the first bit of transmission frame

Note:


− When I2SWS = 48 kHz, I2MCLK = 256 × I2SWS

Frame synchronization signal (I2SWS) is settable to 48 kHz, 32 kHz, 16 kHz.

See “Chapter7-2: I2S (Inter-IC Sound bus) Interface” in "FM4 Family Peripheral Manual

Communication Macro Part (MN709-00004)” for the details.



Note:

− See “Chapter7-2: I2S (Inter-IC Sound bus) Interface” in "FM4 Family Peripheral Manual

Communication Macro Part (MN709-00004)” for the details of CPOL, FSPH, FSLIN, and SMPL.

I2SCK (CPOL=0)

tmhw

tmlw

tmcyc

I2SCK (CPOL=1)

tdfs tdfs

I2SWS(FSPH=0, FSLN=0)

tdfs tdfs


tdfs


tdfs

tdfstdfs


tddo

I2SDO

I2SDI(SMPL=0)

tsdi thdi tsdi thdi

I2SDI(SMPL=1)

tsdi thdi

I2SDI0.8×VCC 0.8×VCC

0.2×VCC 0.2×VCC

0.8×VCC

tfi tri



Slave Mode Timing

(VCC = 2.7V to 5.5V, VSS = 0V)



Input frequency tsyc I2SCK - - 12.288 MHz

Input clock pulse width tshw

I2SCK - 45 55 %

tslw 45 55 %

I2SWS→I2SCK

Setup time tsfi I2SCK, I2SWS - 8 - ns

I2SWS→I2SCK

Hole time thfi I2SCK, I2SWS - 0 - ns

I2SCK↑→I2SDO

Delay time*1

tddo

I2SCK, I2SDO

- 0 32 ns

I2SCK↑→I2SDO

Delay Time*2

tdfb1 - 0 32 ns

I2SDI→I2SCK↓

Setup time tsdi

I2SCK, I2SDI

- 8 - ns

I2SDI→I2SCK↓

Hole time thdi - 0 - ns

Input signal rise time tfi I2SCK, I2SWS,

I2SDI

- - 5 ns

Input signal fall time tfi - - 5 ns

1: Except for the first bit of transmission frame

2: When FSPH bit = 1.

Note:


− When I2SWS = 48 kHz, I2MCLK = 256×I2SWS

Frame synchronization signal (I2SWS) is settable to 48 kHz, 32 kHz, 16 kHz. See “Chapter7-2: I2S

(Inter-IC Sound bus) Interface” in "FM4 Family Peripheral Manual Communication Macro Part

(MN709-00004)" for the details.



Note:

− See “Chapter7-2: I2S (Inter-IC Sound bus) Interface” in "FM4 Family Peripheral Manual

Communication Macro Part (MN709-00004)" for the details of FSPH, FSLN, SMPL

− I2SCK input is selectable polarity by CPOL bit of CNTREG register

I2SCK (CPOL=0)

tshw

tslw

tscyc

I2SCK (CPOL=1)

tsfi thfi


tsfi thfi


tsfi



tddo

I2SDO

I2SDI(SMPL=0)

tsdi thdi tsdi thdi

I2SDI(SMPL=1)

tsdi thdi

tsfi

tdfb1

I2SCKI2SWSI2SDI

0.8×VCC 0.8×VCC

0.2×VCC 0.2×VCC

0.8×VCC

tfi tri



I2SMCLK Input Characteristics

(VCC = 2.7V to 5.5V, VSS = 0V)



Input frequency FCHS I2SCK - - 25 MHz

Input clock cycle tCYLHS - - 40 - ns

Input clock pulse width - - PWHS/tCYLHS

PWLS/tCYLHS 45 55 %

When using

external clock

Input clock rise time and fall

time

tCFS

tCRS - - - 5 ns

When using

external clock

I2SMCLK Output Characteristics

(VCC = 2.7V to 5.5V, VSS = 0V)



Input frequency FCHS I2SCK - - 12.288 MHz

I2SMCLK0.8×VCC 0.8×VCC

0.2×VCC 0.2×VCC

0.8×VCC

tCFS tCRSPWHS PWLS

tCYLHS



14.4.21 High-Speed Quad SPI Timing (VCC = 2.7V to 3.6V, VSS = 0V)



Serial clock frequency tSCYCM Q_SCK_0

CL = 15 pF,

VCC = 3.0 to 3.6V - 66 MHz *1

CL = 30 pF - 50 MHz *2

Enabled CS→

CLK Starting Time

(mode0/mode2)

tOSLSK02

Q_SCK_0,

Q_CS0_0,

Q_CS1_0,

Q_CS2_0

CL = 30 pF

1.5×tSCYCM - 5 - ns

Enabled CS→

CLK Starting Time

(mode1/mode3)

tOSLSK13 tSCYCM - 5 - ns

CLK Last→

Disabled CS Time

(mode0/mode2)

tOSKSL02 tSCYCM - ns

CLK Last→

Disabled CS Time

(mode1/mode3)

tOSKSL13 1.5×tSCYCM - ns

SIO Data output time tOSDAT Q_SCK_0,

Q_IO0_0,

Q_IO1_0,

Q_IO2_0,

Q_IO3_0

CL = 15 pF,

VCC = 3.0 to 3.6V 0 5 ns

CL = 30 pF 0 5

SIO Setup tDSSET CL = 30 pF 3 - ns *1

10 - *2

SIO Hold tSDHOLD CL = 30 pF 0.5×tSCYCM - ns

1: When “RTM = 1 and mode = 0,1,3”

2: When “RTM = 1 and mode = 2” or “RTM = 0 and mode = 0,1,2,3”

Note:

− See “Chapter8-3: High-Speed Quad SPI controller” in "FM4 Family Peripheral Manual

Communication Macro Part (MN709-00004)” for the detail of RTM mode.

− When using High-Speed Quad SPI, please set PDSR register to set the pin drive capability for VCC

= 3V. See “Chapter12: I/O Port” in "FM4 Family Peripheral Manual Main Part (MN709-00001)" for

the details.



Q_CS0,Q_CS1,Q_CS2

tOSLSK02

tDSSET

Q_SCK

mode0

mode2

mode1

mode3

tOSLSK13

tSCYCM

tOSKSL02

tOSKSL13

input

tSDHOLD

output

tOSDAT

Q_IO0,Q_IO1,Q_IO2,Q_IO3



14.5 12-bit A/D Converter

Electrical Characteristics for the A/D Converter

(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V)



Resolution - - - - 12 bit

Integral nonlinearity - - - 4.5 - + 4.5 LSB

AVRH = 2.7V to 5.5V

Differential nonlinearity - - - 2.5 - + 2.5 LSB

Zero transition voltage VZT AN00 to

AN31 - 15 - + 15 mV

Full-scale transition

voltage VFST

AN00 to

AN31

AVRH – 15 - AVRH + 15 mV

AVCC - 15 - AVCC + 15 mV

Conversion time - - 0.5*1

- - μs AVCC ≥ 4.5V

Sampling time Ts - *2 -

10 μs AVCC ≥ 4.5V

*2 - AVCC < 4.5V

Compare clock cycle*3

Tcck - 25 - 1000

ns AVCC ≥ 4.5V

50 - 1000 AVCC < 4.5V

State transition time to

operation permission Tstt - 1.0 - - μs

Power supply current

(analog + digital) - AVCC

- 0.69 0.92 mA A/D 1 unit operation

- 1.3 22 μA When A/D stop

Reference power supply

current

(between AVRH and

AVSS)

- AVRH

- 1.1 1.97 mA A/D 1 unit operation

AVRH = 5.5V

- 0.3 6.3 μA When A/D stop

Analog input capacity CAIN - - - 12.05 pF

Analog input resistance RAIN - - - 1.2

kΩ AVCC ≥ 4.5V

1.8 AVCC < 4.5V

Interchannel disparity - - - - 4 LSB

Analog port input current - AN00 to

AN31 - - 5 μA

Analog input voltage - AN00 to

AN31

AVSS - AVRH V

AVSS - AVCC V

Reference voltage - AVRH 4.5 - AVCC

V Tcck ＜ 50ns

2.7 - AVCC Tcck ≥ 50 ns

1: The conversion time is the value of sampling time (Ts) + compare time (Tc).

The condition of the minimum conversion time is when the value of Ts = 150 ns and Tc = 350 ns (AVCC ≥ 4.5V). Ensure

that it satisfies the value of sampling time (Ts) and compare clock cycle (Tcck). For setting*4

of sampling time and

compare clock cycle, see "Chapter 1-1: A/D Converter" in "FM4 Family Peripheral Manual Analog Macro Part

(MN709-00003).” The register setting of the A/D converter is reflected by the peripheral clock timing. The sampling and

compare clock are set at base clock (HCLK).

2: A necessary sampling time changes by external impedance. Ensure that it sets the sampling time to satisfy (Equation 1).

3: The compare time (Tc) is the value of (Equation 2).

4: The register setting of the A/D converter is reflected by the timing of the APB bus clock. The sampling clock and

compare clock are set in the base clock (HCLK). For more information about the APB bus number to which the A/D

converter is connected, see "10. Block Diagram" in this data sheet.



(Equation 1) Ts ≥ (RAIN + Rext) × CAIN × 9

Ts: Sampling time

RAIN: Input resistance of A/D = 1.2 kΩ at 4.5V ≤ AVCC ≤ 5.5V

Input resistance of A/D = 1.8 kΩ at 2.7V ≤ AVCC < 4.5V

CAIN: Input capacity of A/D = 12.05 pF at 2.7V ≤ AVCC ≤ 5.5V

Rext: Output impedance of external circuit

(Equation 2) Tc = Tcck × 14

Tc: Compare time

Tcck: Compare clock cycle

Rext Rin

Cin

Analog signal

source

AN00 to AN31

Analog input pin Comparator

RAIN

CAIN



Definition of 12-bit A/D Converter Terms

Resolution : Analog variation that is recognized by an A/D converter.

Integral Nonlinearity : Deviation of the line between the zero-transition point

(0b000000000000 ←→ 0b000000000001) and the full-scale transition point

(0b111111111110 ←→ 0b111111111111) from the actual conversion characteristics.

Differential Nonlinearity: Deviation from the ideal value of the input voltage that is required to change

the output code by 1 LSB.

Integral Nonlinearity of digital output N = VNT - {1LSB × (N - 1) + VZT}

[LSB] 1LSB

Differential Nonlinearity of digital output N = V(N + 1) T - VNT

- 1 [LSB] 1LSB

1LSB = VFST - VZT

4094

N: A/D converter digital output value.

VZT: Voltage at which the digital output changes from 0x000 to 0x001.

VFST: Voltage at which the digital output changes from 0xFFE to 0xFFF.

VNT: Voltage at which the digital output changes from 0x(N − 1) to 0xN.

Integral Nonlinearity Differential Nonlinearity

Dig

ital o

utp

ut

Dig

ital o

utp

ut

Actual conversion

characteristics Actual conversion

characteristics

Ideal characteristics (Actually-

measured

value)

Actual conversion

characteristics

Actual conversion characteristics

(Actually-measured

value)

(Actually-measured value)

Ideal characteristics (Actually-measured

value)

Analog input Analog input

(Actually-measured

value)

0x001

0x002

0x003

0x004

0xFFD

0xFFE

0xFFF

AVss AVRH AVss AVRH

0x(N-2)

0x(N-1)

0x(N+1)

0xN

{1 LSB(N-1) + VZT}

VNT

VFST

VZT

VNT

V(N+1)T



14.6 12-bit D/A Converter

Electrical Characteristics for the D/A Converter

(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V)



Resolution -

DA0,

DA1

- - 12 bit

Conversion time tc20 0.56 0.69 0.81 μs Load 20 pF

tc100 2.79 3.42 4.06 μs Load 100 pF

Integral nonlinearity* INL - 16 - + 16 LSB

Differential nonlinearity* DNL - 0.98 - + 1.5 LSB

Output voltage offset VOFF - - + 10 mV When setting 0x000

- 20.0 - + 1.4 mV When setting 0xFFF

Analog output impedance RO 3.10 3.80 4.50 kΩ D/A operation

2.0 - - MΩ When D/A stop

Power supply current* IDDA

AVCC

260 330 410 μs D/A 1ch operation AVCC = 3.3V

400 510 620 μs D/A 1ch operation AVCC = 5.0V

IDSA - - 14 μs When D/A stop

*: During no load



14.7 USB Characteristics

(VCC = AVCC = 2.7V to 5.5V, USBVCC0 = USBVCC1 = 3.0V to 3.6V, VSS = AVSS = 0V)


Name Conditions

Value Unit Remarks

Min Max

Input

characteristics

Input "H" level voltage VIH

UDP0/

UDM0,

UDP1/

UDM1

- 2.0 USBVCC

+ 0.3 V *1

Input "L" level voltage VIL - VSS - 0.3 0.8 V *1

Differential input sensitivity VDI - 0.2 - V *2

Different common mode

range VCM - 0.8 2.5 V *2

Output

characteristics

Output "H" level voltage VOH External pull-down

resistance = 15 kΩ 2.8 3.6 V *3

Output "L" level voltage VOL External pull-up

resistance = 1.5 kΩ 0.0 0.3 V *3

Crossover voltage VCRS - 1.3 2.0 V *4

Rise time tFR Full-Speed 4 20 ns *5

Fall time tFF Full-Speed 4 20 ns *5

Rise/fall time matching tFRFM Full-Speed 90 111.11 % *5

Output impedance ZDRV Full-Speed 28 44 Ω *6

Rise time tLR Low-Speed 75 300 ns *7

Fall time tLF Low-Speed 75 300 ns *7

Rise/fall time matching tLRFM Low-Speed 80 125 % *7

1: The switching threshold voltage of the single-end-receiver of USB I/O buffer is set as within VIL (Max) = 0.8V,

VIH (Min) = 2.0V (TTL input standard).

There is some hysteresis applied to lower noise sensitivity.

2: Use differential-receiver to receive USB differential data signal. Differential-receiver has 200 mV of differential input

sensitivity when the differential data input is within 0.8V to 2.5V to the local ground reference level.

Above voltage range is the common mode input voltage range.

Common mode input voltage [V]

Min

imum

diffe

ren

tia

l in

pu

t

se

nsitiv

ity [

V]



3: The output drive capability of the driver is below 0.3V at low state (VOL) (to 3.6V and 1.5 kΩ load), and 2.8V or

above (to the VSS and 1.5 kΩ load) at high state (VOH).

4: The cross voltage of the external differential output signal (D +/D −) of USB I/O buffer is within 1.3V to 2.0V.

5: They indicate rise time (Trise) and fall time (Tfall) of the full-speed differential data signal.

They are defined by the time between 10% and 90% of the output signal voltage.

For full-speed buffer, Tr/Tf ratio is regulated as within ± 10% to minimize RFI emission.

VCRS specified range

Rise time Falling time



6: USB Full-speed connection is performed via twisted-pair cable shield with 90Ω ± 15% characteristic impedance

(differential mode).

USB standard defines that the output impedance of the USB driver must be in the range from 28Ω to 44Ω. So, a

discrete series resistor (Rs) addition is defined in order to satisfy the above definition and keep balance.

When using this USB I/O, use it with 25Ω to 30Ω (recommended value 27Ω) series resistor Rs.

Rs series resistor 25Ω to 30Ω

Series resistor of 27Ω (recommendation value) must be added.

And, use "resistance with an uncertainty of 5% by E24 sequence.”

7: They indicate rise time (Trise) and fall time (Tfall) of the low-speed differential data signal.

They are defined by the time between 10% and 90% of the output signal voltage.

Note:

− See "Low-Speed Load (Compliance Load)" for conditions of external load.

Mount it as external resistance.

28Ω to 44Ω Equiv. Imped.

28Ω to 44Ω Equiv. Imped.

Rise time Falling time



Low-Speed Load (Upstream Port Load) - Reference 1

Low-Speed Load (Downstream Port Load) - Reference 2

Low-Speed Load (Compliance Load)

CL=50pF to 150pF

CL=50pF to 150pF

CL=

200pF to 600pF

CL=

200pF to 600pF

CL=200pF to 450pF

CL=200pF to 450pF



14.8 Low-Voltage Detection Characteristics

14.8.1 Low-Voltage Detection Reset



Detected voltage VDL - 2.46 2.55 2.64 V When voltage drops

Released voltage VDH - 2.51 2.60 2.69 V When voltage rises

14.8.2 Interrupt of Low-Voltage Detection



Detected voltage VDL SVHI = 0011

2.80 2.90 3.00 V When voltage drops

Released voltage VDH 2.90 3.00 3.11 V When voltage rises






















LVD stabilization wait time TLVDW - - - 6000×tCYCP* μs

*: tCYCP indicates the APB2 bus clock cycle time.



14.9 MainFlash Memory Write/Erase Characteristics

(VCC = 2.7V to 5.5V)

Parameter Value


Sector erase time

Large Sector - 0.7 3.7 s

Includes write time prior to internal erase

Small Sector - 0.3 1.1 s

Half word (16-bit)

write time

Write cycles < 100 times - 12

100 μs Not including system-level overhead time

Write cycles > 100 times 200

Chip erase time* - 13.6 68 s Includes write time prior to internal erase

*: It indicates the chip erase time of 1MB MainFlash memory

For devices with 1.5 MB or 2 MB of MainFlash memory, two erase cycles are required.

See “3.2.2 Command Operating Explanations” and “3.3.3 Flash Erase Operation” in this product's “Flash

Programming Manual” for the detail.

Write Cycles and Data Retention Time

Erase/Write Cycles (Cycle) Data Retention Time (Year)

1,000 20*

10,000 10*

100,000 5*

*: This value comes from the technology qualification (using Arrhenius equation to translate high temperature

acceleration test result into average temperature value at + 85°C).

14.10 Dual Flash Memory Write/Erase Characteristics

It is the same write/erase characteristics as the MainFlash memory.

See “3.6 Dual flash mode” in this product's “Flash Programming Manual” for the detail of dual flash mode.



14.11 Standby Recovery Time

14.11.1 Recovery cause: Interrupt/WKUP The time from the interrupt occurring to the time of program operation start is shown.

Recovery count time

(VCC = 2.7V to 5.5V, VSS = 0V)


Unit Remarks Typ Max*

Sleep mode

Ticnt

HCLK×1 μs

High-speed CR timer mode

Main timer mode

PLL timer mode

40 80 μs

Low-speed CR timer mode 450 900 μs

Sub timer mode 896 1136 μs

RTC mode

Stop mode

(High-speed CR/Main/PLL run mode return)

316 581 μs

RTC mode

Stop mode

(Low-speed CR/sub run mode return)

270 540 μs

Deep standby RTC mode with RAM retention

Deep standby stop mode with RAM retention

365 667 μs without RAM

retention

365 667 μs with RAM retention

*: The maximum value depends on the built-in CR accuracy.

Example of Standby Recovery Operation (when in external interrupt recovery*)

Ext.INT

Ticnt

Interrupt factoraccept

CPUOperation

Start

Active

Interrupt factorclear by CPU

*: External interrupt is set to detecting fall edge.



Example of Standby Recovery Operation (when in internal resource interrupt recovery*)

Internal Resource INT

Ticnt

Interrupt factoraccept

CPUOperation

Start

Active

Interrupt factorclear by CPU

*: Depending on the standby mode, interrupt from the internal resource is not included in the recovery cause.

Notes:

− The return factor is different in each low-power consumption mode. See "Chapter 6: Low Power

Consumption Mode" and "Operations of Standby Modes" in “FM4 Family Peripheral Manual Main

Part (MN709-00001).”

− The recovery process is unique for each operating mode. See "Chapter 6: Low Power

Consumption Mode" in "FM4 Family Peripheral Manual Main Part (MN709-00001).”



14.11.2 Recovery Cause: Reset The time from reset release to the program operation start is shown.

Recovery Count Time

(VCC = 2.7V to 5.5V, VSS = 0V)


Unit Remarks Typ Max*

Sleep mode

Trcnt

155 266 μs

High-speed CR timer mode

Main timer mode

PLL timer mode

155 266 μs

Low-speed CR timer mode 315 567 μs

Sub timer mode 315 567 μs

RTC mode

Stop mode 315 567 μs

Deep standby RTC mode with RAM retention

Deep standby stop mode with RAM retention

336 667 μs without RAM

retention

336 667 μs with RAM retention

*: The maximum value depends on the built-in CR accuracy.

Example of Standby Recovery Operation (when in INITX recovery)

INITX

Trcnt

Internal RST

CPUOperation

Start

RST Active Release



Example of Standby Recovery Operation (when in internal resource reset recovery*)

Internal Resource RST

Trcnt

Internal RST

CPUOperation

Start

RST Active Release

*: Depending on the low-power consumption mode, the reset issue from the internal resource is not included in the

recovery cause.

Notes:

− The return factor is different in each low power consumption mode.

See "Chapter 6: Low Power Consumption Mode" and "Operations of Standby Modes" in “FM4

Family Peripheral Manual Main Part (MN709-00001).”

− The recovery process is unique for each operating mode. See "Chapter 6: Low Power

Consumption Mode" in "FM4 Family Peripheral Manual Main Part (MN709-00001).”

− When the power-on reset/low-voltage detection reset, they are not included in the return factor.

See “14.4.8 Power-On Reset Timing.”

− In recovering from reset, CPU changes to high-speed run mode. In the case of using the main

clock and PLL clock, they need further main clock oscillation stabilization wait time and oscillation

stabilization wait time of main PLL clock.

− Internal resource reset indicates Watchdog reset and CSV reset.



15. ORDERING INFORMATION

Part number Package

S6E2CC8H0AGV20000

Plastic・LQFP (0.5-mm pitch), 144 pin

(FPT-144P-M08) S6E2CC9H0AGV20000

S6E2CCAH0AGV20000

S6E2CC8J0AGV20000


(FPT-176P-M07) S6E2CC9J0AGV20000

S6E2CCAJ0AGV20000

S6E2CC8J0AGB10000


(LBE192) S6E2CC9J0AGB10000

S6E2CCAJ0AGB10000

S6E2CC8L0AGL20000


(FPT-216P-M01) S6E2CC9L0AGL20000

S6E2CCAL0AGL20000



16. PACKAGE DIMENSIONS

144-pin plastic LQFP Lead pitch 0.50 mm

Package width ×package length

20.0 × 20.0 mm

Lead shape Gullwing

Sealing method Plastic mold

Mounting height 1.70 mm MAX

Weight 1.20 g

Code(Reference)

P-LFQFP144-20×20-0.50

144-pin plastic LQFP(FPT-144P-M08)

(FPT-144P-M08)

C 2003-2010 FUJITSU SEMICONDUCTOR LIMITED F144019S-c-4-8

Details of "A" part

0.25(.010)

(Stand off)(.004±.004)0.10±0.10

(.024±.006)0.60±0.15

(.020±.008)0.50±0.20

1.50+0.20–0.10

+.008–.004.059

0°~8°

0.50(.020)

"A"

0.08(.003)

0.145±0.055(.006±.002)

LEAD No. 1 36

INDEX

37

72

73108

109

144

0.22±0.05(.009±.002)

M0.08(.003)

22.00±0.20(.866±.008)SQ

(Mounting height)

* 20.00±0.10(.787±.004)SQ

Dimensions in mm (inches).Note: The values in parentheses are reference values.

Note 1) *:Values do not include resin protrusion.Resin protrusion is +0.25(.010)Max(each side).

Note 2) Pins width and pins thickness include plating thickness.Note 3) Pins width do not include tie bar cutting remainder.





24.0 × 24.0 mm

Lead shape Gullwing



Code(Reference)

P-LQFP-0176-2424-0.50


(FPT-176P-M07)


Details of "A" part

0°~8°

0.50±0.20(.020±.008)0.60±0.15

(.024±.006)

0.25(.010)

(Stand off)(.004±.004)0.10±0.10

1.50+0.20–0.10

+.008–.004.059

(Mounting height)

0.08(.003)

(.006±.002)0.145±0.055

"A"

INDEX

1LEAD No. 44

45

88

89132

133

176

0.50(.020) 0.22±0.05(.009±.002)

M0.08(.003)

*24.00±0.10(.945±.004)SQ

26.00±0.20(1.024±.008)SQ


Note 1) * : Values do not include resin protrusion.Resin protrusion is +0.25(.010)Max(each side).

Note 2) Pins width and pins thickness include plating thicknessNote 3) Pins width do not include tie bar cutting remainder.





24.0 × 24.0 mm

Lead shape Gullwing



Code(Reference)

P-LFQFP216-24×24-0.40


(FPT-216P-M01)


"A"

0.18±0.05(.007±.002)

M0.07(.003)0.145±0.055(.006±.002)

0.08(.003)

0~8°

0.25(.010)

Details of "A" part

0.40(.016)

INDEX

1 54

108

55

162 109

216

163

26.00±0.20(1.024±.008)SQ

(Stand off)(.024±.006)0.60±0.15 0.10±0.05

(.004±.002)

.059 –.004+.008

–0.10+0.20

1.50(Mounting height)

LEAD No.

* 24.00±0.10(.945±.004)SQ


Note 1) * : These dimensions do not include resin protrusion.Note 2) Pins width and pins thickness include plating thickness.Note 3) Pins width do not include tie bar cutting remainder.



PACKAGE

JEDEC

D X E

SYMBOL

A

A1

D

E

D1

E1

MD

ME

n

O b

eE

eD

MIN.

---

0.25

0.35

A1, A14, P1, P14

LBE 192

N/A

12.00mm X 12.00mm PACKAGE

NOM.

---

---

12.00 BSC

12.00 BSC

10.40 BSC

10.40 BSC

14

14

192

---

0.80 BSC

0.80 BSC

0.00 BSC

MAX.

1.45

---

0.55

NOTE

PROFILE

BALL HEIGHT

BODY SIZE

BODY SIZE

MATRIX FOOTPRINT

MATRIX FOOTPRINT

MATRIX SIZE D DIRECTION

MATRIX SIZE E DIRECTION

BALL COUNT

BALL DIAMETER

BALL PITCH

BALL PITCH

SOLDER BALL PLACEMENT

DEPOPULATED SOLDER BALLSLOCATIONS

SD

gs5036-1-lbe192 / 6.16.14

NOTES:

DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5-2009.THIS OUTLINE CONFORMS TO JEP 95, SECTION 4.5.ALL DIMENSIONS ARE IN MILLIMETERS.

BALL POSITION DESIGNATION PER JEP 95, SECTION 3, SPP-010.

e REPRESENTS THE SOLDER BALL GRID PITCH.

SYMBOL “MD” IS THE BALL MATRIX SIZE IN THE “D” DIRECTION. SYMBOL “ME” IS THE BALL MATRIX SIZE IN THE “E” DIRECTION. n IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIXSIZE MD X ME.

DIMENSION “b” IS MEASURED AT THE MAXIMUM BALL DIAMETER IN APLANE PARALLEL TO DATUM C.

SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B ANDDEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW.WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROWSD OR SE = 0WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROWSD OR SE = e/2

A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK,METALLIZED MARK INDENTATION OR OTHER MEANS.

“+” INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS.

1.

2.

3.

4.

5.

6

7

8

9.SE

INDEX MARK IS OPTIONAL.10



17. Major Changes

Page Section Change Results

Revision 0.1

- - Initial release









Colophon

The products described in this document are designed, developed and manufactured as contemplated for general use,

including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not

designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless

extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury,

severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control,

mass transport control, medical life support system, missile launch control in weapons systems), or (2) for any use in which

chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable

to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products.

Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such

failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and

prevention of over-current levels and other abnormal operating conditions. If any products described in this document

represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law

of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the

respective government entity will be required for export of those products.

Trademarks and Notice

The contents of this document are subject to change without notice. This document may contain information on a Spansion

product under development by Spansion. Spansion reserves the right to change or discontinue work on any product without

notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy,

completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other

warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind arising out of the use of

the information in this document.

Copyright © 2014 Spansion LLC. All rights reserved. Spansion®, the Spansion logo, MirrorBit

®, MirrorBit

® Eclipse

TM,

ORNANDTM

, Easy DesignSimTM

, TraveoTM

and combinations thereof, are trademarks and registered trademarks of Spansion

LLC in the United States and other countries. Other names used are for informational purposes only and may be trademarks

of their respective owners.

Documents

S6E2CC Series - cdn.rowleydownload.co.ukcdn.rowleydownload.co.uk/arm/packages/targets/FM4/...Spansion Inc. issues data sheets with advance information or preliminary designations to