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TiN

HfO2

TiOx

Ti

TiN

Ti/SiO2/Si substrate

TiN(sputtering)

Ti (sputtering)

 HfO2 (ALD)

TiN (sputtering)

Form TiOx 

-1.5 -1.0 -0.5 0.0 0.5 1.0 1.510

-6

10-5

10-4

10-3

   C  u  r  r  e  n   t   (   A   )

Top Voltage (V)

C.C.Vreset , Ireset,max

Vstop

Vset

The Physical Insights Into an Abnormal Erratic Behavior in the

Resistance Random Access Memory Y. J. Huang1, Steve S. Chung1,*, H. Y. Lee2, Y. S. Chen2, F. T. Chen2, P. Y. Gu2, and M. -J. Tsai2 

1Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan

* Tel: (886)-3-573-1830, Email: schung@cc.nctu.edu.tw

2 Electronics and Optoelectronics Research Laboratory, Industrial Technology Research Institute, Taiwan 

 Abstract  —  The voltage ramping rate during the forming and set-reset process is strongly related to the formation of soft-

breakdown (SBD) paths. In this paper, we examined the effect of

two different operation methods in RRAM, including sweep and

pulse modes. The RTN analysis has been utilized to examine their

influences on the SBD paths. For the first time, we found a

different behavior of the RTN currents generated by two

different modes of operation. Results show that more SBD paths

are created during the pulse mode which led to the instability of

switched resistance, and induced the erratic bit during the

readout of RRAM.

 Keywords- RRAM, Soft-breakdown, Random Telegraph Noise,

Resistive Switching Mechanism, Multi-level Operation 

I. 

I NTRODUCTION

The switching mechanism of HfOx based RRAM has been

considered as the formation and rupture of the soft-breakdown

(SBD) paths under applying bias, which are formed along the

grain boundaries (GBs) [1]. Under certain operating conditions,

traps are generated in the dielectric and strongly influence the

SBD path. On the other hand, the Random Telegram Noise

(RTN) method is one of the great techniques to study the

 behavior of the oxide traps. Recently, by measuring the gate

current (IG) RTN fluctuation, it has been able to explain theSBD behavior of high-κ  dielectric MOSFET [2]. Few reportshave then been developed to understand the behavior of

switching in RRAMs by RTN [3]. Further understanding of the

traps becomes important for the reliable operation of RRAM. It

was found that different voltage ramping rates during operation

cause different distributions of the SBD paths. In this paper, we

will utilize the RTN approach, to analyze the carrier

trapping/de-trapping in the RRAM devices. By observing the

 bias dependence of capture and emission time, the defect

location could be identified, and the carrier trapped/de-trapped

mechanisms will be investigated. The impact on the RRAM

readout error will then be demonstrated.

II. 

DEVICE PREPARATION 

The structure of RRAM was the TiN/TiOx/HfOx/TiN

stack. The HfO2  thin film was deposited by atomic layer

deposition (ALD), while all the other thin films were

deposited by sputtering methods, as shown in Fig. 1. The

device area is 0.48x0.48 μm2, and the thickness of HfO2 layer

is 10 nm. The TiOx layer was originally titanium metal layer.

After the deposition, the titanium and oxide formed an

imperfect titanium oxide layer [4].

Fig. 1 The cross section and the major process flow of the

experimental RRAM device.

III. CHARACTERISTICS OF MULTI-LEVEL OPERATION 

In this section, we will demonstrate the operation methodsof resistive random access memory to achieve multi-levelstorage and the associated characteristics. One method is sweepoperation and the other one is pulse operation. Also, we willdiscuss the reliability issues for these two different methods.

Fig. 2 Typical current-voltage characteristics of a bipolar RRAM.

C.C. represents the compliance current. Vstop is the maximum

negative sweep voltage. Vreset or Ireset,max are the voltage or current at

which reset takes place. Vset is the voltage at which set takes place. 

 A.  The Sweep Operation

The RRAM structure that we used is suitable for bipolaroperation. In Fig. 2, when RRAM is switched to LRS, wedefine Vset as the turn on voltage, and I set as the corresponding

current. For the memory device, we limit the RRAM currentduring the set and forming process by Agilent 4156C with thecompliance current (C.C.). When RRAM is switched to HRS,we define Vreset  as the turn off voltage and Ireset  as thecorresponding current. Also, we define the maximum negativevoltage as Vstop. So, during the set operation by the sweep, thewaveform in Fig. 3(a) was used, and when the RRAM currentreaches the compliance current that we set, this current will befixed by Agilent 4156C. Hence, we can achieve multi-levelstorage in the low resistance state by changing different

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Forming

0V

4V

0V

Vhigh

0V

-2V

Pulse width

SET

RESET

Forming

0 V

4 V

Terminated

as reaching

Compliance Current

(C.C.)

0 V

Vstop

without

C.C.

+1.5 V

0 V

with

C.C.

SET

RESET

C ase 1: S weep mode Cas e 2: Pulse mode

1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6

0.8

1.0

1.2

  r  e  s   i  s   t  a  n  c  e

   (   k 

   )

 VSET

 (V)

pulse width : 1x10-8

 sec

VSET

10-7

10-6

20

40

60

80

100

  r  e  s   i  s   t  a  n  c  e

   (   k 

   )

tRESET

 ( sec )

tRESET

0V

-2V

HfO2

SBD path

T.E. B.E.

Empty

HfO2

SBD path

T.E. B.E.

Filled

(a) (b)

compliance currents. So, during the set operation by the sweep,the waveform in Fig. 3 (left) was used until a CC limit isreached. For the high resistance state (HRS), RRAM device

after a negative voltage sweep now changes the resistance state.The multi-level storage can be achieved by changing differentstop voltage Vstop. 

Fig. 3 Two different operation modes of RRAM: (left) case 1-sweep

mode, (right) case 2- pulse mode.

 B. 

The Pulse Operation

Besides the sweep operation, the pulse operation is

another operating method for RRAM device. The same as

sweep operation, we add a positive bias to RRAM top

electrode to accomplish the set process, Fig. 3 (right).

The multi-level operation is achieved by changing the

 pulse amplitudes. The pulse width is 1x10-8 sec, by changing

the pulse amplitudes from 1.5 V to 2.5 V. Then, we will get

different resistance levels, as shown in Fig. 4(a). The

resistance decreases as the pulse voltage increases. So, the

RRAM resistances at the low resistance state can be controlled

 by different pulse voltages to achieve multi-level storage.

Different from the set operation, to achieve multi-levelstorage of high resistance state (HRS), we control the width of

the negative pulse. The pulse amplitude should be selected

appropriately. If the pulse amplitude is too large, the RRAM

device will see reverse breakdown and this device will be

failed during the switching. In this case, we fix the pulse

voltages where Vlow  is 0 V and Vhigh  is -2 V; and then, we

change the pulse widths from 5x10-8 to 1x10-6 sec. As shown

in Fig. 4(b), the multi-level storage is achieved by changing

the pulse widths.

Fig. 4 (a) The pulse voltage dependence of the resistance at low resistance

state. The positive pulse width is 1x10-8 sec. (b) The pulse widthdependence of the resistance at high resistance state. The negative pulse

amplitude is -2 V.

IV.  RTN MEASUREMENTS OF TRAPS 

In this section, we will discuss the random telegraph

noise of RRAM. The amplitude, capture, and emission time

are the critical parameters of the random telegraph noise

(RTN) behavior and depend on the trap properties, such as the

trap depth into dielectrics, and the trap energy apart from

conduction band. We can extract the trap position by

analyzing the capture and emission time. Then, we will focuson the random telegraph noise behavior which was operated

 by the case 1 and case 2 as aforementioned. By investigating

the current variation, we can understand what happened in the

soft breakdown paths in the RRAM device.

 A. 

General Equation of RTN

A two-level RTN of the dielectric current between the top

and bottom electrodes can be measured such that the trap

 properties can be well observed. In Fig. 5(a), when the trap is

empty, a huge current through the dielectric can be measured;

in contrast, RRAM current becomes smaller as an electroncaptured in the trap site, as illustrated in this figure. The

reason is that electron trapped will screen the proximity of the

trap and hence suppress the current. While if the trap is filled

 by electrons, Fig. 5(b), a smaller current will be expected. A

typical result of the measured RTN signal is shown in Fig. 5(a),

where the current fluctuation (∆I) is caused by the trapslocated in the dielectric. The two characteristic time in the

above measured current can be defined: (1) capture time, τc forhigh current states, and (2) emission time, τe  for low currentstates, as defined in Fig. 6(a) respectively, where the currents,

I versus time, at different VG  caused by the trap are

demonstrated. The current magnitude is about several nano-

Ampere (nA) and noise amplitude is about 25% of themaximum current through the dielectric.

Fig. 5 (a) The schematic of the current instability caused by theelectron trapping/detrapping (a) Trap empty with large current

through the MIM dielectric. (b) Trap filled state with smaller

current.

 B. 

 Depth of the Traps

The energy band diagram of the metal-insulator-metal

(MIM) structure with the trap energy level E T  and depth  Z T  is

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ln B cT ox

e

k T  Z T 

q V 

τ  

τ  ∂

∂ ⎡ ⎤⎛ ⎞= ⋅⎜ ⎟⎢ ⎥∂   ⎝ ⎠⎣ ⎦

( )[ ]T k  E  E   B F T e

c /exp   −=τ  

τ  

5 65

6

7

8

ILOW

 

c

IHIGH

 

   C  u  r  r  e  n   t   (  n   A   )

Time ( sec )

 

I

 

e

ECd -ET

ZT

 0

EF

TOX

(a)   (b)

0.1 0.2 0.310

-3

10-2

10-1

100

101

102

-0.3 -0.2 -0.110

-1

100

101

τ

  c ,τ

  e   (  s  e  c   )

 c (sec)

 e (sec)

Top Voltage, Vtop ( V )

 

HfO2T.E. B.E.

1 2

ZT(Case 1) = 1.86 nm

ZT(Case 2) = 3.35 nm

(a)   (b)   (c)

100

101

102

103

104

105

106

107

108

103

104

 RESET_1.5V

 RESET_1.25V

 RESET_1.1V

 RESET_1.0V

 SET_200uA

 SET_250uA

 SET_350uA

 SET_500uA

 SET_650uA

 

  r  e  s   i  s   t  a  n  c  e   ( )

Time (sec)

10 years

100

101

102

103

104

105

106

107

108

1

1.5

10

100RESET_1E-6s

RESET_5E-7s

RESET_1E-7s

RESET_5E-8s

SET_1.5V

SET_1.7V

SET_1.9V

SET_2.1V

SET_2.3V

SET_2.5V

  r  e  s   i  s   t  a  n  c  e   (   k 

   )

Time ( sec )

10 years

(a)

(b)

L2L3L1

L4

shown in Fig. 6(b). The fractional occupancy of the oxide trap

is governed by

( )exp / .c T F Be

 E E k T τ  

τ  

= −⎡ ⎤⎣ ⎦   (1)

The expression for the capture time and emission time in terms

of the position of the trap can be derived as the following:

( )0lnc

 B Cd T x

ek T E E E  

τ  

τ  

⎛ ⎞= Φ − − +⎡ ⎤⎜ ⎟   ⎣ ⎦⎝ ⎠

  (2a)and

| | .T  x oxox

 z  E q V 

T =   (2b)

Here, Φ0  is the difference between the work function of TiN

and electron affinity of HfO2, E Cd  is the conduction band edge

of the HfO2, q is the elementary charge, T ox is oxide thickness,

 Z T   is the position of the trap in the oxide from the top

electrode, and V ox is the oxide voltage drop which is the same

as the applied bias. By differentiating Eq. (4.5) with respect to

the applied bias, the Z T  is derived as

ln . B c

T oxe

k T 

 z T q V 

τ  

τ  

∂   ⎡ ⎤⎛ ⎞

= ⋅⎜ ⎟⎢ ⎥∂   ⎝ ⎠⎣ ⎦   (3)

Fig. 6 (a) The parameters of the measured RTN with a fluctuation of twolevel currents, IHIGH and ILOW. (b) Energy band diagram of the MIMstructure considering the trap energy level ET and the depth ZT, from

which the location of traps can be identified.

C. RTN Behavior for Different Operation Modes

To examine the correlation between forming-set-reset and

SBD generation[5], two different operation methods, i.e., the

aforementioned sweep and pulse modes were performed, in

which Case 1 is the sweep mode and Case 2 is the pulse mode.

From the above understanding, first the τc-τe  plots can beobtained from the measured top voltages, Vtop. Further, the

trap location can be determined by Eq. (3) [2]. Depending on

the operation mode, the τc-τe  plots show different behaviors. Namely, the traps were generated more close to the top

electrode for sweep operation, while they are much deeper into

the HfO2  for the pulse operation. Their mechanisms are

different, as can be seen from the τc-τe plot in Figs. 7 (a) and(b), in which the escape of electrons out of the trap is based on

the tunneling, while the electrons escape in Case 2 is due to

the thermionic emission since the electrons can not escape via

the tunneling for the much deeper traps, Fig. 7(b).

Fig. 7 Variation of τc and τe when the voltage on the top electrodeincreases: (a) Case 1- the sweep mode and (b) Case 2- the pulse

mode. (c) The extracted trap depths for two different traps in case1 (ZT= 1.86nm) and case 2 (ZT= 3.35nm).

Fig. 8 (a) Data retention characteristics of multi-level states by the sweep

mode (case 1). The results predict excellent 10 years lifetime. (b) Dataretention characteristics of multi-level states by the pulse mode (case 2).

The results project excellent 10 years lifetime for LRS state, but not for

HRS where erratic bits were observed as a result of the window closure.

C.  The Observation of Erratic Bit forMulti-Level Operation

 Next, we will discuss the correlation between the generated

traps using different operating schemes and their impacts on

the multi-level operation.

For the data retention measurement, we tried the multi-level operation by the sweep method (case 1). The LRS datawriting for five resistance levels has been demonstrated byvarying the compliance currents of the sweep process. In Fig.8(a), the LRS multi-level resistance is achieved by fivecompliance currents (200 µA ~ 650 µA) over a long period oftime at 100oC, and the HRS multi-level storage was obtained by using various stop voltages (-1.0V to -1.5V). The prediction of 10-year lifetime on this plot shows excellent dataretention characteristics.

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 reset_1E-7s

 reset_2E-7s

 reset_5E-7s

 reset_8E-7s

100

101

102

103

104

10

15

20

25

30

   R  e  s

   i  s   t  a  n  c  e   (   k 

Time ( sec )2 3 4

1.6

1.8

2.0

2.2

   C  u  r  r  e  n   t   (µ   A   )

 

Time ( sec )

 I/I = 37%

(a)   (b)

(a)   (b)

0

1

2

3

∆

   I   (  n   A   )

0.05 0.06 0.07 0.08 0.09 0.100

10

20

30

∆

   I   /   I   H   I   G   H   (   %    )

| Top Voltage | ( V )

20

40

∆

   I   (  n   A   )

0.16 0.18 0.200.22 0.24 0.26 0.28 0.300

2

4

6

∆

   I   /   I   H   I   G   H   (   %    )

| Top Voltage | ( V )

(a) (b)

In comparison, the multi-level operation by the pulsemode was demonstrated in Fig. 8(b). For the low resistancestate (LRS), there are six levels which are operated bydifferent pulse amplitudes at a fixed pulse width during the setoperation. Also, for the high resistance state (HRS), we usedfour levels which are achieved by different pulse widths (Fig.3) during the reset operation. As shown in Fig. 9(a), the highand low resistance states are separated more than one orderdifference, but some levels are overlapped. We do not see any problem to control the high and low resistance states in the beginning. But after 200 seconds baking (100 oC), the highresistance state becomes unstable. Here, it can be clearly seenthat the overlap between L2 and L3 was observed around 102 seconds, i.e., the window closure. By sensing the current, wefound it was caused by the random telegraph noise (RTN), asrevealed in Fig. 9(b). The ∆I/I is larger than 37 % and it mightcause the resistance unstable.

Fig. 9 (a) Erratic bit- the high resistance states overlapped witheach other. (b) By measuring the RTN current, a huge RTN signal

with ∆I/I over 37 % was observed, which is the origin of the erratic bit as seen in (a).

Fig. 10 The current variation amplitude versus different Vtop: ∆I and

∆I/I vs. Vtop after different operation modes. (a) sweep operation. (b)

 pulse operation.

The above observations are attributed to the difference in

the operation mode as well as the generated traps. To show

their discrepancies, the RTN currents are used to describe thedifferences, Figs.10 (a) and (b). For the sweep operation (i.e.,

the slower ramping rate), the SBD path will be generated

intensively at the weakest point first. After that, the other SBD

 paths increase near that point, as illustrated in Fig. 11(a). So,

the trap will screen most of the SBD paths. For the pulse mode

(i.e., the faster ramping rate), there are many weaker spots of

GBs which will create more disperse SBD paths during a

severe voltage jump, Fig. 11(b). So, more SBD paths of pulse

operation are generated than the sweep operation ones. The

latter will cause the instability of switched resistance, which

leads to the erratic bit during the readout, especially for multi-

level operation.

Fig. 11 Illustration of the SBD paths distribution after differentoperation modes. (a) Sweep operation- fewer SBD paths are created.

(b) Pulse operation- more disperse SBD paths are created such thatthe RTN signal shows a much larger influence to the current flow.

When the influence becomes larger, larger RTN signal tends to

induce the erratic bit in Fig. 9. 

V.  SUMMARY A ND CONCLUSIONS 

In summary, the grain boundaries in the dielectric layer

constitute a preferential leakage current path, which are then

transformed into the soft-breakdown (SBD) path during the

forming or set-reset process. The created SBD paths of fast

voltage ramping rate operation are more disperse than that of

the slower one. Different carrier trapping/detrapping

mechanisms have been observed from different operation

methods. Results show that the pulse mode operation exhibits

a more disperse SBD path which leads to the erratic bit during

the readout of RRAM for multi-level operation.

ACKNOWLEDGMENT

The first author would like to thank the Emerging Memoryteam of EOL, ITRI, Taiwan for the device fabrication.

R EFERENCES 

[1] 

G. Bersuker, D. C. Gilmer, D. Veksler, J. Yum, H. Park, S. Lian, L.Vandelli, A. Padovani, L. Larcher,K. McKenna, A. Shluger, V. Iglesias,M. Porti, M. Nafría, W. Taylor, P. D. Kirsch, and R. Jammy, “MetalOxide RRAM Switching Mechanism Based on Conductive FilamentMicroscopic Properties,” in  IEDM Tech. Dig., pp. 456 – 459, 2010.

[2] 

C. M. Chang, S. S. Chung et al., “The Observation in Trapping andDetrapping Effects in High-k Gate Dielectric MOSFETs by a New GateCurrent Random Telegraph Noise(IG RTN) Approach,” in IEDM Tech.

 Dig., pp. 787-790, December 15-17, 2008.

[3] 

M. Terai, Y. Sakotsubo, Y.Saito, S. Kotsuji, and H. Hada, “Effect of

Bottom Electrode of ReRAM with Ta2O5/TiO2  Stack on RTN andRetention,” in  IEDM Tech. Dig., pp. 775 – 778, 2009.

[4] 

H. -Y. Lee, P. -S. Chen, T. -Y. Wu, Y. -S. Chen, C. -C. Wang, P. -J.Tzeng, C. -H. Lin, F. Chen, C. -H. Lien, and M. -J. Tsai, “Low Powerand High Speed Bipolar Switching with A Thin Reactive Ti BufferLayer in Robust HfO2 Based RRAM,” in  IEDM Tech. Dig., pp. 297 –300, 2008.

[5] 

 N. Raghavan, K. -L. Pey, X. -Li,W. -H. Liu, X. Wu, M. Bosman, and T.Kauerauf “Very Low Reset Current for an RRAM Device Achieved inthe Oxygen-vacancy-controlled Regime,”  IEEE Electron Device Lett.,vol. 32, no. 6, pp. 716 – 718, 2011.

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