ROM BIST

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ROM BISTRAM BIST

Serial BIST for RAMsProcessor-Based RAM BISTRAM BISTs in SOCs Characteristics of todays SOC designs

Typically more than 30 embedded memories on a chipMemories scattered around the device rather than

concentrated in one location

Different types and sizes of memoriesMemories doubly embedded inside embedded coresTest access to these memories from only a few chip I/O

pins

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Built-in self-test (BIST) is considered the best solutionfor testing embedded memories within

SOCs

It offers a simple and low-cost means withoutsignificantly impacting performance

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General BIST Architecture

Test Circuit Under Test Response

Generator (CUT) Verification

Test Controller

EE, National Central Uni versity Jin-Fu L i 4

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ROM Functional Block Diagram

Inputs

Buffer

NOR/NANDDecoder(ROM Array)

Buffer

Outputs


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An Example of ROM BIST

Counter

RO

M

ControllerMISR

Go/No-Go Status


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Typical RAM BIST Architecture

Normal I/Os

Test Controller

Test Pattern

Generator

Go/No-Go

Comparator

Test

Collar

RAM


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RAM BIST

In general, two BIST approaches have beenproposed for the RAMs

FSM-based RAM BIST ROM-based RAM BIST

Controller

Generate control signals to the test patterngenerator & the memory under test

Test pattern generator (TPG) Generate the required test patterns and Read/Write signals

ComparatorEvaluate the response


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ROM-Based RAM BIST

The features of ROM-based BIST scheme The ROM stores test procedures for generating test patterns Self-test is executed by using BIST circuits controlled by the

microprogram ROM

A wide range of test capabilities due to ROMprogramming flexibility

The BIST circuits consists of the followingfunctional blocks Microprogram ROM to store the test procedure

Program counter which controls the microprogram

ROM

TPG Comparator


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ROM-Based RAM BIST Architecture

Normal I/Os

End Microprogram

ROM

TPG

Go/No-Go

Comparator

Te

stCollar

RA

M


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Normal I/Os

EndFSM

TPG

TestCo

llar

RA

M

Go/No-Go

Comparator


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FSM-Based RAM BIST

An example ofthe statediagram ofcontroller

W0 0 NOT last address?

R0

S1

NOT last address?

W1S

2

R1 S3 NOT last address?

W0 4

R0S

5NOT last address?

W1S

4

End S4EE, National Central Uni versity Jin-Fu L i 13

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Programmable RAM BIST

An example ofthe programmableRAM BIST

BSI

BSC

BRS

BGO

CLKBNS

Controller

Normal I/Os

CMD&T

PG

Test

TGO

ENACom

par

Collar

DONE tor

RAM


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FSM State Diagram of the Controller

Idle BRS=1

BSC=1

DONE=1 Shift_cmd

BSC=0

Get_cmd

Apply ENA=1

DONE=0


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Serial BIST

Todays telecommunication ICs often have a varietyif multiport memories on one chip

Typical RAM BISTs evaluate all the bits of amemory word in parallel as it is read

We can encounter significant problems when applyingthese BIST schemes to chips that have multipleembedded RAMs ofvarying sizes andportconfigurations The area cost of these BIST designs would be

unacceptably high

One better solution is a serial BIST technique To share BIST design among several RAMs


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Benefits of Serial BIST

Only a small amount of additional circuitry isrequired

Only a few lines are needed to connect the RAM to thetest controller

Several RAM blocks easily share the BISTcontroller hardware

The serial-access mode does not compromise theRAM cycle time

Existing memory designs do not need any modification touse the serial interfaceEE, National Central Uni versity Jin-Fu L i 19

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Serial-Data-Path Connection

dR

ow

Ci Ci+1ecoder

Column decoder

Latch Latch

Write

Read

BIST on To next test inputFrom previous output or serial input

or serial input

Ii Oi i+1 i+1EE, National Central Uni versity Jin-Fu L i 20

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Serial Shift Operation

An example of serial shift operations for thematchelement (R0W1)

Time Operation Serial Word Serial

in content out

101 00 00 00

010 00 0 0

1 0X X

0 X 0 0 0 0 X

1 R0 X 0 0 0 00

2 W1 1 1 0 0 0 0

3 R0 1 1 0 00 0

4 W1 1 1 1 0 0 0

5 R0 1 1 1 0 0 0

6 W1 1 1 1 1 0 0

7 R0 1 01 1 1 0

08 W1 1 1 1 1 1


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Serial March (SMarch)

Assume that a RAM has Wwords, and each wordcontains Cbits

A Read operation is denoted by R0, R1, orRx,depending on the expected value at the serial output(x=dot care)

For a write operation, the terms W0 orW1 are usedand only the serial input is forced to the valueindicated

The SMarch modified from March C- is asfollcows(RxW0)

C

(R0,W0)C

;(R0,W1)C

(R1,W1)C

(R1,W0)C(R0,W0)C; (R0,W1)C(R1,W1)C

(R1,W0)C

(R0,W0)C

; (R0,W0)C

(R0,W0)C


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Serial BIST Architecture

BIST GO Done

ControlData out

Data inAddress

Counters Controller

SO SI

lsb msb

C-1

Multiplexer MultiplexerCC

Address Data in Data out

RAM (Wwords ofCbits)

Timing

generator

Multiplexer

Control


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Sharing BIST in Daisy-Chain Style

BIST GO Done

CountersController Timing

SO SI generator

Address R d/Write

Test Collar Test Collar Test Collar

RAM1 RAM2 RAM3

Serial Interface Serial Interface Serial Interface

SI SO SI SO SI SO


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Sharing BIST in Parallel Style

BISTGO

Done

DeMux

SO SI Timing

Counters Controller generator

Address

Test Collar Test Collar Test Collar

RAM1 RAM2 RAM3

Serial Interface Serial Interface Serial Interface

SI SO SI SO SI SO


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BIST Using Data Decoding/Encoding

n

m wiren

n

m wire


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Processor-Based RAM BIST

Normal I/Os

Processor

TPG

Go/No-Go

Comparator

TestCollar

RA

M


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NTHU Processor-Programmable BIST

ADDR_cp

uADD

R

ADDR_bist

DATAO_sys DATA

O

DATAO_bist

Embedded Clock_cpuBIST core

Mux_sel On-chip Embedded

CPU bus Memory

Ctrl_cpuCtrl_bist control

DATAIDATAI_bist DATAI_sysDATAI_cpu

Source: Prof. C. W. Wu, NTHU

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BIST core

DATAO_cpu

RB

G

RA

LADDR_cpu

Address R

decorder AH

Lowest/highest addr

REA

DATAO_bist

Address ADDR_bist

counter

Up/down

RM

E

RI

R

RFLA

G

RED

Controller

Read/Write

Control

DATAI_bis

t

Match/unmatch

Data background

ComparatorDATAI_sys


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Data registers

Register Function

BG Store background data

AL Store lowest address

AH

Store highest address

ME Store current March element

IR Instruction register of BIST circuit

FLAG Status register of BIST circuit

ED Erroneous response of defective cell

EA Address of defective cell



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BIST procedure Source: Prof. C. W. Wu, NTHU

Performed by

test program

Test program write data background to RBG

Test program write lowest/highest address to RAL/RAH

Test program write March instructions to RME

Test program write START to RIR

(Wa) (Ra,Wa) (Ra,Wa) (Ra,Wa) (Ra,Wa) (Ra)

Performed by

BIST circuit

Compare yesData error

No

No March elementcomplete

yes

Write FINISH to RFLAG

Write ERROR to RFLAG

Write error response to RED

Write faulty addr to REA

Test program

take over


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SOC Testing

A typical SOC chip

ADC FPGA

Wrapper

CPU UDLDSP

Source Test Access Mechanism (TAM)

MPEG SRAM SRAM

Flash Memory

SinkTAM

DRAM

Source: Y. Zorian, et al.-ITC98


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SOC Test Access

ADC FPGAFlash

Off-chip Source/Sink

Memory 1. Pins determine bandwidthCPU UDL

Wrapper

DSP

Sink

2. More TAM area

SourceTAM TAM

3. Requires expensive ATE

MPEG SRAM SRAMDRAM

On-chip Source/Sink

1. Close to Core-under-test

ADC FPGAFlash

Wrapper Memory

CPUUDL

DSP

Sink Sink

2. Less TAM area

3.BIST IP area4.Requires lightweight ATE

SourceSource

MPEG SRAM SRAM DRAM

Source: Y. Zorian and E.J. Marinissen


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1500 Scalable Test Architecture

Source User Defined Parallel TAM Sink

TAM-in TAM-out TAM-in TAM-out

1500 Wrapper 1500 Wrapper

FinCore1

Fout FinCoreN

Fout

WSI WIR WSO WSI WIR WSO

WIP

User-DefinedTest Controller


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1500 Test Wrapper

Test stimuli WPI

Functional

data

WBR Core WB

R

WPO Test response

Functional

data

WBY

WSI WIRWSO

WSC


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Memories in SOCs

ADC FPGA

Flash Memory

CPUUDL DSP

SRAM SRAM SRAMDRAM

BIST

BIST

DRAMMPEG SRAM SRAM

BIST BIST

Non-BIST memory cores BIST-ready memory cores


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RAM BIST in SOCs

Memory cores in an SOC can be categorized intotwo types in term of testability BIST-ready memory coresNon-BIST memory cores

An SOC can contain tens or even hundreds ofmemory cores Although a BIST usually have only about 8

controlling pins

The total BIST controlling pins is huge if each BIST-readymemory cores has its own BIST controlling pins

The BIST controlling pins should be shared One solution is using memory BIST interfaceEE, National Central Uni versity Jin-Fu L i 37

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Sharing BIST Controlling Pins

ADC FPGA

CPU UDL

SRAM SRAMBISTMBI

MBI

MPEGBIST

SRAM

Flash Memory

DSP

DRAM

SRAM BISTMBI

MBI

BIST

SRAMDRAM


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Memory BIST Interface (MBI)


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Memory BIST Interface (MBI)

Instruction Register

Store the instructions RUN_BIST, RUN_DIAGN, EXPORT_STATUS, TAM_CONTROL

Bypass Register It is selected if the corresponding memory core is not tested

Monitor Register Monitor the error flag (indicating whether a memory fault is

detected or not)

Status Register Record the key status values, such as Fail output from the

BIST


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Testing Multiple Memories with MBI

Using RUN_BIST instruction, we can test multiplememory cores concurrently

When one or more BIST circuits detect faults, the primary MSO_N willbe high after N-K clock cycles if the concurrent output of the (K+1)through the N memory cores are fault free


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Sharing BIST Hardware

BIST controlling signals

BIST Controller

TPG &

Comparator

BIST Collar BIST Collar BIST Collar

RAM 1 RAM 2 RAM N


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RAM BIST Compiler



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1500-Compilant BIST

T

ConAP

Wra

TA

P

troller

pper

BIST RAM


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Programmable BISD for RAMs in SOCs

General test architecture

ATE

SO

CTAP controller

TAM

Wrapper

Processor + Test Program Memory

Embedded Memory Core

Source: Appello D., et. al. ITC03

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Test Processor

Processor

Wrapper

P1500Instructions

P1500

Output Data

ControlTest Program

Unit

Memory Address Bus

AdapterData Bus

Control Signals



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Control UnitManage the test program executionInclude an Instruction Register (IR) and

Program Counter (PC)

The control unit allows the correct update of someregisters located in Memory Adapter

This part simplifies the processor reuse in differentapplications without the need for any re-design


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Memory AdapterControl Address registers (Current_address)Control Memory registers

Current_data Received_data

Control Test registers Dbg_index, Step, Direction flag, and Timer registers

Result registers Status, Error, and Result registers

Some constant value registers Add_Max, Add_Min, DataBackGround, Dbg_max


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Processor instruction set

Instruction Meaning

SET_ADD Current_address Add_Max

Direction flagBACKWARD

RST_ADDCurrent_address Add_Min

Direction flagFORWARD

STORE_DBG

Current_data DataBackGround[Dbg_index]

Dbg_index Dbg_index+1

INV_DBG Current_data NOT (Current_data)

READCurrent

_data Memory[Current

_address]

WRITE Memory[Current_address] Current_data



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Wrapper

WSI

TAP

controller

WRCK

WRSTN

ShiftWR

UpdateWR

CaptureWR

SelectWIR

WSO

W

C

WD

Me WW R

I D Processor mory

B

R R R

WTestB

Y Program CORE

Wrapper



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Summary

ROM BIST has been presented

ROM-based and FSM-based RAM BIST havebeen introduced

Serial BIST methodology for embeddedmemories has also presented

BIST approaches for testing multiple RAMs in an SOChave also been addressed


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Documents

ROM BIST