117th Oct 2013

Roll-to-roll Vacuum Processing of Organic Thin Film Transistors

Hazel AssenderDepartment of Materials

University of Oxford

DALMATIAN

TECHNOLOGY

217th Oct 2013

Aim of the Research

- Flexible, polymer substrate (web)

- High speed (e.g. 1m/s web speed)

- R2R process

- Low cost materials

2

Possible application:

anticounterfeiting/product

tracking tags for packaging.

To demonstrate the ability to fabricate all-evaporated transistors in a

R2R vacuum web process environment exploiting the technology that

is used in the packaging industry.

317th Oct 2013 3

Issues to consider

5) Robustness of final devices

Gate

Substrate

Source and Drain (Metal)

L W

Org. Semiconductor

Insulatore.g. 0.5µm acrylic

e.g. 125µm thick PEN

e.g. 90nm pentacene

1) Process parameters in R2R environment – building and testing transistors.

2) Circuit design tailored for the properties achievable with this manufacturing route

3) Materials (organic semiconductor and polymer gate insulator layer) developed for this manufacturing route

4) Patterning processes

417th Oct 2013

Substrate (e.g. PET)

Gate

Source and Drain (Metal)

4

Roll-to-roll devices

Polymer smoothing layer:

Flash evaporated monomers then cure

Gate:pattern metallization

Gate insulator layer:Flash evaporated monomers

then cure

Perhaps surface modification layer: Various options

Build complete

device structure

on the substrate

Insulator (e.g. acrylic

dielectric)

Possible interlayer

Possible surface modification

Molecular semiconductor: Evaporation

Source and Drain: pattern metallization

Encapsulation layer/gas barrier

Org. Semiconductor

WL

517th Oct 2013 5

Materials: pattern metallization

Evaporation zone 5 × 10-4 mbar

Winding zone

Unwind

Process Drum

Rewind

Anilox Roller

and Oil Boiler Cliché Plate

PRINTING RESOLUTION

MD: 30-50 micron

TD: 30-50 micron

---

----

Sourc

e/D

rain

Ele

ctr

odes--

----

Magnification x 200

Magnification x 60

617th Oct 2013

• In-line process• High speed

Depositing the gate-insulator

Smooth Acrylic layer

VacuumHeat Tank 250 °C

i. Evaporate monomer (liquid)

ii. Monomer condenses onto substrate (web) as a liquid (flat)

iii. Polymerize (cure) in-situ to a solid

717th Oct 2013

Patterning the organic layers

Semiconductor:

High speed organic vapour jet printing.

We have demonstrated working devices made with OVJP.

Carrier gas in

Gas heating furnace

Semiconductor furnace

Nozzle

Gas out

Insulator:

Development of solventless printing (e.g. flexoprint and inkjet) of liquid monomer prior to e-beam or UV cure

SubstrateInk bath

Anilox roller

Printing plate

Doctor blade

Cure

817th Oct 2013

Increase e-beam cure current

Make R2R process

-10

-8

-6

-4

-2

0-50 -40 -30 -20 -10 0

VD(V)

I D(n

A)

-10V-20V-24V-30V-40V-44V

VG

-50 -40 -30 -20 -10 0

-3

-2

-1

0

I D(µ

A)

VD(V)

-10V

-20V

-30V

-40V

-50V

Gate insulator deposition

8

First devices

Plasma cured, single pass

Anneal (150ºC 1hr)

-40 -30 -20 -10 0

-6

-4

-2

0

-10V-20V-30V-40V

I D(µ

A)

VD(V)

E-beam cured + annealed

Ion/Ioff = 1.3x103

Vth = 15V

µ = 0.1cm2/Vs

-10

-5

0-40 -30 -20 -10 0

0V-10V-20V-30V-40V

I D(n

A)

VD(V)

VG

E-beam cured

917th Oct 2013

Modification of the insulator

surfaceSpin coat a thin (20-40nm) polymer layer:

1µm

0.01 0.1 1 10

0.01

0.1

PNP

PS

PVS

PBM

TPGDA

PMMA

Mobili

ty (

cm

2/V

s)

Polar part surface energy (mN/m)

Ester:carbon ratio

1017th Oct 2013 10

Materials developments

DNTT, dinaphtho[2,3-b:2′,3′-f]thieno[3,2-b]thiophene, has better

environmental stability due to a reduced tendency to oxidize.

Synthetic route for DNTT:

DNTT synthesised and processed via A, literature route and B, an evolved method.

1117th Oct 2013

DNTT devices

VT (V)µ

(cm2 V-1 s-1)Ion/Ioff

S(V/decade)

TPGDA / DNTT

-4 0.12 105 1.8

TPGDA / Pentacene

-12 0.04 103 8.0

TPGDA / PS / DNTT

-1 0.95 ± 0.17 107 0.5

TPGDA / PS / Pentacene

-10 0.57 ± 0.04 106 2.0

• Made with evaporated TPGDA/PS dielectric: 100%

-40 -20 0 20

1E-12

1E-10

1E-8

1E-6

1E-4

DNTT µ=1 cm2/Vs

Pentacene µ=0.6 cm2/Vs

Vg(V)

I d(A

)

0.000

0.005

0.010

I d0.5

(A0.5

)

Yields, tested over batches of 96 transistors

• Made with solution-cast PS dielectric: 66%

1217th Oct 2013

Modelling DNTT devices

Parameter

Solution-deposited

PS insulator

Evaporated acrylic insulator

Evaporated acrylic insulator with PS buffer

Ambient Air Air Vacuum

W(µm) 15900 3000 2400

L(µm) 36 150 200

Ci (nF/cm2) 1.59 5.84 12.8

VT (V) -3.91 -4.78 -1.31

V0 (V) 1.45 3.12 0.31

VACC 1 1 1

µACC (cm2/Vs) 0.01 0.04 1.05

γ 0.63 0.36 6x10-7

λ 0.0124 0 0

MSAT 2.84 3.41 2.58

ASAT 0.20 1.42 1.41

I0 (fA) 30 30 30

σ0 (S) 7x10-14 1x10-20 1x10-13

RS (kΩ) 438 0 73.9

RD (kΩ) 337 0 86.6

-60

-40

-20

0

-40 -20 0VD(V)

I D(m

A) Vg=0V

-5V-10V

-15V

-20V

-25V

-30V

-10

-8

-6

-4

-30 -20 -10 0VG(V)

Log

10(I

D/A

)

Vg=-0.5V

-2.5V

-4.0V

-30.0V

1317th Oct 2013

Invertor-V

VIN

VOUT

Enhancement Load

Driver OTFT

Experimental Response Transfer Plot

1417th Oct 2013

NAND

VIN 1 VIN 2 VOUT

0 0 1

0 1 1

1 0 1

1 1 0

Truth Table

Logic Circuits

NOR

VIN 1 VIN 2 VOUT

0 0 1

0 1 0

1 0 0

1 1 0

NAND NOR

Truth Table

1517th Oct 2013

Ring Oscillator

VDD (V) Frequency (kHz)Sim Expt

Amplitude(V)Sim Expt

-60 16.7 0.365 25.6 16.0

-40 5.1 0.137 8.3 7.0

1617th Oct 2013

Environmental testing

Dry vs. damp airIncrease in Ioff

Mobility and VT unaffectedEffect of water recoverable

e.g. by exposing sample to vacuum.

Vacuum vs. dry airSmall VT shift

Apparently stable performance over weeks if stored in dry conditions.

Lamination and in-line encapsulation (e.g. TPGDA followed by SiOx) tried• good working devices.

-40 -20 0 20

1E-10

1E-8

1E-6

1E-4Vac

Vg(V)

I d(A

)

Dry air

DNTT with acrylate/PS insulator

Dry air

-40 -20 0 20

1E-10

1E-8

1E-6

1E-4

RH 50%

Vg(V)

I d(A

)

1717th Oct 2013

Mechanical testing

Polymer dielectric AlOx dielectric

1817th Oct 2013 18

Progress so far…..

1) Process parameters in R2R environment – building and testing transistors Plastic flexible substrates (125 µm thick PEN

substrate)

Al gate electrode

Improved in-line curing method (10 m/min webspeed)

Interface buffer layer (evaporated PS thin layer)

Low hysteresis in devices and good stability

Very high yield

1917th Oct 2013 19

Progress so far……

2) Circuit design tailored for the properties achievable with this manufacturing route

Transistor characteristics modelled

3) Materials (semiconductor and gate insulator layer) developed for this manufacturing route

New SC synthesised, more under development

Tried new insulator materials

4) Robustness of final devices Strain to failure much greater than devices with ceramic insulators

Device mobility stable on bending

Devices can survive lamination

5) Patterning processes Favoured options for SC and insulator layers under development

2017th Oct 2013 20

Acknowledgements

Bangor

Prof Martin Taylor

Mr Aled Williams

Mr Eifion Patchett

Oxford

Dr Gamal Abbas

Mr Ziqian Ding

Dr Kanad Mallik

Leeds

Prof Long Lin

Dr Weidong He

Manchester

Prof Steve Yeates

Dr John Morrison