Rodwell_SBSEE10

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High Speed TransistorsLow Power Transistors for VLSI

[email protected] 805-893-3244, 805-893-5705 fax

Energy Summit, Santa Barbara, May 12, 2010

Mark Rodwell

University of California, Santa Barbara

Coauthors: HBT

E. Lobisser, V. Jain, A. Baraskar, B. J. Thibeault,University of California, Santa Barbara

Z. Griffith, J. Hacker, M. Seo, M. Urteaga, Richard Pierson, B. BrarTeledyne Scientific Company

Coauthors: FETM. A. Wistey*, U. Singisetti, G. J. Burek, A. Carter B. J. Thibeault, A. Baraskar, J. Law, J. Cagnon, C.Palmstrom, S. Stemmer, A. C. GossardUniversity of California, Santa Barbara (*Now at Notre Dame)

E. Kim, P. C. McIntyreStanford University

B. Yue, L. Wang, P. Asbeck, Y. Taur, A. KummelUniversity of California, San Diego


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High-Speed Transistors...an overview.


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Why Build THz Transistors ?

THz amplifiers! THz radios! imaging, sensing,communications

precision analog designat microwave frequencies! high-performance receivers

500 GHz digital logic! fiber optics

Higher-ResolutionMicrowave ADCs, DACs,DDSs


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FET parameter change

gate length decrease 2:1

current density (mA/m), gm (mS/m) increase 2:1

channel 2DEG electron density increase 2:1

gate-channel capacitance density increase 2:1

dielectric equivalent thickness decrease 2:1

channel thickness decrease 2:1

channel density of states increase 2:1

source & drain contact resistivities decrease 4:1

Changes required to double transistor bandwidth

HBT parameter change

emitter & collector junction widths decrease 4:1current density (mA/m2) increase 4:1

current density (mA/m) constant

collector depletion thickness decrease 2:1

base thickness decrease 1.4:1

emitter & base contact resistivities decrease 4:1

constant voltage, constant velocity scaling

nearly constant junction temperature! linewidths vary as (1 / bandwidth)2

fringing capacitance does not scale! linewidths scale as (1 / bandwidth )


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THz & nm Transistors: it's all about the interfaces

Metal-semiconductor interfaces (Ohmic contacts):very low resistivity

Dielectric-semiconductor interfaces (Gate dielectrics):very high capacitance density

Transistor & IC thermal resistivity.


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256 nm InP HBT 150 nm thick collector

70 nm thick collector

60 nm thick collector

440 GHz VCO

340 GHzdynamicfrequency

divider

324 GHzamplifier

Z. Griffith

J. Hacker, TSC

Z. Griffith

E. Lind

M. Seo, UCSB/TSC

M. Seo, UCSB/TSC

204 GHzstaticfrequencydivider

Z. Griffith, TSC


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InP Bipolar Transistor Scaling Roadmap

emitter 512 256 128 64 32 nm width

16 8 4 2 1 !"m2 access #$

base 300 175 120 60 30 nm contact width,

20 10 5 2.5 1.25!"m2 contact

#

collector 150 106 75 53 37.5 nm thick,

4.5 9 18 36 72 mA/m2 current density

4.9 4 3.3 2.75 2-2.5 V, breakdown

f% 370 520 730 1000 1400 GHzfmax 490 850 1300 2000 2800 GHz

power amplifiers 245 430 660 1000 1400 GHz

digital 2:1 divider 150 240 330 480 660 GHz

industry university

!industry

university

2007-9

appears

feasible

maybe


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128 / 64 nm process: Sputtered Refractory Base

V. Jain

E. Lobisser

In-situ MBE emitter contacts:refractory! high Jlow contact #: ~0.7 !-m2Refractory emitter contactdry-etched! nm resolutionrefractory! high current

Wet/dry etched emitterdry-etched! nm resolution

Refractory base contactslow penetration! thin baseslow contact # ~2.5 !-m2self-aligned/ liftoff-free


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128 nm InP DHBT ProcessV. JainE. Lobisser


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InGaAs FET Scaling Roadmap

Applicationsmicrowave / mm-wave / THz ICsVLSI


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27 nm InGaAs MOSFET with Regrown Source/DrainCarter, Burek,Law, Baraskar


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III-V MOSFETs: What Are Our Goals ?

Low off-state current (10 nA/m) for low static dissipation! minimum subthreshold slope! minimum Lg/ Tox

low gate tunneling, low band-band tunneling

Low delay CFET!V/Id in gates wheretransistor capacitances dominate.

Parasitic capacitances are 0.5-1.0 fF/m! while low Cgs is good,

high Idis much better

Low delay Cwire!V/Id in gates wherewiring capacitances dominate.

large FET footprint! long wires between gates

! need high Id/ Wgat low voltage

target ~2.5 mA/

m @ 500 mV Vdd


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Ultra Low Power Logic for Future Computers

A subject of great importance; being broadly pursued.Can we greatly reduce static and dynamic IC power ?

Modified { transistors, gates, interconnects, singaling}Alternate logic devices to replace FETs ?


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Logic must Compute

e.g. , problem if input is DC H-fieldand output is 50 GHz spin wave amplitude

e.g. , problem if input is DC currentand output is DC B-field

e.g. , problem if input is at 2 GHz,and output is at 25 GHz (parametric gain)


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Logic Must Be Robust

e.g. , nondegenerate parametric gain ---bilateral

e.g. clockless tunnel diode logic---bilateral

e.g. clockless Josephson Junction logic---bilateral


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Logic Elements Must Communicate

ion / reagent concentration in solution (biology)wiresgears (adding machines)optical waveguides


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Parts to Build Computers

What would you use....to compute ?

....to communicate ?

http://en.wikipedia.org/wiki/File:Standard_Model_of_Elementary_Particles.svg

Gluonics ?

Gravitonics ?


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Wires

CMOS VLSI


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The VLSI Power Problem

Low standby power! increase supply voltage

Low dynamic switching power! decrease supply voltage


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Thermal-Noise-Limited Voltage Swing

No Poisson statistics(Shot noise) associated with thecapacitor charge


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Zero-Resistance wires! no CV2f dissipation


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Trying To Beat C(kT/q ln(Ion/Ioff))2 : Transistor Approaches

channel

P+++source

N+++source

gate

drain

Appenzeller, PurdueSeabaugh, Notre DameAsbeck, San Diego


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Beating CVdd2F Using Linear Amplifiers ... at a cost


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Beating C(kT/q ln(Ion/Ioff))2 using optical interconnects


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Low Power Logic Using Magnetic Devices ?


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Current Signaling Suffers From Static Dissipation


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Reducing Power by Scaling FET & IC Dimensions


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Reducing Power by Reducing Supply Voltage


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Normalized Drive Current Comparison


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