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Robust Gate Sizing by Geometric Programming. Jaskirat Singh, Vidyasagar Nookala, Tom Luo, Sachin Sapatnekar Department of Electrical and Computer Engineering University of Minnesota. Outline. Introduction Motivation Robust gate sizing - PowerPoint PPT Presentation
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Robust Gate Sizing by Robust Gate Sizing by Geometric Geometric
ProgrammingProgrammingJaskirat Singh, Vidyasagar Nookala, Tom Luo, Sachin Jaskirat Singh, Vidyasagar Nookala, Tom Luo, Sachin
SapatnekarSapatnekar
Department of Electrical and Computer EngineeringDepartment of Electrical and Computer Engineering
University of MinnesotaUniversity of Minnesota
2
OutlineOutline
IntroductionIntroduction Motivation Motivation Robust gate sizingRobust gate sizing
Impact of variations on the conventional gate sizing Impact of variations on the conventional gate sizing solutionsolution
Uncertainty ellipsoidUncertainty ellipsoid Robust GP formulationRobust GP formulation
Experimental resultsExperimental results SummarySummary
3
IntroductionIntroduction
There’s many a slip between the cup and the lip
Impact of increasing variability in designImpact of increasing variability in design
Process uncertainties
Environment variations
Tool inaccuracies
What you draw ………… is NOT what you get!!
delay
delay specs# of chips
Timing yieldTiming yield of the circuit affected of the circuit affected
4
Gate Sizing ProblemGate Sizing Problem
22 / np XX
33 / np XX11 / np XX Minimize Area (Power)
Subject to:
Delay ≤ Dspec
Xmin ≤ X ≤ Xmax
Previous workPrevious work Fishburn and Dunlop, ICCAD ’85Fishburn and Dunlop, ICCAD ’85 Sapatnekar Sapatnekar et. alet. al, TCAD ’93, TCAD ’93 Chen Chen et. al, et. al, TCAD’99TCAD’99
Do not account for variationsDo not account for variations Circuit optimized for a specified delay Circuit optimized for a specified delay
A number of dies have to die!!
1 3
2
5
Robust Gate Sizing SolutionsRobust Gate Sizing Solutions
Traditional worst-casing techniquesTraditional worst-casing techniques Set tighter specs than requiredSet tighter specs than required
May lead to large overheadsMay lead to large overheads
delay
delay specs new
# of chips
delay specs original
slack
Corner based designsCorner based designs Design for extreme values of the Design for extreme values of the
parameter variationsparameter variations Ignores correlations betweenIgnores correlations between
random variablesrandom variables Curse of dimensionalityCurse of dimensionality
pmin ≤ p ≤ pmax
Statistical DesignsStatistical Designs
6
OutlineOutline
IntroductionIntroduction MotivationMotivation Robust gate sizingRobust gate sizing
Impact of variations on the conventional gate sizing Impact of variations on the conventional gate sizing solutionsolution
Uncertainty ellipsoidUncertainty ellipsoid Robust GP formulationRobust GP formulation
Experimental resultsExperimental results SummarySummary
7
Conventional Gate Sizing SolutionConventional Gate Sizing Solution
Min Area (W, L)Subject to: Delay (W, L) ≤ Dspec
Wmin ≤W ≤ Wmax
L=Lmin
Area, Delay are posynomials in (W, L)
iii i LWmArea
Posynomial delay models, e.g., Elmore delay- Replace each gate by RC elements
CLR C CL
W
LR
LWC
Delay constraints at the output of each gate: itLWPosy ),(
Solve the GP by convex optimization tools
8
Impact of Variations on Gate Sizing Impact of Variations on Gate Sizing
Parametric variations as random variable Parametric variations as random variable (W, L)(W, L) vary as vary as (W(W00++δδW, LW, L00++δδL)L)
itLWPosy ),(
ii tXf )(),()( LWPosyXfi
Define
L
WX
and constraint function
Effect on delay constraints
)(Xfi varies as )( XXf oi Using first order Taylor series
XXfXfXXf iXii )()()( 000 0
Nominal term Variation term
An example of Gaussian variations in (W, L)(W, L)
(W0,L0)
Delay constraints :Delay constraints :
Nominal term + Variation term ≤ Nominal term + Variation term ≤ ttii
Violations if:Violations if:
Variation term > SlackVariation term > Slack
9
OutlineOutline
IntroductionIntroduction MotivationMotivation Robust gate sizingRobust gate sizing
Impact of variations on the conventional gate sizing Impact of variations on the conventional gate sizing solutionsolution
Uncertainty ellipsoidUncertainty ellipsoid Robust GP formulationRobust GP formulation
Experimental resultsExperimental results SummarySummary
10
Uncertainty Ellipsoid ModelUncertainty Ellipsoid Model
1)()(
2
20
2
20
b
yy
a
xx
10
0
0
0
2
2
00
yy
xx
b
ayyxx
}1)()(:{ 01
0 XXPXXXU T
x
yy0
x0 ab An ellipse set
x
y
z
An ellipsoid set
Substituting uXXP )( 02/1
}1)()(:{ 01
0 XXPXXXU T }1|{ 2/10 uuPXU
uuu T
11
Uncertainty Ellipsoid ModelUncertainty Ellipsoid Model
Ellipsoid uncertainty modelEllipsoid uncertainty model Bounded model for random variations Bounded model for random variations
}1|{ 2/10 uuPXU
x0
eig21
2
eig1
nominal design
:random variations
covariance matrix
X
12
OutlineOutline
IntroductionIntroduction MotivationMotivation Robust gate sizingRobust gate sizing
Impact of variations on the conventional gate sizing Impact of variations on the conventional gate sizing solutionsolution
Uncertainty ellipsoidUncertainty ellipsoid Robust GP formulationRobust GP formulation
Experimental resultsExperimental results SummarySummary
13
Generate posynomial delay constraints by STAGenerate posynomial delay constraints by STA Use Elmore delay for simplicityUse Elmore delay for simplicity Any generalized posynomial constraints may be usedAny generalized posynomial constraints may be used
Kasamsetty, Ketkar and Sapatnekar, TCAD’98Kasamsetty, Ketkar and Sapatnekar, TCAD’98..
Robust Gate Sizing ProcedureRobust Gate Sizing Procedure
itLWPosyXf ),()(
Using first order Taylor series for variations around nominal values
XXfXfXXf iXii )()()( 000 0
Nominal term Variation term
14
Robust Gate Sizing ProcedureRobust Gate Sizing Procedure
Nominal term + Variation term ≤ Nominal term + Variation term ≤ ttii
Use the ellipsoid uncertainty modelUse the ellipsoid uncertainty model
}1|{ 2/10 uuPXU
x0
eig21
2
eig1
For robustnessFor robustness Nominal term + Nominal term + Max Max δδXXєєUU (Variation term) ≤(Variation term) ≤ ttii
iiX tXXf )))(((0
)( 0Xfi UXMax
This is still a posynomial An example follows
),( 0 oLWPosyULWMax , itLWLWPosygrad ),)),((( 00
15
ExampleExample
2CL
(W1 , L1 ) (W2 , L2 )
1
2
1
2
1
L
L
W
W
X
specTW
Lk
W
WLLk
2
22
1
2211
specL TCRCR 221
specTW
Lk
W
WLLk
2
22
1
2211 0
0
0
000
2
22
1
2211
W
Lk
W
WLLkspecT21 rr
11 PT 21r 1
22 PT 22r 1
Convert each original posynomial constraint to a set of posynomial robust constraints
16
ExampleExample
2CL
(W1 , L1 ) (W2 , L2 )
1specT
W
Lk
W
WLLk
2
22
1
2211
2
1
2
1
L
L
W
W
X
First order Taylor series approximation
0
0
0
000
2
22
1
2211
W
Lk
W
WLLkULW
Max ,
)
(
22
222
12
12211
2
22
1
2211
1
1221
1
2211
0
0
0
000
0
0
00
0
00
0
00
W
WLk
W
WWLLk
W
Lk
W
LWLk
W
LWLk
W
WLLk
specT
),( 00 LWDnom
2
1
2
1
L
L
W
W
X
ULWMax
,
)
(
22
222
12
12211
2
22
1
2211
1
1221
1
2211
0
0
0
000
0
0
00
0
00
0
00
W
WLk
W
WWLLk
W
Lk
W
LWLk
W
LWLk
W
WLLk
specT
17
)
(
22
222
12
12211
2
22
1
2211
1
1221
1
2211
0
0
0
000
0
0
00
0
00
0
00
W
WLk
W
WWLLk
W
Lk
W
LWLk
W
LWLk
W
WLLk
ExampleExample
2CL
(W1 , L1 ) (W2 , L2 )
1
),( 00 LWDnom ULWMax
,specT
00
00
0
00
0
00
2
2
1
211
1
221
1
211
1
0
W
k
W
WLkW
WLkW
LLk
0
00
0
0
000
22
22
21
2211
2W
LkW
WLLk
2
1
2
1
L
L
W
W
X
),( 00 LWDnom UXMax
specT
),( 00 LWDnomUX
Max
),,( 21 XX specT baba T,
))()(
)()()((
221112
441331221
XX
XXX
18
42/1
32/1
22/1
12/1
2/1
)(
)(
)(
)(
uP
uP
uP
uP
uP
}1|{ 2/10 uuPXU
ExampleExample
baba T,
Using Cauchy Schwartz inequality baba , aaa T
22/1
12/1
22/1
12/1 ),,( PPuPuP
uMax
Use uncertainty ellipsoid model
),( 00 LWDnom 22/1
12/1 PP specT
2CL
(W1 , L1 ) (W2 , L2 )
1
2
1
2
1
L
L
W
W
X
),( 00 LWDnomUX
Max
),,( 21 XX specT
x0
eig21
2
eig1
),( 00 LWDnomu
Max
),,( 22/1
12/1 uPuP specT
19
ExampleExample
0
0
0
000
2
22
1
2211
W
Lk
W
WLLk2
2/11
2/1 PP specT
Define robust variables r1, r2
222
222/1
2
112
112/1
1
PrPr
PrPr
T
T
0
0
0
000
2
22
1
2211
W
Lk
W
WLLkspecT21 rr
11 PT1
22 PT 22r 1
A set of posynomial robust constraints
2CL
(W1 , L1 ) (W2 , L2 )
1
21r
P : covariance matrix Pij ≥ 0
20
GP MethodGP Method
Convert each original constraint to a set of robust constraints Convert each original constraint to a set of robust constraints
specTW
Lk
W
WLLk
2
22
1
2211 0
0
0
000
2
22
1
2211
W
Lk
W
WLLkspecT21 rr
11 PT 21r 1
22 PT 22r 1
Cost of at most two additional variables per constraint Cost of at most two additional variables per constraint
21
The Complete ProcedureThe Complete Procedure
Generate Elmore delay based constraints by STA
Taylor series expansion of constraint functions
Model variations as an uncertainty ellipsoid
Generate robust constraints
Solve the GP
22
Experimental SetupExperimental Setup
ISCAS’85 benchmark circuits optimizedISCAS’85 benchmark circuits optimized 20% L, 25%W 320% L, 25%W 3σσ variations assumed variations assumed TTspecspec set as 15% slack point set as 15% slack point MOSEK solver for the GPMOSEK solver for the GP Monte Carlo simulations for timing yield determinationMonte Carlo simulations for timing yield determination
5000 samples drawn assuming multivariate normal 5000 samples drawn assuming multivariate normal N(XN(X00 ,P) ,P) Non-robust designs compared with robust designsNon-robust designs compared with robust designs
23
ResultsResults
Ckt
# of
Gates
Non Robust Design Robust Design
Area
% Delay
Violations
Time
(sec) Area
% Delay
Violations
Time
(sec)
C432 616 1.00 78.76% 3.45 1.17 0.00% 18.08
C499 1262 1.00 70.52% 7.49 1.23 0.01% 29.26
C880 854 1.00 72.36% 5.30 1.14 0.00% 22.17
C1355 1202 1.00 68.76% 7.33 1.20 0.00% 36.42
C1908 1636 1.00 65.43% 14.40 1.19 0.00% 307.88
C2670 2072 1.00 60.09% 20.52 1.21 0.03% 310.34
C3540 2882 1.00 67.12% 31.70 1.11 0.02% 342.14
C5315 4514 1.00 62.25% 65.12 1.18 0.01% 817.89
C6288 5548 1.00 63.36% 98.27 1.18 0.02% 1042.44
C6524 6524 1.00 65.12% 120.35 1.22 0.03% 1245.34
A comparison of robust and non-robust sizing solutions
Monte Carlo simulations for timing yield determination
24
SummarySummary
Propose a novel uncertainty aware gate sizing Propose a novel uncertainty aware gate sizing schemescheme
Use an uncertainty ellipsoid to model random Use an uncertainty ellipsoid to model random variationsvariations
Robust formulation relaxed to a GPRobust formulation relaxed to a GP Timing yield of robust circuits improves 3-4 timesTiming yield of robust circuits improves 3-4 times Better than the conventional worst-casing Better than the conventional worst-casing
methodmethod