Research plans

Evaluating the suitability of FinFET technology for analog/RF circuits involves the following:

– Developing a working model for SPICE simulation based on 3-D device simulation

– Finding optimal device layouts for high-frequency performance

– Designing, fabricating test circuits (LNA, oscillator) and verifying power gain, noise, linearity

– Refining device models based on circuit-level measurements

– Comparing utility of FinFET for different applications

RF CMOS performance trends

• Effect of technology scaling on RF performance:

fT: improves with scaling (1/L for short-channel devices)

fMAX: improves with scaling, but limited by strong dependence on gate resistance and parasitics

FMIN: decreases with scaling for a given frequency

IIP3: Id/W must increase to maintain good linearity

• Can a sub-100nm advanced transistor structure (FinFET) take advantage of these scaling trends and confer additional benefits to analog/RF circuits, e.g. better noise performance, improved gmro?

• I m p a c t o f g a t e r e s i s t a n c e o n R F p e r f o r m a n c e– i f i g n o r e d , p o t e n t i a l e r r o r i n i m p e d a n c e m a t c h i n g ( e . g . , t o a

5 0 - Ω s o u r c e )– i n c r e a s e d m i n i m u m n o i s e f i g u r e– r e d u c e d p o w e r g a i n , d e g r a d e d o v e r a l l t r a n s c o n d u c t a n c e

– f M A X

• G a t e r e s i s t a n c e m o d e l i n gR g a t e c o n s i s t s o f t w o c o m p o n e n t s :

• d i s t r i b u t e d g a t e e l e c t r o d e r e s i s t a n c e• c h a n n e l - i n d u c e d g a t e r e s i s t a n c e

• M i n i m i z e g a t e r e s i s t a n c e b y u s i n g– g a t e c o n t a c t s o n b o t h e n d s– p r o p e r l a y o u t ( s h o r t m u l t i - g a t e f i n g e r s t r u c t u r e s )– s i l i c i d e d p o l y - g a t e / m e t a l g a t e t e c h n o l o g i e s

H i g h - f r e q u e n c y m o d e l i n g

S o u r c e : J i n , I E D M ’ 9 8

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F i n F E T s t r u c t u r e a n d l a y o u t

• T h e d o u b l e - g a t e F i n F E T — a p r o m i s i n g c a n d i d a t e t o c o n t i n u e C M O S s c a l i n g d e e p i n t o t h e n a n o m e t e r r e g i m e

• G a t e s t r a d d l e s t h i n s i l i c o n f i n , f o r m i n g t w o c o n d u c t i n g c h a n n e l s o n s i d e w a l l

S o u r c e ( a l l i m a g e s ) : T - J K i n g , e t a l , “ F i n F E T T e c h n o l o g y O p t i m i z a t i o n … ” p r e s e n t a t i o n s l i d e s , O c t . 2 0 0 3

G a t eS o u r c e

D r a i n

S o u r c e

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D r a i n

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S o u r c e

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M u l t i - f i n l a y o u tC o n v e n t i o n a l S O I M O S F E T

• L a y o u t s i m i l a r t o c o n v e n t i o n a l S O I M O S F E T

So

urc

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inG a t e 2G a t e 2

F i n W i d t h W f i n = T S i

F i n H e i g h t = H f i n = W

G a t e L e n g t h = L g

C u r r e n t F l o w

G a t e 1G a t e 1

So

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inG a t e 2G a t e 2

F i n W i d t h W f i n = T S i

F i n H e i g h t = H f i n = W

G a t e L e n g t h = L g

C u r r e n t F l o w

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3 D v i e w o f F i n F E T

S o u r c e D r a i n

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S o u r c e D r a i n

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S o u r c e D r a i n

G a t e

Future work

• Run 3-D device simulations using ISE DESSIS to extract high-frequency Y-parameters

• Can we obtain measured S-parameter data?

• Consider how best to build an adequate SPICE model (AC) based on device simulation results

• With a working SPICE model, estimate important high-frequency figures of merit and begin to design basic analog/RF circuits for system-level verification of power gain, noise, linearity

FinFET modeling

• Need a suitable SPICE model for initial design based on transistor I-V, C-V, and AC (S-parameter) characteristics

• Initial simulations based on BSIMSOI3.1 using preliminary SPAWAR (DC) model. BSIM DG currently under development.

• Need to verify high-frequency behavior of SPICE model

• BSIMSOI3.1 includes RF functionality and has been incorporated into spice3

• How to obtain RF model parameters?

BSIMSOI RF model (RgateMod =3)Source: BSIMSOI3.1 Manual

3D device simulation(ISE)

Extract and compareY11, Y12, ...

RF model parameters(XRCRG1, XGW,…)

SPICE simulation(BSIMSOI3.1)

calibrate

Future work

• Run 3-D device simulations using ISE DESSIS to extract high-frequency Y-parameters

• Can we obtain measured S-parameter data?

• Consider how best to build an adequate SPICE model (AC) based on device simulation results

• With a working SPICE model, estimate important high-frequency figures of merit and begin to design basic analog/RF circuits for system-level verification of power gain, noise, linearity

Application of FinFETTechnology to Analog/RF

Circuits

Matthew Muh, Professor Ali M. Niknejad