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DIGITIAL ELECTRONICS Assigment#1 “Review Question Problems of chapter 4” Submit By: M.Usman Rafique Reg.No.: BEE-Fa10-038 Section: B

Review Question Problems of chapter 4

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Page 1: Review Question Problems of chapter 4

DIGITIAL ELECTRONICS

Assigment#1

“Review Question Problems of chapter 4”

Submit By: M.Usman Rafique

Reg.No.: BEE-Fa10-038

Section: B

The University of Faisalabad

Page 2: Review Question Problems of chapter 4

Q#1: sketch bjt as a switch and compare transistor with ideal switch.

Ans:

When transistor’s switch is off, there is small collector leakage current in nano amperes exist and so, V CE is not exact equal to vcc due leakage collector current, while in ideal switch we ignore leakage current so V CE is exact equal to vcc .

When transistor’s switch is on i.e. in saturation mode then small collector emitter voltage exist, typically about 0.2v while in ideal switchV CE=0.

Q#2: Define saturated switch, nonsaturated switch, saturation voltage, collector base leakage current and hfe (min) relation.

Ans: Saturated switch: In saturated switch base-emitter junction is forward biased

and base-collector junction is also forward biased.V CE Approaches to 0.2 volts approximately.

Page 3: Review Question Problems of chapter 4

Nonsaturated switch: In nonsaturated switch base-emitter junction is forward biased, while base-collector junction is reversed biased.

Saturation voltage: When we increase I c until V CE is less then0.7v then transistor

goes to saturation mode then V CEis said to be saturated voltage.

Collector base leakage current: In cutttoff region when IB is zero,I c is not zero.

Instead a small current flows. This current is called collector base leakage current.

hfe (min):H FE tell us that transistor goes to saturation or not. Transistor must have min.

value of hFE for saturation to occur.

Relationshipe:When transistor is “on” saturation voltage occur and when “off” leakage current occur and saturation depend on hfe.

Q#4:

ANS:a)

Given:vcc=20v; RL=2.2kΩ

hFE(min)=?

IC=20v/2.2kΩ

=9.09mA

hFE(min)=9.09/0.3=30.3

Page 4: Review Question Problems of chapter 4

b)hFE(min)=50

IB=9.09mA/50=182µA

Q#5:

ANS:at R=22kΩ ; IB=?

Ic=25/22=1.136mA

hFE(min)=70

IB=1.136mA/70=16.22mA

At R=2.2kΩ ; IB=?

Ic=25/2.2kΩ=11.36mA

IB=11.36mA/100=114 µA

Q#6:

ANS: At R=22kΩ

At saturation…

Page 5: Review Question Problems of chapter 4

p=ic*V CE

p=1.136mA*0.2v=0.228mW

At cutoff…

P=25*50nA=1.25mW

At R=22kΩ

At saturation…

p=11.36mA*0.2v=2.28mW

At cutoff…

P=25*50nA=1.25mW

Q#8:

Ans:vcc =15v ; R=2.7kΩ ; pulse width=2µs

V CE=?

a)before pulse apply…V CE=15-(50nA)(2.7kΩ)

=14.999

b)at the end of delay time…

Page 6: Review Question Problems of chapter 4

V CE=15-0.1(ic)Rc

=15-(0.1V CE/Rc)*Rc

=15-0.1*15=13.5v

c)at the end of storage time…V CE=15-0.9(ic)Rc

=15-(0.9V CE/Rc)*Rc

=15-0.9*15=13.5v

=1.5v

d)until transistor switch on..

ton=20ns

until transistor switch off…

pw+ton=2µs+22ns=2.022 µs

Q#9:

Ans: To reduce the turn on and turn off time we placed capacitor parallel to the base

resistance. At switch on, capacitor began to charge and iB began to increase so junction capacitance charge fastly and turn on time reduce. At switch off capacitor start to discharge and produce reverse iB so, junction capacitance discharge rapidly. this reduces turn off time.

Page 7: Review Question Problems of chapter 4

Q#10:

Ans:R=27kΩ ;

A)C=?

T=1/100 kHz = 0.01ms

tre=T/2=5 µs

tre=2.3cRB

c=5 µs/(2.3*27kΩ)=80.5pF

B)f=?

tre=2.3(100pF)( 27kΩv )

=6.21 µs

T=2tre

T=12.42 µs

f=1/T=80.5kHz

Q#11:

Page 8: Review Question Problems of chapter 4

Ans:In n-channel JFET,at on condition input voltage is zero and to get off condition

we provide negative input voltage, exceeding the vGS(off).

Comparision:JFET saturation voltage is less than BJT saturation voltage. It has small drain-gate leakage current than BJT leakage current. IT has higher input resistance than BJT.

Q#12:

Ans:a)cut off…

vDS=?

vDS=vdd−iDRD

=20-(0.25nA)( 4.7kΩ)

19.99999=20v

b)switch on…

iD=vdd/RL

=20/4.7kΩ=4.26mA

V=¿D)(rds)=

4.26mA(25Ω ¿=¿106mA

Q#14:

Ans:CMOSE:The complementary combination of n-channel and p-channel

MOSFET term as CMOS.

Page 9: Review Question Problems of chapter 4

Advantages: Power dissipation is extremely small compared to other devices. There is no drain-gate leakage current but there is very small drain-source leakage current .Very high input impedance.

Disadvantages: CMOS has low frequency response.

CMOS has high capacitance in it.so,its propagation delay is high among the logic families.