331 Lec 14.1 Fall 2002

Review: Abstract Implementation ViewSplit memory (Harvard) model - single cycle operation

Simplified to contain only the instructions:memory-reference instructions: lw, swarithmetic-logical instructions: add, sub, and, or, sltcontrol flow instructions: beq, j

Sequential components (PC, RegFile, Memory) are edge triggered

state elements are written on every clock cycle; if not, need explicit write control signal

- write occurs only when both the write control is asserted and the clock edge occurs

Address Instruction

InstructionMemory

Write Data

Reg Addr

Reg Addr

Reg Addr

Register

File ALUData

Memory

Address

Write Data

Read DataPC

ReadData

ReadData

331 Lec 14.2 Fall 2002

ExampleLet’s modify the ISA and remove the ability to specify an offset for memory access instructions. Specifically, the load-store instructions would contain only two registers. In other words, all MIPS load-store instructions with offsets would become pseudoinstructions and would be implemented using two instructions:

lw $t0, 104($t1)=>

331 Lec 14.3 Fall 2002

Example cont’d

Instruction

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

ReadData 1

ReadData 2

ALU

overflowzero

ALU controlRegWrite

DataMemory

Address

Write Data

Read Data

SignExtend

MemWrite

MemRead

181717

16 32

16-bit offset

331 Lec 14.4 Fall 2002

Creating a Single Datapath from the PartsAssemble the datapath segments from the last lecture, add control lines as needed, and design the control path

Fetch, decode and execute each instructions in one clock cycle – single cycle design

no datapath resource can be used more than once per instruction, so some must be duplicated (e.g., why we have a separate Instruction Memory and Data Memory)to share datapath elements between two different instruction classes will need multiplexors at the input of the shared elements with control lines to do the selection

Cycle time is determined by length of the longest path

331 Lec 14.5 Fall 2002

Fetch, R, and Memory Access Portions

ReadAddress

Instruction

InstructionMemory

Add

PC

4

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

ReadData 1

ReadData 2

ALU

ovfzero

ALU controlRegWrite

DataMemory

Address

Write Data

Read Data

MemWrite

MemReadSign

Extend16 32

lw

R

R

lw / sw

331 Lec 14.6 Fall 2002

Multiplexor Insertion

MemtoReg

ReadAddress

Instruction

InstructionMemory

Add

PC

4

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

ReadData 1

Read Data 2

ALU

ovfzero

ALU controlRegWrite

DataMemory

Address

Write Data

Read Data

MemWrite

MemReadSign

Extend16 32

ALUSrc

331 Lec 14.7 Fall 2002

Adding the Branch Portion

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

ReadData 1

ReadData 2

ALU

ovfzero

ALU controlRegWrite

DataMemory

Address

Write Data

Read Data

MemWrite

MemReadSign

Extend16 32

MemtoRegALUSrc

ReadAddress

Instruction

InstructionMemory

Add

PC

4 Shiftleft 2

Add

PCSrc

R

lw / swR

lw

Branch not taken, R, lw /sw

331 Lec 14.8 Fall 2002

Adding the ControlSelecting the operations to perform (ALU, Register File and Memory read/write)

Controlling the flow of data (multiplexor inputs)

Information comes from the 32 bits of the instruction

I-Type: op rs rt address offset31 25 20 15 0

R-type:31 25 20 15 5 0

op rs rt rd functshamt

10

Observationsop field always in bits 31-26addr of two registers to be read are always specified by the rs and rt fields (bits 25-21 and 20-16)addr. of register to be written is in one of two places – in rt (bits 20-16) for lw; in rd (bits 15-11) for R-type instructionsbase register for lw and sw always in rs (bits 25-21)offset for beq, lw, and sw always in bits 15-0

331 Lec 14.9 Fall 2002

(Almost) Complete Single Cycle Datapath

ReadAddress

Instr[31-0]

InstructionMemory

Add

PC

Write Data

Read Addr 1

Read Addr 2

Write Addr ALU

ovf

zeroData

Memory

Address

Write Data

Read Data

MemWrite

MemRead

Register

File

ReadData 1

ReadData 2

RegWrite

SignExtend16 32

Shiftleft 2

Add

RegDst

0

1

ALUSrc

0

1

MemtoReg

1

0

PCSrc

1

0

ALUcontrol

ALUOpInstr[5-0]

Instr[15-0]

Instr[25-21]

Instr[20-16]

Instr[15 -11]

4

331 Lec 14.10 Fall 2002

ALU ControlALU's operation based on instruction type and function code

set on less than111

subtract110

add010

or001

and000

FunctionALU control input

(Binvert + Operation)

331 Lec 14.11 Fall 2002

ALU Control, Con’tControlling the ALU makes use of multiple levels of decoding

main control unit generates the ALUOp bitsALU control unit generates ALU control inputs

slt

or

and

subtract

add

desired action

11110101010slt

00110100101or

00010100100and

11010100010subt

01010100000add

01xxxxxxbeq

00xxxxxxsw

00xxxxxxlw

ALU control input

ALUOpfunctInstr op

331 Lec 14.12 Fall 2002

ALU Control Truth Table

0

1

0

0

0

X

X

F0

1

0

0

1

0

X

X

F1

0

1

1

0

0

X

X

F2

1

0

0

0

0

X

X

F3

X

X

X

X

X

X

X

F4

X

X

X

X

X

X

X

F5

1

0

ALUOp0

1

1

1

1

1

0

ALUOp1

1

1

0

0

0

0

0

Op0

1

0

0

1

1

1

1

Op1

1

0

0

1

0

1

0

Op2

Can make use of more don’t caressince ALUOp does not use the encoding 11since F5 and F4 are always 10

Logic comes from the K-maps …

X

X

X

X

X

X

331 Lec 14.13 Fall 2002

ALU Control Combinational LogicFrom the truth table can design the ALU Control logic

Operation2

Operation1

Operation0

Operation

ALUOp1

F3

F2

F1

F0

F (5–0)

ALUOp0

ALUOp

ALU control block

331 Lec 14.14 Fall 2002

(Almost) Complete Datapath with Control Unit

ReadAddress

Instr[31-0]

InstructionMemory

Add

PC

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

ReadData 1

ReadData 2

ALU

ovf

zero

RegWrite

DataMemory

Address

Write Data

Read Data

MemWrite

MemRead

SignExtend16 32

MemtoReg

Shiftleft 2

Add

PCSrc

RegDst

ALUcontrol

1

1

00

0

0

1

ALUOp

Instr[5-0]

Instr[15-0]

Instr[25-21]

Instr[20-16]

Instr[15 -11]

ControlUnit

Instr[31-26]

4

Branch

ALUSrc

1

331 Lec 14.15 Fall 2002

R-type Instruction Data/Control Flow

Instr[15 -11]

Instr[20-16]

Instr[25-21]

ReadAddress

Instr[31-0]

InstructionMemory

Add

PC

4

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

ReadData 1

ReadData 2

ALU

ovf

zero

RegWrite

DataMemory

Address

Write Data

Read Data

MemWrite

MemRead

SignExtend16 32

MemtoReg

ALUSrc

Shiftleft 2

Add

PCSrc

RegDst

ALUcontrol

1

1

1

00

0

0

1

ALUOp

Instr[5-0]

Instr[15-0]

ControlUnit

Instr[31-26]

Branch

331 Lec 14.16 Fall 2002

Store Word Instruction Data/Control Flow

Instr[25-21]

Instr[20-16]ReadAddress

Instr[31-0]

InstructionMemory

Add

PC

4

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

ReadData 1

ReadData 2

ALU

ovf

zero

RegWrite

DataMemory

Address

Write Data

Read Data

MemWrite

MemRead

SignExtend16 32

MemtoReg

ALUSrc

Shiftleft 2

Add

PCSrc

RegDst

ALUcontrol

1

1

1

00

0

0

1

ALUOp

Instr[5-0]

Instr[15-0]

Instr[15 -11]

ControlUnit

Instr[31-26]

Branch

331 Lec 14.17 Fall 2002

Load Word Instruction Data/Control Flow

ReadAddress

Instr[31-0]

InstructionMemory

Add

PC

4

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

ReadData 1

ReadData 2

ALU

ovf

zero

RegWrite

DataMemory

Address

Write Data

Read Data

MemWrite

MemRead

SignExtend16 32

MemtoReg

ALUSrc

Shiftleft 2

Add

PCSrc

RegDst

ALUcontrol

1

1

1

00

0

0

1

ALUOp

Instr[5-0]

Instr[15-0]

Instr[25-21]

Instr[20-16]

Instr[15 -11]

ControlUnit

Instr[31-26]

Branch

331 Lec 14.18 Fall 2002

Branch Instruction Data/Control Flow

ReadAddress

Instr[31-0]

InstructionMemory

Add

PC

4

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

ReadData 1

ReadData 2

ALU

ovf

zero

RegWrite

DataMemory

Address

Write Data

Read Data

MemWrite

MemRead

SignExtend16 32

MemtoReg

ALUSrc

Shiftleft 2

Add

PCSrc

RegDst

ALUcontrol

1

1

1

00

0

0

1

ALUOp

Instr[5-0]

Instr[15-0]

Instr[25-21]

Instr[20-16]

Instr[15 -11]

ControlUnit

Instr[31-26]

Branch

331 Lec 14.19 Fall 2002

Main Control Unit

1X10X0X0Xbeq

000100

0001X0X1Xsw

101011

000011110lw

100011

X100X1001R-type

000000

ALUOp0ALUOp1BranchMemWrMemRdRegWrMemRegALUSrcRegDstInstr

331 Lec 14.20 Fall 2002

Control Unit LogicFrom the truth table can design the Main Control logic

Instr[31]Instr[30]Instr[29]Instr[28]Instr[27]Instr[26]

lw sw beqR-typeRegDst

ALUSrc

MemtoReg

RegWrite

MemRead

MemWrite

Branch

ALUOp1

ALUOp0

331 Lec 14.21 Fall 2002

Adding the Jump Operation

ReadAddress

Instr[31-0]

InstructionMemory

Add

PC

4

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

ReadData 1

ReadData 2

ALU

ovf

zero

RegWrite

DataMemory

Address

Write Data

Read Data

MemWrite

MemRead

SignExtend16 32

MemtoReg

Shiftleft 2

Add

PCSrc

RegDst

ALUcontrol

1

1

00

0

0

1

ALUOp

Instr[5-0]

Instr[15-0]

Instr[25-21]

Instr[20-16]

Instr[15 -11]

ControlUnit

Instr[31-26]

Branch

Shiftleft 2

0

1

Jump

32Instr[25-0]

26PC+4[31-28]

28

ALUSrc

1

331 Lec 14.22 Fall 2002

Single Cycle Implementation Cycle TimeUnfortunately, though simple, the single cycle approach is not used because it is inefficient

Clock cycle must have the same length for every instruction

What is the longest path (slowest instruction)?

331 Lec 14.23 Fall 2002

Instruction Critical PathsCalculate cycle time assuming negligible delays (for

muxes, control unit, sign extend, PC access, shift left 2, wires) except:

Instruction and Data Memory (2ns)ALU and adders (2ns)Register File access (reads or writes) (1ns)

jump

beqstore

load

R-type

TotalReg WrD MemALU OpReg RdI MemInstr.

61212

812212

722125212

22

331 Lec 14.24 Fall 2002

Where We are HeadedProblems with single cycle datapath design

uses clock cycle inefficientlyand what if we had a more complicated instruction like floating point multiply?wasteful of area

Another approachuse a “smaller” cycle timehave different instructions take different numbers of cyclesa “multicycle” datapath:

AddressRead Data

(Instr. or Data)

Memory

PC

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

ReadData 1

ReadData 2

ALU

Write Data

IRM

DR

AB A

LUou

t

331 Lec 14.25 Fall 2002

ReadAddress

Instr[31-0]

InstructionMemory

Add

PC

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

ReadData 1

ReadData 2

ALU

ovf

zero

RegWrite

DataMemory

Address

Write Data

Read Data

MemWrite

MemRead

SignExtend16 32

MemtoReg

Shiftleft 2

Add

PCSrc

RegDst

ALUcontrol

1

1

00

0

0

1

ALUOp

Instr[5-0]

Instr[15-0]

Instr[25-21]

Instr[20-16]

Instr[15 -11]

ControlUnit

Instr[31-26]

Shiftleft 2

0

132

Instr[25-0]

26PC+4[31-28]

28

Complete Datapath

4Jump

Branch

ALUSrc

1

331 Lec 14.26 Fall 2002

Example I: R instruction

RegWriteMemtoReg

ALUSrcMemRead

MemWriteBranch

AlUOp0Jump

ALUOp1RegDst

SettingControl Signal

SettingControl Signal

331 Lec 14.27 Fall 2002

Example I: lw instruction

RegWriteMemtoReg

ALUSrcMemRead

MemWriteBranch

AlUOp0Jump

ALUOp1RegDst

SettingControl Signal

SettingControl Signal

331 Lec 14.28 Fall 2002

Example I: sw instruction

RegWriteMemtoReg

ALUSrcMemRead

MemWriteBranch

AlUOp0Jump

ALUOp1RegDst

SettingControl Signal

SettingControl Signal

331 Lec 14.29 Fall 2002

Example I: beq instruction

RegWriteMemtoReg

ALUSrcMemRead

MemWriteBranch

AlUOp0Jump

ALUOp1RegDst

SettingControl Signal

SettingControl Signal

331 Lec 14.30 Fall 2002

Example II: cycle length

Calculate cycle time assuming negligible delays (for muxes, control unit, sign extend, PC access, shift left 2, wires) except:

Instruction and Data Memory (2ns)ALU (2ns)Register File access (reads or writes) (1ns)Adder for PC+4 (5ns)Adder for branch address computation (5ns)

331 Lec 14.31 Fall 2002

Example III:Describe the effect that a single stuck-at-0 fault (I.e., regardless of what it should be, the signal is always 0) would have on the multiplexors in the single-cycle datapath. Which instruction, if any, would still work? Consider each of the following faults separately: RegDst = 0, ALUSrc = 0, MemtoReg = 0, Zero = 0;

331 Lec 14.32 Fall 2002

Example IV:We wish to add the instruction addi to the single-cycle datapath. Add any necessary datapaths and control signals.

RegWriteMemtoReg

ALUSrcMemRead

MemWriteBranch

AlUOp0Jump

ALUOp1RegDst

SettingControl Signal

SettingControl Signal

331 Lec 14.33 Fall 2002

ReadAddress

Instr[31-0]

InstructionMemory

Add

PC

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

ReadData 1

ReadData 2

ALU

ovf

zero

RegWrite

DataMemory

Address

Write Data

Read Data

MemWrite

MemRead

SignExtend16 32

MemtoReg

Shiftleft 2

Add

PCSrc

RegDst

ALUcontrol

1

1

00

0

0

1

ALUOp

Instr[5-0]

Instr[15-0]

Instr[25-21]

Instr[20-16]

Instr[15 -11]

ControlUnit

Instr[31-26]

Shiftleft 2

0

132

Instr[25-0]

26PC+4[31-28]

28

Complete Datapath

4Jump

Branch

ALUSrc

1

331 Lec 14.34 Fall 2002

ReadAddress

Instr[31-0]

InstructionMemory

Add

PC

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

ReadData 1

ReadData 2

ALU

ovf

zero

RegWrite

DataMemory

Address

Write DataRead Data

MemWrite

MemRead

SignExtend16 32

MemtoReg

ALUSrc

Shiftleft 2

Add

PCSrc

RegDst

ALUcontrol

1

1

1

00

0

0

1

ALUOp

Instr[5-0]

Instr[15-0]

Instr[25-21]

Instr[20-16]

Instr[15 -11]

ControlUnit

Instr[31-26]

Branch

Shiftleft 2

0

1

Jump

3226PC+4[31-28]

28

31

RegDst1

1

0

MemtoReg1

Example V: add jalInstr[25-0]

4

331 Lec 14.35 Fall 2002

Example V: add jal (cont’d)

RegWriteMemtoReg

RegDst1MemtoReg1

ALUSrcMemRead

MemWriteBranch

AlUOp0Jump

ALUOp1RegDst

SettingControl Signal

SettingControl Signal