AAKASH PATEL 101 E San Fernando St, San Jose, CA-95112

(714) 210-9183 | patel.akash102@csu.fullerton.edu LinkedIn: https://www.linkedin.com/in/aakash-patel

Professional Summary Reliable Computer Engineer with 5+ years of academic and 2 years of industrial experience in the field of VLSI

technology. Extensive knowledge in CMOS IC circuit design, FPGA/ASIC design and layout, implementation, pin

placing and routing, debugging and verification. Well versed in Computer Architecture, Semiconductor technologies,

and Embedded systems. Currently looking for a suitable position in an exciting and expanding company.

Experience

Service Engineer, 07/2013 to 08/2014

Angel Industrial Instrumentation - Gujarat, India

Designed and tested various circuits and identified functionality issues.

Worked on projects with a team and gained good experience in VLSI technology.

Managed various projects as per their budget and time limit.

Attained various seminars and participated in various technical events.

Improved communication skill by working in a sales part of the company.

Engineering Student Intern, 08/2012 to 06/2013

Angel Industrial Instrumentation - Gujarat, India Worked on a project named book issuing system. Learned about the functionality of components such as PIC

microcontroller, RFID tag, and GSM modem.

Embedded above mentioned components and build data transformation through the RS232 serial port.

Developed leadership skills through working with other interns in the same project.

Coordinated senior engineer in the examination of various projects.

Academic Projects

5 stage 32-bit pipelined processor, 06/2016 to 08/2016

Developed Verilog code for five stages of ARM processor. 32-bit ARM instruction decomposed through fetch,

decode, execute, memory and write back stages. Compiled and simulated Verilog code with Xilinx ISE tool. Verified design by giving two different instructions

which performed addition and subtraction operation.

Cache Memory Controller, 01/2016 to 05/2016

Generated Verilog code for cache module through Icarus Verilog. Developed modules for memory and cache

controller. Successfully tested code by generating test bench and analyzing hit and miss rate of inputs.

XOR gate implementation using GDI technique, 01/2016 to 05/ 2016

Compared XOR implementation of general CMOS technology with gate diffusion input (GDI) technique.

Developed HSPICE code for XOR circuit based on GDI technique implementation.

Observed propagation delay, static and dynamic power dissipation of 32nm and 22nm technology nodes

through Cosmosscope. Achieved a low power dissipation and less delay in GDI technology based circuit.

VGA Display, 08/2015 to 12/2015

Prepared Verilog code and simulated in Xilinx Vivado tool. Programmed project code on Nexys 4 FPGA board

and worked on 25 MHz clock frequency.

Analyze output in the monitor by connecting it to FPGA board through a serial port.

RC4 Cryptographic Algorithm, 01/2015 to 05/2015

Built encryption code for the RC4 algorithm which is used in various cryptography process. Developed ciphertext

by combining plain text and keystream.

Programmed in C language through turbo C tool.

Professional Skills

Programming Languages: Verilog, System

Verilog, VHDL, C, C++, SystemC, MIPS Assembly,

Matlab, Python

Tools: Xilinx Vivado, Xilinx ISE Design Suite,

Quartus Prime, Icarus Verilog, UVM, PCBWEB

designer, Electric CAD, Hspice, LTspice, Multisim,

Modelsim, ScanExpress, Leonardo Spectrum,

Cadence Virtuoso, MS Suite

Protocol: UART, SPI, RS-232, I2C

FPGAs: Nexys 4 DDR, Spartan3

Platforms: Windows, Linux, Mac OS

Computer Architecture: 8085 and 8086

Microprocessors, 8051 Microcontroller, ARM

processor, 8237 DMA Controller, DRAM, SRAM,

Nand Flash, RISC and CISC instruction set

CMOS Technology: Low Power Techniques,

Mixed Signal Techniques, Transistor Sizing,

Analog/Digital IC Design and layout, Transistor

Analysis (Static/Dynamic Power dissipation,

Leakage current, Delays)

Education

Master of Science

Computer Engineering, December 2016

California State University, Fullerton

California, US

Bachelor of Engineering

Electronics and Communication, May 2013

Gujarat Technological University, Surat

Gujarat, India

Certification SOC Verification using SystemVerilog - UC-CTMJM60D – Udemy

Boundary Scan Training – Corelis Inc.