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Advances in Radio Science (2003) 1: 223–228c© Copernicus GmbH 2003 Advances in
Radio Science
Resonance circuits for adiabatic circuits
C. Schlachta and M. Glesner
Darmstadt University of Technology, Institute of Microelectronic Systems, Germany
Abstract. One of the possible techniques to reduces thepower consumption in digital CMOS circuits is to slow downthe charge transport. This slowdown can be achieved by in-troducing an inductor in the charging path. Additionally, theinductor can act as an energy storage element, conserving theenergy that is normally dissipated during discharging. To-gether with the parasitic capacitances from the circuit a LC-resonant circuit is formed.
1 Introduction
In conventional CMOS logic the load capacitor is charged toVDD via the PMOS block (pull up network) and dischargedto GND via the NMOS block (pull down network). Duringthe charging of the output, the power supply has to deliver achargeQ = CLVDD at the voltageVDD resulting in a sup-plied energy ofQVDD = CLV 2
DD. that dissipats as heat.To decrease the dissipated energy, the charge transport can
be slowed down. Using a ramp-like charging voltage, theoutput capacitance is charged at a constant current. This cur-rent source delivers the chargeCLVDD over a period of timeT . The dissipation through the resistance of the chargingpathR is then (Chandrakasan and Brodersen, 1995):
Ediss = P · T = I2RT =
(CLVDD
T
)2
RT
=
(RCL
T
)CLV 2
DD . (1)
This shows that it is possible to charge and discharge a ca-pacitance through a resistance while dissipating less energythanCLV 2
DD. By introducing an energy storage element, theenergy that is normally dissipated as capacitances are dis-charged can be conserved for later use. This can be observed
Correspondence to:C. Schlachta([email protected])
in LC resonant circuits, where the energy oscillates betweenthe capacitance and the inductance.
To determine the efficiency of a resonant circuit, theamount charge per charging/discharging cycle of an idealabrupt charge/discharge circuit can be compared to the av-erage charge required by the oscillator.
Eoscillator,percycle =iavg,osc
fosc
(2)
Eabrupt,percycle = Cload · Vdd (3)
In the equationsCload is the sum of all capacitances inthe resonance circuit andfosc the frequency of the oscillator.From this equations we can determine the efficiency of anoscillator
η =Eoscillator,percycle
Eabrupt,percycle
=
iavg,osc
fosc
CLoad · Vdd
(4)
This means, that at a resonant circuit with an efficiency of70% dissipates only 30% of the power of an abrupt chargingcircuit.
2 Multi-stage charging
A very simple approach to implement a charging/dechargingcircuit is to use multi-stage charging (Saas et al., 2001).Multi-stage charging is not a LC oscillator due to its miss-ing inductor however it is presented here as comparisionto the other resonant oscillators. The basic concept is tocharge/discharge the capacitance stepwise inn steps eachwith the voltageVstep =
Vsupply
n.
Multi-stage charging also reuses the charge stored in theload capacity. Under the assumption that the pull-up tran-sistors charge the load to the full supply voltage, the powerdissipation for discharging is the same as for charging. Itis not necessary to use power supplies for the intermediatevoltages because the average current is zero in the ideal case.
224 C. Schlachta and M. Glesner: Resonant circuits
�� �
� ��
�
�
� ��
�
�
� ��
�
�
Fig. 1. Principle of multi-stage charging.
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109
1010
0
10
20
30
40
50
60
70
80
90
Frequency [Hz]
Channel width [m]
Effi
cien
cy [%
]
Fig. 2. Efficiency for 5-stage (4 intermediate voltages) charg-ing/discharging.
Instead, large buffering capacitors are sufficient. These ca-pacitors must be charged to the desired voltage just at startupand afterwards it is only necessary to compensate losses.
The efficiency of the multi-stage charging is assessedthrough a simulation that is depicted in Fig. 2. This simu-lation was done for a five step circuit, this means four in-termediate voltages are used. The current consumption iscalculated for a load capacity of 1500 pF, the current con-sumed by the control logic is estimated to be equal to the cur-rent needed for driving the pass transistor gates. This means,that the current is twice the current consumed by driving thepass transistor gates. The channel length of the transistors is0.35µm and the circuit is supplied with 3.3 V. The top area
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Fig. 3. Schematic of the one transistor oscillator.
1
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50
60
70
80
90
100
Quality factor QChannel width n−MOS [m]
Effi
cien
cy [%
]at
f= 1
0MH
z
Fig. 4. Efficiency for one transistor oscillator.
of the graph shows the range for usefull operation. Increas-ing the channel width leads to bad efficieny because of therising current consumption for the control logic. The otherlimitation is the charging time, increasing the operating fre-quency reduces the time period for charging/discharging theload capacity. If the time interval is getting to small the loadcapacity can not be completely charged or discharged. Con-sequently case multi-stage charging is not applicable in thiscase.
3 Continuously oscillating circuits
3.1 One transitor resonant circuit
The simplest attempt to design a resonant circuit is the 1-transistor circuit depicted in Fig. 3 (Voss, 2001). The gateof the transistor is driven by a control signal that must be de-rived from an other oscillator, i.e. a crystal oscillator. Besidesthe control of the frequency the gate driver logic has also tocontrol the duty cycle of the transistor. The efficiency dia-gram of this oscillator is depicted in Fig. 4. This diagramresults from a simulation with a transistor channel lengthof wn = 0.35µm, a resonant capacity ofCres = 1500 pF,an inductance withLres = 170 nH and a supply voltage ofVosc = 1.65 V. The oscillation frequency is about 10 MHz.The gate of the MOSFET is driven with a pulse widthpw =
10 ns (equiv. to a duty cycle of≈ 10%) and a periode ofper = 100 ns (resonance frequency). The power consump-tion of the driver logic for the transistor gate was also taken
C. Schlachta and M. Glesner: Resonant circuits 225
1
10
100
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10−20
1
2
3
4
5
Quality factor QChannel width n−MOS [m]
Osc
illat
or a
mpl
itude
[V]
Fig. 5. One transistor oscillator: Variation of the quality factor ofthe inductor.
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0
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0
1
2
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5
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7
Periode duration: Deviationfrom resonance frequency [%]
Channel width n−MOS [m]
Osc
illat
or a
mpl
itude
[V]
for
a qu
ality
fact
or Q
= 2
5
Fig. 6. One transistor oscillator: Amplitude as function of variationof the control frequency.
into account. It’s value was estimated as twice the powerneeded for driving only the gate of the MOSFET.
In Fig. 3.1 the amplitude of the oscillator as a function ofthe channel width of the MOSFET and the quality factor ofthe inductor is shown. It can be seen that only for very highquality factors of the inductor and small channel width of theMOSFET the amplitude of the oscillation differs from thenominal value (3.3 V, twice the oscillator voltage).
In Fig. 3.1 the periode duration of the gate drive signal isvaried from the period duration at resonance frequency (fre-quency mismatch) and the resulting oscillator amplitude isdrawn. It can be seen very clearly that the oscillator is onlyworking well within in the range of some percent around theresonance frequency. This limits also changes in the load ca-pacity because these changes are equal to changes in the res-onance frequency as it can be derived from the calculation of
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Fig. 7. Two transistor oscillator.
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0
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0
1
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Periode duration: Deviationfrom resonance frequency [%]
Channel width n−MOS [m]
Osc
illat
or a
mpl
itude
[V]
for
a qu
ality
fact
or Q
= 2
5
Fig. 8. Two transistor oscillator: Amplitude as function of variationof the control frequency.
the resonance frequency:
fresonance,actual
fresonance,nominal
=
√Cactual
Cnominal
(5)
This equation shows, that the deviation in the load capac-itance must also be in the range of some percent around thenominal value for a stable operation.
3.2 Two-transistor oscillator
The one transistor oscillator can be expanded to a push-pushstage by adding ap-MOSFET and the necessary controllogic. This stage behaves mostly like the single transistor os-cillator previously presented. It can be clearly seen in Fig. 8that this circuit is also not stable against mismatch betweencontrol and resonance frequency or varying the load capacity.
3.3 H-bridge oscillator
If the circuitry needs a sine signal with as well 0◦ as 180◦
phase shift, the two-transistor oscillator can be extended tothe H-bridge shown in Fig. 9 (Voss, 2001). The main ad-vantages of the H-bridge are the stable phase shift between
226 C. Schlachta and M. Glesner: Resonant circuits
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Fig. 9. H-bridge with four transistors.
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1
2
3
4
5
Quality factor QChannel width n−MOS [m]
Osc
illat
or a
mpl
itude
[V]
Fig. 10. H-bridge: Amplitude for varying quality factor of the in-ductor.
the two outputs and the use of only one inductor. The sta-bility against mismatch between control and resonance fre-quency or variation of the capacitances is even worse com-pared to both the one-transitor and the two-transistor oscilla-tor (Fig. 8).
4 Controlled resonance circuit
Another approch is the oscillator circuit shown in Fig. 13(Schlachta et al., 2002; Athas et al., 1996). Contrary to theprevious discussed oscillators this resonane cell doesn’t os-cillate continuously.
We start the discussion of the circuit by assuming that theconnected load has to change its state. That triggers the cir-cuit, which behaves like a clocked latch. The actual voltageover the resonance capacitor determines the needed transi-tion and is saved in an RS flip flop in the control logic duringthe whole transition. The power transistor (depicted as idealswitch) is switched on and starts the resonant process by con-necting the inductor to
Vsupply
2 This starts a resonant oscilla-
tion with an amplitude of alsoVsupply
2 , achieving a voltage
swing betweenVsupply
2 −Vsupply
2 = 0 andVsupply
2 +Vsupply
2 =
V dd. Therefore it is only necessary to stop the oscillation atthe desired voltage level to get the demanded change in the
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80
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100
Quality factor QChannel width n−MOS [m]
Effi
cien
cy [%
]at
f= 1
0MH
z
Fig. 11. H-bridge: Efficiency for varying quality factor of the in-ductor.
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0
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6
Periode duration: Deviationfrom resonance frequency [%]
Channel width n−MOS [m]
Osc
illat
or a
mpl
itude
[V]
for
Q=
25
Fig. 12. H-bridge:
voltage of the load. If these levels are the minimum or max-imum voltages of the resonant circuit, the inductor containsno energy so that the free wheeling diodes are not needed. Acomparator is used to determine the threshold at which thepower transistor is switched off. Since there are two thresh-olds, one for switching fromLOW to HIGH and one forswitching fromHIGH to LOW , two comparators adjust-ing the switching thresholds are used where the active oneis selected depending on the initial value of the resonancecapacitor. To ensure constant levels after switching, a tris-tate buffer is used. This buffer is enabled when the switchingcycle is finished and pulls up or down the resonant capaci-tor, thus compensating the energy and the consequent voltagelosses in the resonant ciruit.
Because the resistance of the charging/discharging path in-fluences the energy dissipation in the design (see Eq. 1), thepower transistors had to be made very wide. On the otherhand, the width of the switching transistors is responsible forthe gate capacitance that has to be charged and dischargedconventionally each switching cycle, thence dissipating en-
C. Schlachta and M. Glesner: Resonant circuits 227
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Fig. 13. Controlled oscillator cell.
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Channel width n−MOS [m]
Inductance [H]
Sw
itchi
ng ti
me
[s]
Fig. 14. Controlled oscillator: Switching as function of inductance.
ergy. Thereby, the channel widths of the transistors are atradeoff between the resistive loss in the resonant circuit es-pecially at full load as well as the switching losses due to thegate capacitance at small load.
Another subject to tradeoff is the value of the resonant ca-pacitor. The resonant capacitor together with the switchableand thereby variable load capacitances forms the resonantcapacitance and determines the switching time and thus theslew rate. To achieve a small range of switching time be-tween no load and full load it is necessary and advantageousto use a large additional capacitor (in the range of the max-imum load capacitance). The drawback of a large resonantcapacitor is that it significantly increases switching losses es-pecially with less load capacitance. As a compromise, theresonant capacitor is sized equal to one third of the maximumload capacitance, achieving a change of 1:
√3 + 1 ≈ 1 : 2
in the switching time between minimum (no load) and fullload.
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Channel width n−MOS [m]
Quality factor Q
Effi
cien
cy p
er c
ycle
[%]
(cha
rge
and
dech
arge
)
Fig. 15. Controlled oscialltor: efficiency as function of quality fac-tor.
5 Conclusions
Several oscillator designs have been presented. All of thesedesigns have their advantages and drawbacks:
– Multi stage charging is only applicable for limited fre-quencies; the design without an inductor and the highefficiency makes it a good choice for circuits with lowerclock frequencies.
– The one- and two-transistor oscillator and H-bridgehave a good efficiency but they all require a nearly con-stant load capacitance. This limits the application tonets with a constant capacitvie load, e.g. the clock neton a chip.
– The controlled oscillator contains some difficult to im-plement components like the analog comparators, andthe operating speed is limited because of the difficultturn-off detection. On the other hand the ability to driveloads with varying capacity makes it very flexible. Con-sequently it is a good choice for I/O-buffers and similiarapplications.
As a result can be said, that none of the proposed con-cepts is an optimal choice for all application. Nevertheless,through a careful selection of the oscillator type accordingto the demands of the load it is possible to find very goodsolutions for a broad range of applications.
Acknowledgements.This work is granted by the DeutscheForschungsgemeinschaft as part of the VIVA project under the labelGL 144/18-2.
References
Athas, W., Svenson, J., and Tzartzanis, N.: A resonant signal driver-for two-phase, almost-non-overlapping clocks, in Proceedings ofthe ISCAS 1996, pp. 129–132, 1996.
228 C. Schlachta and M. Glesner: Resonant circuits
Chandrakasan, A. P. and Brodersen, R. W.: Low Power Digi-tal CMOS Design, chap. 7: Minimizing Switched Capacitance,Kluwer Academic Publishers, 1995.
Saas, C., Schlaffer, A., and Nossek, J. A.: An adiabatic multi stagedriver, in Proc. of ECCTD’01 European Conference on CircuitTheory and Design, 2001.
Schlachta, C., Voss, B., and Glesner, M.: A low-power line driver
using resonant charging, in Design Automation and Test Europe(DATE), 2002.
Voss, B.: Resonantes Umladen als Schaltungstechnik zur Ver-lustleistungsreduktion in digitalen CMOS-Schaltungen, Ph.D.thesis, TU Darmstadt, Shaker Verlag, ISBN: 3-8265-9800-8,2001.
