Research and Innovation Action - Flex5Gware and Innovation Action ... use case mapping and related activities time plans. ... Dieter Ferling ALUD [email protected]

PROPRIETARY RIGHTS STATEMENT

This document contains information, which is proprietary to the Flex5Gware Consortium.

Research and Innovation Action

Flex5Gware

Flexible and efficient hardware/software platforms for 5G network elements and devices

H2020 Grant Agreement Number: 671563

WP6 – Proof of concept in Flex5Gware

D6.1 - Preliminary PoC evaluation in Flex5Gware

Contractual Delivery Date: 30/06/2016 Actual Delivery Date: 30/06/2016 Responsible Beneficiary: TST Contributing Beneficiaries: IMC, ALUD, CEA, CNIT, CTTC, EAB, F-IAF, iMinds, KU

Leuven, NEC, SEQ, TI, TST, UC3M, UNI Pisa, VTT, WINGS

Dissemination Level: Public Version: 1.0

PROPRIETARY RIGHTS STATEMENT

This document contains information, which is proprietary to the Flex5Gware Consortium.

This page is left blank intentionally

H2020 Grant Agreement Number: 671563 Document ID: WP6 / D6.1

Dissemination Level: Public Page 3

Document Information

Document ID: D6.1

Version Date: 30/06/2016

Total Number of Pages: 139

Abstract: This document contains the first and complete description of Flex5Gware Proof of Concepts in terms of technology to be used, partner roles and descriptions, preliminary Test object lists, use case mapping and related activities time plans.

Keywords: Proof of Concept, Test object list, KPI, demonstrator, performance, test

Authors

Full Name Beneficiary / Organisation

e-mail Role

Dieter Ferling ALUD [email protected] PoC 4/11 leader / Contributor

Daniel Markert ALUD [email protected] Contributor Apostolos Georgiadis CTTC [email protected] Contributor Fermin Mira CTTC [email protected] Contributor Ana Collado CTTC [email protected] Contributor

Nikolaos Bartzoudis CTTC [email protected] PoC 7 leader / Contributor

Marco Miozzo CTTC [email protected] Contributor

Oriol Font CTTC [email protected] Contributor

Miquel Payaró CTTC [email protected] Contributor

Javier Valiño TST [email protected] Editor / Contributor

Pablo Pelayo TST [email protected] Contributor

Sergio Martín TST [email protected] Contributor

Carlos Lavín TST [email protected] Contributor

Thomas Olsson EAB [email protected] PoC 1 leader / Contributor

Stefan Andersson EAB [email protected] Contributor

Tony Påhlsson EAB [email protected] Contributor

Hendrik Rogier iMinds [email protected] PoC 2 leader / Contributor

Sam Agneessens iMinds [email protected] Contributor

Patrick Reynaert KU Leuven [email protected] Contributor



Paramartha Indirayanti KU Leuven [email protected] Contributor

Atso Hekkala VTT [email protected] PoC 3 leader / Contributor

Haesik Kim VTT [email protected] Contributor

Rüdiger Quay F-IAF [email protected] Contributor

Kilian Roth IMC [email protected] PoC 5 leader / Contributor

Leonardo Gomes Baltar

IMC [email protected] Contributor

Mustafa Emara IMC [email protected] Contributor

Sylvie Mayrargue CEA [email protected] Contributor

Patrick Rosson CEA [email protected] Contributor

David Dassonville CEA [email protected] Contributor

Manuel Pezzin CEA [email protected] Contributor

Xavier Popon CEA [email protected] Contributor

Valentin Savin CEA [email protected] Contributor

Tushar Gupta CEA [email protected] Contributor

Pablo Serrano UC3M [email protected] Contributor

Vincenzo Mancuso UC3M/IMDEA [email protected] Contributor

Domenico Giustiniano UC3M/IMDEA domenico.giustiniano @imdea.org Contributor

Héctor Cordobés de la Calle

UC3M/IMDEA [email protected] Contributor

Maurizio Rea UC3M/IMDEA [email protected] Contributor

Ilenia Tinnirello CNIT [email protected] PoC 8 leader / Contributor

Panagiotis Vlacheas WINGS [email protected] Contributor

Vassilis Foteinos WINGS [email protected] Contributor

Evaggelia Tzifa WINGS [email protected] Contributor

Aikaterini Demesticha WINGS [email protected] Contributor

Orestis Liakopoulos WINGS [email protected] Contributor

Dimitris Kelaidonis WINGS [email protected] Contributor

Vassilis Kaldanis WINGS [email protected] Contributor

Marios Logothetis WINGS [email protected] Contributor

Kostas Tsagkaris WINGS [email protected] Contributor

Vera Stavroulaki WINGS [email protected] Contributor

Ioannis Stenos WINGS [email protected] Contributor

Panagiotis Demestichas

WINGS [email protected] Contributor

Yiouli Kritikou WINGS [email protected] Contributor

Vangelis Argoudelis WINGS [email protected] Contributor

Felipe Huici NEC [email protected] PoC 9 leader / Contributor

Jose Mendes NEC [email protected] Contributor



Francesco Mauro TIM [email protected] PoC 10 leader / Contributor

Dario Sabella TIM [email protected] Contributor

Valerio Palestini TIM [email protected] Contributor

Marco Careti TIM [email protected] Contributor

Gian Michele Dell'Aera TIM [email protected] Contributor

Antonio Virdis UNI Pisa [email protected] Contributor

Giovanni Stea UNI Pisa [email protected] Contributor

Antonio Frangioni UNI Pisa [email protected] Contributor

Giovanni Nardini UNI Pisa [email protected] Contributor

Niccolò Iardella UNI Pisa [email protected] Contributor

Reviewers

Full Name Beneficiary / Organisation

e-mail Date

Miquel Payaró CTTC [email protected] 01/06/2016 Dario Sabella TI [email protected] 01/06/2016 Vassilis Foteinos WINGS [email protected] 01/06/2016 Pablo Serrano UC3M [email protected] 01/06/2016

Kilian Roth IMC [email protected] 01/06/2016 Javier Valiño TST [email protected] 01/06/2016 Dieter Ferling ALUD dieter.ferling@nokia-bell-

labs.com 22/06/2016

Michael Faerber IMC [email protected] 22/06/2016 Rautio Tapio VTT [email protected] 22/06/2016

Version history

Version Date Comments 1.0 30/06/2016 D6.1 submission



Executive Summary

This document serves as a first complete report of the relevant information related to Flex5Gware Proof of Concept (PoC) demonstrators. The present D6.1 deliverable includes information about the motivation of each PoC, the partners and technologies involved, the proposal on architecture and preliminary definition of Test Object List (TOL), including individual hardware/software/interface validation as well as high level testing. Next D6.2 deliverable will contain an update of the TOLs and will include the final test results for all PoCs in Flex5gware. In fact, since the design and implementation phase (in WP2-5) is still on-going, it may happen that PoCs in WP6 will need to modify some testbench configurations (e.g. number of terminals involved, characteristics of traffic levels, power levels or system parameters setup), and consequently also to update testing methodologies for the assessment of KPIs (also in order to improve the accuracy, or the relevance of the test to the quantification of the gains). Eleven PoC demonstrators have been proposed in Flex5Gware project. PoC 1 focuses on frequency generation up to 60GHz, with a prototype operating at 28GHz, where the objective is low cost and low power consumption in CMOS technology. PoC 2 deals with active SIW antennas integrating a power amplifier. The operating band in this case lies within the 17-30GHz interval. PoC 3 addresses linearity/distortion reduction by developing new PAPR reduction and power amplifier pre-distortion techniques. PoC 4 involves the design of a multiband transmitter. PoC 5 proposes a full duplex filter bank multicarrier transceiver. PoC 6 addresses MIMO and high-throughput decoders, while PoC 7 proposes an experimental validation of flexible HW/SW partitioning. PoC 8 targets software re-configurability of 5G systems and aims to demonstrate reconfiguring the radio behaviour according to advanced context estimates and different optimization criteria. The scope of PoC 9 is to build a flexible, scalable small cell platform able to allow third parties to deploy localized processing based on raw samples or higher-layer traffic (e.g. TCP/UDP). PoC 10 addresses the effects of resource allocation algorithms for CRAN/VRAN networks. Finally, PoC 11 proposes a multi-chain MIMO transmitter, with multi-chain RF signal generation and a power amplifier.



Table of Contents

1. Introduction ..................................................................................................... 201.1 PoCs and testing activities in WP6 ....................................................................211.2 PoC ID cards ........................................................................................................221.3 Use cases and KPIs in WP6 ...............................................................................23

2. Test Object List (TOL) definition .................................................................... 252.1 Description ..........................................................................................................252.2 Device under test (DUT) scheme .......................................................................262.3 Test bench setup specification ..........................................................................262.4 Test procedure description ................................................................................272.5 Test results ..........................................................................................................27

3. On chip frequency generation (PoC 1) .......................................................... 283.1 Short description ................................................................................................283.2 Partners and roles ...............................................................................................283.3 Test Object List ...................................................................................................28

3.3.1 Device under test (DUT) scheme ......................................................................293.3.2 Elementary test 1: 60GHz VCO Measurements ................................................303.3.3 Elementary test 2: 60GHz PLL Measurements ..................................................303.3.4 Elementary test 3: 28GHz PLL Measurements ..................................................313.3.5 Tests results ......................................................................................................31

3.4 Use case mapping ...............................................................................................333.5 Additional considerations ..................................................................................333.6 Time plan and availability ...................................................................................33

4. Active SIW (Substrate Integrated Waveguide) antennas with integrated power amplifiers in the frequency range of 17 to 30GHz (PoC 2) ....................... 35

4.1 Short description ................................................................................................354.2 Partners and roles ...............................................................................................364.3 Test Object List ...................................................................................................36

4.3.1 Device under test (DUT) scheme ......................................................................374.3.2 Elementary test 1: Stand-alone antenna ...........................................................384.3.3 Elementary test 2: Stand-alone PA ....................................................................404.3.4 Elementary test 3: Integrated antenna and PA ..................................................424.3.5 Test results .......................................................................................................43

4.4 Use case mapping ...............................................................................................44



4.5 Additional considerations ..................................................................................444.6 Time plan and availability ...................................................................................45

5. PAPR reduction and power amplifier predistortion (PoC 3) ........................ 465.1 Short description ................................................................................................465.2 Partners and roles ...............................................................................................475.3 Test Object List ...................................................................................................48

5.3.1 Device under test (DUT) scheme ......................................................................485.3.2 Elementary test 1: PAPR performance ..............................................................495.3.3 Test results .......................................................................................................49


6. Multiband transmitter (PoC 4) ........................................................................ 526.1 Short description ................................................................................................526.2 Partners and roles ...............................................................................................536.3 Test Object List ...................................................................................................53

6.3.1 Device under test (DUT) scheme ......................................................................546.3.2 Elementary test 1: operating bandwidth ............................................................556.3.3 Elementary test 2: flexibility, frequency agility ...................................................556.3.4 Test results .......................................................................................................56


7. Full duplex FBMC (Filter Bank Based MultiCarrier) transceiver (PoC 5) .... 587.1 Short description ................................................................................................587.2 Partners and roles ...............................................................................................597.3 Test Object List ...................................................................................................59

7.3.1 Device under test (DUT) scheme ......................................................................607.3.2 Elementary test 1: RF SIC performance ............................................................617.3.3 Elementary test 2: HSIC performance measurement .........................................627.3.4 Elementary test 3: DSIC performance measurement .........................................637.3.5 Elementary test 4: aggregated SIC performance measurement ........................647.3.6 Test results .......................................................................................................65

7.4 Use case mapping ...............................................................................................65



7.5 Additional consideration ....................................................................................667.6 Time plan and availability ...................................................................................66

8. High-Speed Low Power LDPC Decoder (PoC 6) ........................................... 678.1 Short description ................................................................................................678.2 Partners and roles ...............................................................................................688.3 Test Object List ...................................................................................................68

8.3.1 Device under Test (DUT) scheme .....................................................................698.3.2 Elementary test 1: ASIC Synthesis Results .......................................................708.3.3 Elementary test 2: ASIC Power Consumption estimated ...................................708.3.4 Elementary test 3: FPGA Emulation ..................................................................718.3.5 Test results .......................................................................................................72


9. HW/SW function split for energy aware communications (PoC 7) .............. 749.1 Short description ................................................................................................749.2 Partners and roles ...............................................................................................769.3 Test Object List ...................................................................................................78

9.3.1 Device under test (DUT) scheme ......................................................................799.3.2 Elementary Tests ..............................................................................................829.3.3 Tests Results ....................................................................................................88


10. Reconfigurable and programmable radio platform (terminal side) and SW programming performed and injected by the network (PoC 8) .......................... 93

10.1 Short description ................................................................................................9310.2 Partners and roles ...............................................................................................9510.3 Test Object List ...................................................................................................96

10.3.1 Device under test (DUT) scheme ..................................................................9710.3.2 Elementary test 1: Adaptation Mechanisms in WiFi – LTE-U co-existence Scenario 10010.3.3 Elementary test 2: Location-based capture effect mitigation ........................ 10110.3.4 Elementary test 3: Reconfiguration of an LTE eNodeB network stack ......... 10310.3.5 Test results .................................................................................................. 104



10.4 Use case mapping ............................................................................................. 10510.5 Additional considerations ................................................................................ 10610.6 Time plan and availability ................................................................................. 107

11. Flexible, scalable and reconfigurable small cell platform (PoC 9) .........10811.1 Short description .............................................................................................. 10811.2 Partners and roles ............................................................................................. 11011.3 Test Object List ................................................................................................. 110

11.3.1 Device under test (DUT) scheme ................................................................ 11111.3.2 Elementary test 1: Re-configurability time .................................................... 11111.3.3 Elementary test 2: network bandwidth-latency correlation ........................... 11211.3.4 Test results .................................................................................................. 113


12. Flexible resource allocation in CRAN/VRAN platform (PoC 10) .............11512.1 Short description .............................................................................................. 11512.2 Partners and roles ............................................................................................. 11612.3 Test Object List ................................................................................................. 116

12.3.1 Device under test (DUT) scheme ................................................................ 11712.3.2 Elementary test 1: assessing the energy efficiency .................................... 11912.3.3 Elementary test 2: assessing the user data rate improvement .................... 12212.3.4 Elementary test 3: assessing the flexibility .................................................. 12512.3.5 Test results .................................................................................................. 126


13. Multi-Chain MIMO Transmitter (PoC 11) ...................................................12913.1 Short description .............................................................................................. 12913.2 Partners and roles ............................................................................................. 13013.3 Test Object List ................................................................................................. 130

13.3.1 Device under test (DUT) scheme ................................................................ 13113.3.2 Elementary test 1: assessing the multi-chain RF signal generation ............. 13113.3.3 Elementary test 2: assessing the PA performance ...................................... 13213.3.4 Elementary test 3: assessing the system performance ................................ 132



13.3.5 Tests results ................................................................................................ 13313.4 Use case mapping ............................................................................................. 13413.5 Additional considerations ................................................................................ 13413.6 Time plan and availability ................................................................................. 135

14. Conclusions ................................................................................................136

15. References ..................................................................................................137



List of Figures

Figure 1-1. High level overview of the Flex5Gware concept. ................................................20Figure 1-2. Use case families and relation to the PoCs [Fle11]. ............................................23Figure 2-1. DUT scheme example. .......................................................................................26Figure 2-2. Testbench example. ...........................................................................................27Figure 3-1. PLL targeting a 28GHz sliding-IF transceiver. ....................................................29Figure 3-2. General test setup. .............................................................................................30Figure 4-1. Antenna component consisting of closely integrated PA and antenna. ...............35Figure 4-2. SIW slot antenna. ...............................................................................................37Figure 4-3. CMOS power amplifier. ......................................................................................38Figure 4-4. Lumped components amplifier. ...........................................................................38Figure 4-5. Test bench for stand-alone antenna. ..................................................................39Figure 4-6. Test bench for stand-alone PA. ..........................................................................41Figure 4-7. Test bench for integrated PA and antenna .........................................................42Figure 5-1. ETTUS X310 and B200 SDR devices in VTT 5G Lab. ........................................47Figure 5-2. User Interface (Real-time LTE-based system). ...................................................47Figure 5-3. PoC 3 ToL Testbench. ........................................................................................48Figure 6-1. Block diagram of a multiband transmitter test setup. ..........................................52Figure 6-2. Block diagram of a multiband transmitter (DUT). ................................................54Figure 6-3. Block diagram of the test setup. .........................................................................55Figure 7-1. Interference generated in half duplex and full-duplex for scenario of [San14]. ....58Figure 7-2. Planned demonstrator hardware – Digital Baseband board and ARRadio (AD9361) component. ..........................................................................................................59Figure 7-3. PoC 5 Devices under test. ..................................................................................60Figure 7-4. Illustration of expected interference cancellation along the receiver chain. .........61Figure 7-5. Setup for elementary RFSIC measurement. .......................................................62Figure 7-6. Setup for elementary HSIC measurement. .........................................................63Figure 7-7. Setup for elementary DSIC measurement. .........................................................63Figure 7-8. Setup for elementary HSIC measurement. .........................................................64Figure 8-1. Proposed electronic card to be used for design validation ..................................67Figure 8-2. Proposed hardware for design validation ............................................................68Figure 8-3. Iterative design flow considered for PoC 6 ..........................................................69Figure 8-4. Envisaged demonstration setup as expected in month 23 ..................................71Figure 9-1. A high-level overview of the PoC 7 architecture. .................................................74



Figure 9-2. DC power consumption breakdown for different types of BSs at maximum load [Ear10]. .................................................................................................................................75Figure 9-3. The Xilinx ZC706 board. .....................................................................................80Figure 9-4. The AD-FMCOMMS3-EBZ board. ......................................................................80Figure 9-5. CTTC’s EXTREME testbed. ...............................................................................81Figure 9-6. Overview of LENA’s LTE-EPC simulation model. ...............................................81Figure 9-7. The DUT and interfaces of the PoC 7. ................................................................81Figure 9-8. The NETCFG#1. ................................................................................................83Figure 9-9. A snapshot of the measurement campaign log-file (due to be conducted for this test case). .............................................................................................................................84Figure 9-10. The NETCFG#2. ..............................................................................................85Figure 9-11. The NETCFG#3. ..............................................................................................86Figure 9-12. The PoC 7 setup for the real-time demonstration. ............................................87Figure 9-13. Gantt chart of PoC 7. ........................................................................................91Figure 10-1. Reconfigurable programmable radio platform. ..................................................93Figure 10-2. PoC 8 devices, functionalities and roles. ..........................................................95Figure 10-3. DUT elements. .................................................................................................97Figure 10-4. Capture effect experiment setup ..................................................................... 102Figure 10-5. PoC 8 Test#3 testbed ..................................................................................... 103Figure 10-6. Experimental procedure ................................................................................. 104Figure 11-1. Overall PoC Architecture. ............................................................................... 109Figure 11-2. Use case: accurate user location. ................................................................... 109Figure 11-3. Components of the device under test. ............................................................ 111Figure 12-1. Hexagonal cell with Macro and Micro layer. .................................................... 115Figure 12-2. Elements involved within the PoC. .................................................................. 116Figure 12-3. Ettus B210. ..................................................................................................... 117Figure 12-4. Overall connections. ....................................................................................... 117Figure 12-5. General Test Scenario (1 macro cell and 2 micro cells). ................................. 118Figure 12-6. Wiring diagram. .............................................................................................. 118Figure 12-7. Offered traffic. ................................................................................................. 119Figure 12-8. Current clamp. ................................................................................................ 119Figure 12-9. Step1. ............................................................................................................. 120Figure 12-10. Step 2a. ........................................................................................................ 120Figure 12-11. Step 2b. ........................................................................................................ 120Figure 12-12. Step 3. .......................................................................................................... 121Figure 12-13. Step 4a. ........................................................................................................ 121



Figure 12-14. Step 4b. ........................................................................................................ 121Figure 12-15. High-level architecture and interfaces. .......................................................... 122Figure 12-16. System Setup A. ........................................................................................... 123Figure 12-17. System Setup B. ........................................................................................... 124Figure 12-18. Scenario. ...................................................................................................... 125Figure 12-19. Network changes. ......................................................................................... 125Figure 13-1. Block diagram of a multi-chain transmitter test setup. ..................................... 130Figure 13-2. Block diagram of a multi-chain transmitter. ..................................................... 131



List of Tables

Table 1-1. List of PoCs. ........................................................................................................22Table 1-2. Consolidated KPIs in WP1. ..................................................................................23Table 3-1. PoC 1 partner roles. ............................................................................................28Table 3-2. PoC 1 KPI table. ..................................................................................................28Table 3-3. PoC 1 60GHz VCO test results. ...........................................................................31Table 3-4. PoC 1 28GHz PLL test results. ............................................................................32Table 3-5. PoC 1 60GHz PLL test results. ............................................................................32Table 3-6. Baseline for 60GHz VCO. ....................................................................................32Table 3-7. PoC 1 time plan. ..................................................................................................34Table 4-1. PoC 2 partner roles. ............................................................................................36Table 4-2. PoC 2 KPI table. ..................................................................................................36Table 4-3. Baseline for SIW antenna performance. ..............................................................39Table 4-4. Baseline 18GHz amplifier performance using the Triquint 2023-2—01 device [Qor16] .................................................................................................................................40Table 4-5. Baseline for CMOS PA ........................................................................................41Table 4-6. Test results ..........................................................................................................43Table 4-7. PoC 2 time plan. ..................................................................................................45Table 5-1. PoC 3 partner roles. ............................................................................................48Table 5-2. PoC 3 KPI table. ..................................................................................................48Table 5-3. PoC 3 test results. ...............................................................................................50Table 5-4. PoC 3 time plan. ..................................................................................................51Table 6-1. PoC 4 partner roles. ............................................................................................53Table 6-2. PoC 4 KPI table. ..................................................................................................53Table 6-3. PoC 4 test 1 results. ............................................................................................56Table 6-4. PoC 4 test 2 results. ............................................................................................56Table 6-5. PoC 4 time plan. ..................................................................................................57Table 7-1. PoC 5 partner roles. ............................................................................................59Table 7-2. PoC 5 KPI table. ..................................................................................................60Table 7-3. Average performance gain of full-duplex vs half-duplex as a function of interference cancellation level. .............................................................................................60Table 7-4. KPI relationship to PoC 5. ....................................................................................61Table 7-5. PoC 5 test results. ...............................................................................................65Table 7-6. PoC 5 time plan. ..................................................................................................66Table 8-1. PoC 6 partner roles. ............................................................................................68



Table 8-2. PoC 6 KPI table. ..................................................................................................68Table 8-3. PoC 6 Devices under Test. ..................................................................................69Table 8-4. PoC 6 test results. ...............................................................................................72Table 8-5. PoC 6 time plan. ..................................................................................................72Table 9-1. PoC 7 partner roles. ............................................................................................77Table 9-2. PoC 7 KPI table. ..................................................................................................78Table 9-3. The KPIs that PoC 7 targets. ...............................................................................79Table 9-4. The test cases involving NETCFGs, WCPs and different KPIs. ...........................82Table 9-5. The baseline configuration specifications. ...........................................................82Table 9-6. NETCFG#1 testbench setup. ...............................................................................83Table 9-7. The test procedure steps. ....................................................................................83Table 9-8. Real-time demonstration testbench setup. ...........................................................87Table 9-9. The test procedure steps. ....................................................................................87Table 9-10. PoC 7 NETCFG#1 Results. ...............................................................................89Table 9-11. PoC 7 NETCFG#2 Results. ...............................................................................89Table 9-12. PoC 7 NETCFG#3 Results. ...............................................................................90Table 9-13. PoC 7 time plan. ................................................................................................91Table 10-1. PoC 8 Partner roles. ..........................................................................................95Table 10-2. PoC 8 KPI table. ................................................................................................96Table 10-3. The KPIs that PoC 8 targets. ........................................................................... 100Table 10-4. Test results ...................................................................................................... 105Table 10-5. PoC 8 Time plan. ............................................................................................. 107Table 11-1. PoC 9 partner roles. ........................................................................................ 110Table 11-2. PoC 9 KPI table. .............................................................................................. 110Table 11-3. KPI relationship to PoC 9. ................................................................................ 111Table 11-4. PoC 9 results. .................................................................................................. 113Table 11-5. PoC 9 Time Plan. ............................................................................................ 114Table 12-1. PoC 10 partner roles. ....................................................................................... 116Table 12-2. PoC 10 KPI table. ............................................................................................ 117Table 12-3. KPI relationship to PoC 10. .............................................................................. 118Table 12-4. PoC 10 Test 1 Results. .................................................................................... 126Table 12-5. PoC 10 Test 2 Results. .................................................................................... 127Table 12-6. PoC 10 Test 3 Results. .................................................................................... 127Table 12-7. PoC 10 time plan. ............................................................................................ 128Table 13-1. PoC 11 partner roles. ....................................................................................... 130



Table 13-2. PoC 11 KPI table. ............................................................................................ 130Table 13-3. PoC 11 test 1 results. ...................................................................................... 133Table 13-4. PoC 11 Results of test 2 results. ...................................................................... 134Table 13-5. PoC 11 test 3 results. ...................................................................................... 134Table 13-6. PoC 11 time plan. ............................................................................................ 135



List of Acronyms and Abbreviations

Term Description 3GPP 3rd Generation Partnership Project ACLR Adjacent Channel Leakage Ratio ADC analogue to digital converter ASIC Application-Specific Integrated Circuit BLE Bluetooth Low Energy BW Bandwidth CA Carrier Aggregation CAD Computer Assisted Design CMOS Complementary Metal Oxide Semiconductor CoMP Coordinated Multi-Point CRAN Cloud RAN DAC digital to analogue converter DSP Digital Signal Processor EVM Error vector magnitude FBMC Filter Bank Based Multi Carrier FD-SOI Fully Depleted Silicon On Insulator FPGA Field Programmable Gate Array IBFD In Band Full-Duplex IMD3 Inter Modulation Distortion from the third order of a circuit IP Internet Protocol LDPC Low Density Parity Check LO Local Oscillator LPF/BPF Low pass / band pass filter LTE Long Term Evolution MEC Mobile Edge Computing MIMO Multiple Input Multiple Output MMIC Monolithic Microwave Integrated Circuits MSU Michigan State University MVNO Mobile Virtual Network Operator NFV Network Function Virtualization OAI Open Air Interface OFDMA Orthogonal Frequency-Division Multiple Access



PA Power Amplifier PAE Power-Added Efficiency PAPR Peak-to-Average Power Ratio PLL Phase-Locked Loop PoC Proof-of-Concept RAN Radio Access Network RF Radio Frequency RSSI Received Signal Strength Indicator SDR Software Defined Radio SDN Software Defined Network SDR Software Defined Radio SEM spectrum emission mask SIC Self Interference Cancellation SIW Substrate Integrated Waveguide SoC System on Chip SoTA State of The Art SPI Serial Peripheral Interface TCP Transmission Control Protocol TOL Test Object List TTL Transistor-transistor Logic UDP User Datagram Protocol UHD Universal Hardware Driver VHDL VHSIC Hardware Description Language VHSIC Very High Speed Integrated Circuit VCO Voltage-Controlled Oscillator VM Virtual Machine VRAN Virtual RAN WP Work Package XFSN Cross-platform Finite State Machine



1. Introduction Flex5Gware aims at delivering and demonstrating key building blocks of hardware and software platforms capable to meet the demanding requirements of 5G systems in terms of capacity, energy consumption and scalability, with the required flexibility and re-configurability, thus ensuring a seamless transition from the preceding 4G systems. The goal of WP6 is to demonstrate 5G technologies and services, in terms of proof of concepts (PoCs), both in standalone (demonstration of a single technology, usually by a single partner) and integrated way (demonstration of more than one technology in a single PoC, usually via collaboration among partners). Involved partners develop and provide (in collaboration with the other WPs) the proof of concepts / demonstrations of the 5G key building blocks developed within Flex5Gware. While WP2-WP5 are focused on the design, implementation and validation of technology-specific enhancements, typically based on standalone platforms, effort in WP6 consists in integration activities for the integrated PoCs and validation, testing and demonstration for all the PoCs (both standalone and integrated).

Figure 1-1. High level overview of the Flex5Gware concept.

Flex5Gware provides key building blocks in 4 domains, namely Software, Digital Hardware, Mixed-signal and conversion stages and Analogue domains (coloured blocks on Figure 1-1 denotes technical heterogeneity, while grey ones stand for HW-agnostic functions and interface abstractions). The Flex5Gware PoCs presented in this deliverable are represented by dashed ovals.



In close cooperation with the technology developments carried out in WP2-5, WP6 activities are described in the following:

• Definition of the final list of PoCs, starting from the initial list contained in the Flex5GwareDescription of Work (DoW);

• For each one of the PoCs, a Test Object List (ToL) has been defined, with related KPI of interest (e.g., energy efficiency, capacity, etc.) in accordance with the overall project goals [Fle11];

• Harmonization with use cases and scenarios defined in Flex5Gware’s D1.1 [Fle11]; • Validation and testing of standalone (single technology) PoCs; • Integration, validation and testing of integrated (multiple technologies) PoCs; • Definition and writing of measurements reports, with related performance evaluations and

analysis; • Hosting demonstrations, showcases, presentations, also in synergy with other 5GPPP

projects when appropriate (e.g. joint demonstrations with 5G PPP projects); This document includes the first consolidated version of PoCs to be demonstrated as a result of Flex5Gwareproject. Moreover, D6.1 aims at refining the first PoC definition already made on DoW document by giving further details and elaborating more on the test procedure. The report is structured as follows: some initial subsections in Section 1 include important definitions in the framework of WP6 activities: subsection 1.1 describes the PoCs and related testing activities in WP6, then subsection 1.2 contains the definition of PoC ID cards in WP6, while use cases, scenarios and KPIs are presented in subsection 1.3 from a WP6 perspective, together with their relationship with other WPs in Flex5Gware. Then Section 2 contains a detailed description of a TOL, as an anticipation of the main content of D6.1 deliverable, while each of Sections 0 to 0is devoted to a PoC in Flex5Gware and contains current version of the PoC details updated by all involved partners. Finally, Section 14 concludes this deliverable. 1.1 PoCs and testing activities in WP6

A PoC is defined as a SW and/or HW platform used to demonstrate technologies and services in the framework of Flex5Gware project. It starts from an innovative idea expected to provide enhancements with respect to the current situation and aims at proving its key assumptions through a hardware and/or software setup. In order to address the fundamental application of the use cases targeted by Flex5Gware, which have been documented in detail in D1.1 [Fle11], eleven PoCs have been identified and are being developed over the course of the project. These PoCs are being tested during the project lifetime, and finally demonstrated during a final demonstration event hosted by Telecom Italia in Turin (Italy). The PoCs are being assessed by partners (making use of all the information provided on each PoC section, including KPIs) in order to address the needs of the various use cases identified in the project; and at the same time their final demonstration will highlight the background and technology advancement gained by project partners. The PoC demonstrators target to improve on Key Performance Indicators (KPIs) which have been identified in D1.1 based on the use cases under consideration. Table 1-1 below contains a concise summary of the PoCs, the partners involved, and the Technology Readiness Level (TRL) of the demonstrators (TRL 3: experimental proof of concept, TRL 4: technology validated in lab).



Table 1-1. List of PoCs. PoC Innovative proof of concept Involved partners TRL

1 On chip frequency generation EAB 4

2 Active SIW antenna systems for the 20-40GHz band iMinds, CTTC, KU Leuven 4

3 PAPR reduction and power amplifier predistortion VTT, F-IAF, CTTC, SEQ 3

4 Multiband transmitter ALUD, F-IAF 4

5 Full duplex FBMC transceiver CEA, IMC 3

6 High-speed low power LDPC decoder CEA 4

7 HW/SW function split on SoC prototyping board for energy aware communications UC3M, CTTC 4

8 Reconfigurable and programmable radio platform (terminal side) and SW programming performed and injected by the network

CNIT, WINGS, UC3M, TST 4

9 Flexible, scalable and reconfigurable small cell platform NEC 4

10 Flexible resource allocation in CRAN/vRAN platform TI, UNIPI 4

11 Multi-chain MIMO Transmitter ALUD, F-IAF 4

1.2 PoC ID cards

As already stated above, D6.1 aims at extending the level of detail of the first PoC definition presented in the DoW by giving additional details and elaborating further on the test procedure. Following this main objective, PoC “ID cards” have been defined in WP6 in order to practically identify all PoCs and related testing and demonstration activities. In accordance with WP6 goals, these documents are structured so as to cover all aspects related to PoC definition and test procedure. This document captures in sections 3-13 the current status of PoC ID cards, where separate subsections are created in order to cover the following topics:

• The first subsection of each PoC description is dedicated to the general description of the demonstrator itself. It includes the motivation, state of the art reference providing the starting point of each PoC and, if applicable, the overall architecture. This last item is critical to the PoC definition, as it is used as reference on later sections. The architecture is presented as a figure, in which all hardware devices, software modules implemented on top of the aforementioned hardware devices and interfaces between either software or hardware modules are identified.

• Using the previous subsection as reference, each PoC description includes in addition a list of partners and roles of the activity. For each partner included, details on the specific HW, SW and interfaces impacted by their work are given, stressing also the role they are playing for building the demonstrator (leader, HW/SW provider, and integrator).

• On a subsequent subsection, each PoC description defines its Test Object List (TOL). This section is oriented to identify the KPIs to be used for the performance assessment of the PoC. These KPIs are inherited from WP1 proposal already available at D1.1 [Fle11]. For each selected KPI, specific info about how to evaluate it with respect to PoC equipment and proposals are given. In addition, TOL is used to guide and assess the testing phase of each individual PoC, setting the base procedures for evaluating and leaving room to present results.



• The fourth subsection on each PoC description contains further WP1 alignment, in this case, with respect to use cases. Use cases families, use cases and test cases are provided as a result of D1.1 delivery. PoC classification with respect to use cases is already presented on the aforementioned document. This document aims at giving further details, based on D1.1 content, with respect to the impact of each PoC on the related use cases.

• Subsection five of each PoC contains additional details about requirements, key challenges and other information with the aim to further clarify PoC contents, scope and envisaged impact.

• Finally, the time plan for all modules regarding each PoC is presented, in accordance with all committed deadlines present on the project proposal.

This way, a complete definition of PoC scope, test procedure and expected results is given. 1.3 Use cases and KPIs in WP6

Flex5Gware use cases families, specific use cases and project level KPIs have been collected in WP1 by following a bottom-up approach (see also D1.1 for more details [Fle11]). As an illustration on how the use cases connect to use case families, an overview is provided in the following figure.

Figure 1-2. Use case families and relation to the PoCs [Fle11].

Similarly, by following this bottom-up approach, the KPIs relevant to Flex5Gware have also been derived in WP1. This list of KPIs (see table below) will be used at project level for the final evaluation of project level results in D1.3 (for more details please refer to D1.1 [Fle11]).

Table 1-2. Consolidated KPIs in WP1.

Consolidated KPIs in WP1 Acronym

Flexibility / versatility / re-configurability FVR

Cost CST

Energy efficiency NRG

Resilience and continuity RES



Mobile data volume • Aggregated data rate

• Coverage / ubiquitous access MDV

Number of users / connected devices NoU

Bandwidth • Radio bandwidth

• Operation bandwidth BW

Latency LAT

User data rate UDR

Integration / size / footprint ISF

Then, given the wide scope of the research topics addressed in Flex5Gware, these derived high level KPIs have to be particularized in different tasks outside WP1 for each one of the four technology areas addressed in Flex5Gware, which correspond to following work packages:

• WP2: RF front-ends and antennas

• WP3: Mixed-signal technologies

• WP4: Digital front-ends and HW/SW function split

• WP5: SW modules and functions These particularizations yield to specific design principles, requirements, and guidelines for the development of the corresponding enabling technologies in each one of those areas. Since WP6 is focused on testing, integration and demonstration activities, the term KPI (from WP6 perspective) could be further specialized with respect to the specific demonstration and testing needs: in fact, in case a KPI in WP1 (e.g. energy efficiency) is defined at cluster or network level, while the related PoC showcase will be performed with a small scale prototype (i.e. with few network nodes), for practical reasons in ease of demonstration. As a consequence, testing activities will be referred in WP6 (from now on) to “measurable KPIs”, in the sense that only KPIs subject to tests will be considered and reported in TOLs at the end of WP6 activities. Then, these KPIs could be extrapolated in WP1 for more comprehensive considerations (e.g. by aiming at the assessment of energy efficiency in a cluster of nodes or at country-wide level in order to evaluate the energy consumption of the mobile network).



2. Test Object List (TOL) definition As it has been described above, Flex5Gware is addressing a selected set of key building blocks for HW and SW platforms, thus it is very important to clarify and illustrate the advanced capabilities and concrete progress PoCs in the project with respect to the state of the art. In fact, PoCs are intended not only as live demonstrations to be showcased in the final dissemination event, but also prototypes to be tested and assessed during the project lifetime, thus providing more insight on the performances of the implemented technologies. The selected (standalone or integrated) PoCs are demonstrated and evaluated in order to determine how each proposed technology solution meets the specified requirements and improve the KPIs. The definition of the evaluation procedure is significant, as each test procedure reflects the methodology and approach used to assess the capabilities. To this respect, each contribution includes a test plan of the selected technique. The general purpose of a test plan is to describe the scope of the plan, the approach of the test technique and the resources utilization. Furthermore a test plan also identifies the items to be tested, the features being tested and the testing tasks to be performed. In this document, the test plan of each contribution is illustrated as a first contribution for the definition of TOL. 2.1 Description

A TOL is defined as a (short) reference document used to describe the overall testing methodology (a reference commonly used in standardization for TOLs can be found in [ETS07]). In the context of Flex5Gware project, the TOLs described in D6.1 contain:

1. Architecture of the device under test (DUT), 2. Descriptions of the test setup, 3. Step by step description of the test procedure, 4. Results Table (that will be filled by test results as they become available, in D6.2

deliverable). Each of the above items is defined in detail in the next subsections. In case of considering more than one elementary test on the device/PoC, items 2 and 3 are iterated for a number of times corresponding to the tests considered.

o Example: a certain PoC may foresee a first test for assessing the energy efficiency, and a second one for the latency: in that case, it may happen that the PoC needs to be tested in these two schemes, in principle slightly different, and the procedure may differ since the KPIs to be measured are different.

Regarding the list of elementary tests planned (items 2 and 3), each one contains essentially the following fields: Item 2:

• OBJECTIVE: this field indicates the aim of the test, in other words, the functionality/device to be checked, and the targeted KPI.

• INTERFACES: this is a list of the interfaces involved in the test.

• PRECONDITIONS (optional): this describes the phases of preparation that have to be carried out to bring all elements of the system to the initial conditions necessary for performing the test.

• PRIORITY: the importance given to performing the test compared to others.



Item 3:

• PROCEDURE DESCRIPTION: this describes the sequence of actions to perform to solicit the functionality/device under test.

• NOTES (optional): comments, explanations or suggestions about the test.

• REFERENCES (optional): the specifications and documents offering more information on problems with the test.

For the time being, since the design of different technologies is still ongoing, TOLs are only in a draft status (and may be subjected to changes in D6.2): in the following most of the PoCs generally contain a scheme of the DUT, a short draft description of a possible test bench (at high level), and a draft time plan for the tests. 2.2 Device under test (DUT) scheme

This section consists on the specification of the device(s) under test (understanding “device” as an individual hardware or software module or even and algorithm including several modules), along with a DUT scheme representing the system implementation (including hardware and/or software modules) that are evaluated. The scheme includes a graphical representation of the DUT modules, the interactions and interconnections between the DUT modules. An example of a DUT scheme is provided in the following figure:

Figure 2-1. DUT scheme example.

2.3 Test bench setup specification

The DUT of the above section is possibly accompanied by a set of hardware devices e.g. an external transmitter, a spectrum analyzer, communication protocols e.g. WiFi, Ethernet and software functions e.g. a software toolkit or interface. The test bench setup specification refers to the description of the environment, in which the model under development is tested, with the aid of software and hardware tools. An example of a test bench scheme is provided in the following figure:



Figure 2-2. Testbench example.

2.4 Test procedure description

This section holds a specific description of the test procedure, referring to the sequence of steps in the procedure. The procedure’s steps include the starting and the ending point of the test along with inputs and the expected functionality of the modules or the higher level model. In the following list, we provide an example test procedure:

1. Launch external transmitter. 2. Launch software testing tool. 3. Perform actions. 4. Waveform evaluation.

The final step may also include an expected outcome to be evaluated from the results. 2.5 Test results

A final table includes the actual resulting values or events of the test procedure. The results may be combined with the expected outcome and metrics, as specified in each testing scenario. The table may also include information for the past requirements, number of tests and further logging information. On the following sections, each PoC is described individually and integrating all the information described.



3. On chip frequency generation (PoC 1) On-chip frequency generation is a key part of all high performance transceivers. The quality of the local oscillator (LO) signal provides fundamental limitations to the achievable data rate, receiver selectivity, transmitter spurious and noise emissions, etc. In advanced transceivers there is also typically a need for highly accurate quadrature signals. In Flex5Gware, we target mmWave beamforming systems, where high precision phase control is desired to transmit signals simultaneously to several transceivers. The required precision and signal quality, the high operating frequency, and the large number of transceivers pose significant cost and power challenges. The work at PoC 1 “On chip frequency generation” aims at the on-chip frequency generation for both upcoming 28GHz 5G mobile beamforming systems and envisioned 60GHz ones. 3.1 Short description

The scope of this PoC covers the full frequency generation system, including transport of signals to receiving blocks, e.g. up and down conversion mixers. As a first step, frequencies up to 30GHz are studied, but extended to also include 60GHz scenarios as part of the cooperation with the third party Lund University (LU). Key aspects in the study comprise performance parameters like power consumption, phase noise etc, but also production aspects like low cost technology options and co-integration in monolithic radio SoCs where signal integrity is important. For a 5G system to become an alternative on the market, device cost and power consumption has to be kept low. The goal for the EAB studies in Flex5Gware is to reduce cost in terms of die size and fabrication process and reduce power consumption compared to state of the art. 3.2 Partners and roles

This is a standalone PoC. EAB roles are described on the following table. Table 3-1. PoC 1 partner roles.

Partner Devices Interfaces Role EAB PLL (Phase-Locked

Loop) for 28 and 60GHz operation

NA PoC leader, development of PLL circuits

3.3 Test Object List

As described in previous sections, the goal of this PoC is to cover the frequency generation system. The selected KPIs (among the ones proposed on Flex5Gware WP1) for this purpose are described on the following table.

Table 3-2. PoC 1 KPI table. KPI Related Use Case(s) Comment CST Crowded

venues/Dynamic hotspots

CMOS is selected as a low-cost option for high integration level. The frequency synthesizer must be area efficient to enable integration of many transceiver chains in a massive MIMO implementation.

FVR Performance equipment

The frequency synthesizer needs to operate over a wide frequency range.



NRG Dynamic hotspots The frequency synthesizer must have low energy consumption to enable integration of many transceiver chains in a massive MIMO implementation.

BW Performance equipment

The frequency synthesizer needs to operate over a wide frequency range with good phase noise properties.

ISF Crowded venues/Dynamic hotspots

CMOS is selected as a low-cost option for high integration level. The frequency synthesizer must be area efficient to enable integration of many transceiver chains in a massive MIMO implementation.

3.3.1 Device under test (DUT) scheme

PoC 1 considers the following devices.

• 60GHz VCOs in 28nm FD-SOI (Fully Depleted Silicon On Insulator). The work on local oscillator generation for 60GHz transceivers is ongoing. We have started on the key building blocks in high frequency PLLs, the oscillator and frequency divider. Frequency dividers are under design, and oscillators have been designed, fabricated and measured to evaluate the achievable performance of 60GHz VCOs implemented in 28nm SOI CMOS.

• PLL for a 28GHz and 60GHz RF receivers in 28nm FD-SOI. The chip has a reference signal input, where a frequency reference common to other chips in the system is received. On the chip there are phase-locked loops (PLLs) using the reference signal and generating the high frequency local oscillator signals needed by the mmWave transceiver. By using one separate PLL per transceiver, only the reference signal needs to be distributed over the chip, which is much lower in frequency compared to the LO signal and hence easier to distribute. Each PLL can also have an individually programmable phase to support beamforming. In this work we investigate such PLL frequency generation for two different frequency bands, 28GHz and 60GHz. Figure 3-1 below shows the 28GHz PLL. There is a strong emphasis on minimum silicon area and power consumption, still meeting the stringent requirements of cellular systems. More details on the PLL designs are found in [Fle21].

Figure 3-1. PLL targeting a 28GHz sliding-IF transceiver.



The general test setup is illustrated in Figure 3-2. For the PLL measurements we use a SPI (Serial Peripheral Interface) interface to control a multiplexer to output the wanted signal. For illustration purpose the figure includes a spectrum analyser, but the measurement equipment also includes oscilloscope and a specialized phase-noise measurement unit.

Figure 3-2. General test setup.

3.3.2 Elementary test 1: 60GHz VCO Measurements 3.3.2.1 Testbench setup specification

3.3.2.2 Test procedure description

First, a PCB has to be built. The low-frequency signals are bonded and the high-frequency signals are probed. The VCO is connected to a control voltage and its output is measured with different measurement instruments, e.g. spectrum analyzer, oscilloscope or phase noise analyzer. 3.3.3 Elementary test 2: 60GHz PLL Measurements 3.3.3.1 Testbench setup specification

Objective Measure the VCO power consumption, phase noise, and tuning range

Interfaces Signal generator, power sensor and meter, DC source, phase noise analyser

Preconditions PCB built Priority High

Responsible partners EAB (LU)

Objective Measure the PLL power consumption, phase noise, tuning range, and phase control accuracy

Interfaces Signal generator, power sensor and meter, DC source, phase noise analyzer

Preconditions PCB built




The PLL is connected to a reference source and its output is measured with different measurement instruments, e.g. spectrum analyzer, oscilloscope or phase noise analyzer. 3.3.4 Elementary test 3: 28GHz PLL Measurements

There is no separate 28GHz VCO measurement, since it is not implemented as a stand-alone component. The main reason is that since it is a lower frequency, it is closer to previous background activities. 3.3.4.1 Testbench setup specification


The PLL is connected to a reference source and its output is measured with different measurement instruments, e.g. spectrum analyzer, oscilloscope or phase noise analyzer. 3.3.5 Tests results

Table 3-3 to Table 3-5 give the performance parameters, target values and test results. Some target values are still to be decided, values are to be updated for D6.2.

Table 3-3. PoC 1 60GHz VCO test results.

Requirements Expected Results (Preliminary)

Observed Results Observed Results Comments

Tuning range ~11% 10.9% 11.1% -

Phase noise <-110dBc/Hz -109.9dBc/Hz -116.5dBc/Hz -

Power consumption

< 3.5mW 3.15mW 3.15mW -

Priority High

Responsible partners EAB (LU)

Objective Measure the PLL power consumption, phase noise, tuning range, and phase control accuracy

Interfaces Signal generator, power sensor and meter, DC source, phase noise analyzer

Preconditions PCB built

Priority High

Responsible partners EAB



Table 3-4. PoC 1 28GHz PLL test results.

Requirements Expected Results

(Preliminary)

Observed Results Comments

Tuning range 2GHz - -

Phase noise 44.8dBc - -

Power consumption Per PLL

13mW - -

Phase control accuracy 12 deg - -

Table 3-5. PoC 1 60GHz PLL test results.

Requirements Expected Results

(Preliminary)

Observed Results Comments

Tuning range TBD GHz - -

Phase noise TBD dBc - -

Power consumption Per PLL

TBD mW - -

Phase control accuracy TBD deg - -

As baseline, the PLL circuit in [Sir15] consumes 33mW and has 0.51ps integrated jitter. The circuit in [Agr16] has superior phase noise (0.10ps), but consumes very high power, 87mW per PLL. The baseline for the 60GHz VCO is given in Table 3-6. Results for two already measured VCOs (VCO-1 and VCO-2) are also given in the same table.

Table 3-6. Baseline for 60GHz VCO.

VCO -1 VCO-2 [Chi15] [Fei14] [Jai13]

Technology (CMOS)

28nm FD-SOI

28nm FD-SOI

90nm bulk

65nm bulk

65nm bulk

Supply Voltage (V)

0.9 0.9 1.2 1 1.2

Frequency (GHz)

67.3 64 61.3 61 59.3

Tuning Range (%)

10.9 11.1 8.44 14.2 39



Power consumption (mW)

3.15 3.15 7.2 6 10.4

PN@10MHz (dBc/Hz)

-109.9 -116.5 -90.9 (1MHz)

-108.3 -110.3

FOM

(dBc/Hz) -181 -187 -178.1

(1MHz) -178.7 -173.7

Area (mm2) 0.0088 0.016 0.34 (incl. pads)

0.031 0.074

3.4 Use case mapping

For a 5G system to become attractive on the broader market, including IoT, device cost and power consumption has to be kept low. The goal for this PoC is thus to improve these parameters compared to state of the art. Although the usage of high performing, cost efficient clock and frequency generation is paramount for many of the outlined use cases, special focus is put on the use case families Massive internet of things – (performance equipment) and Broadband access in dense areas – (crowded venues and dynamic hotspots) as these together combine the urge for cost efficient and flexible/versatile high frequency hardware. Use-case family - Massive internet of things

• Use-case - performance equipment

Need for high performing frequency generation components in high-frequency bands for maximum throughput

Use-case family - Broadband access in dense areas • Use-case - crowded venues

Need for cost efficient and versatile frequency generation components in high-frequency bands

• Use-case - dynamic hotspots • Need for low-power frequency generation components in high-frequency bands in a

small-cell deployment 3.5 Additional considerations

No additional considerations are presented in addition to the previous PoC 1 description. 3.6 Time plan and availability

The below table shows the plan of the work for PoC 1.



Table 3-7. PoC 1 time plan.

Component/Task M1 M6 M12 M18 M24

28GHz PLL Preliminary definition

PLL implemented

PLL evaluated, updated PLL with extended tuning range implemented

Updated PLL evaluated

PoC Demonstration

Building blocks for 60GHz PLL

VCO implemented

VCO initial measurements

VCO evaluated, updated VCO implemented, frequency dividers implemented

PoC Demonstration -

60GHz PLL - - Preliminary definition

PLL implemented, updated VCO and frequency dividers evaluated

PLL evaluated, PoC Demonstration



4. Active SIW (Substrate Integrated Waveguide) antennas with integrated power amplifiers in the frequency range of 17 to 30GHz (PoC 2) Frequency bands above 10GHz are of interest to 5G communication systems due to their large fractional bandwidth. At these frequencies parasitic effects and interconnection losses are high compared to lower frequency systems and the performance of the first stages of the RF front-end becomes even more important for the overall system performance. Typically, the components of the front-end are designed independently, matched to a 50 Ω input and output impedance, and later concatenated. This has the advantage of an easier design, but optimal overall performance is often not obtained due to losses in the matching circuits, long interconnects, or because active circuits (such as PAs) perform better at impedances which are quite different from 50 Ω. Furthermore, the higher interconnection parasitic effects and short wavelength at high frequencies often result in stability issues, such as unwanted feedback loops and oscillations and signal integrity problems. To overcome these drawbacks, a co-design paradigm, where different subsystems are designed simultaneously, can be adopted. The requirement of matching each individual component to 50 Ω at in- and output can be omitted and interconnection lengths can be kept short. The goal of this PoC is to investigate the potential of an active antenna co-design for 5G applications frequencies above 15GHz. The active antenna that is the focus of the work is a Substrate Integrated Waveguide cavity backed slot antenna which is directly integrated with a power amplifier. Two types of power amplifiers are developed in parallel: a PA fabricated in CMOS technology, operating around 28GHz and a lumped element PA operating around 17GHz. The performance of the co-design will be compared to the results of a standard procedure configuration where the individual components are independently designed and concatenated. 4.1 Short description

PoC 2 is developing an active SIW antenna with integrated power amplifier for operation in the 17-30GHz frequency range (Figure 4-1). Therefore, PoC 2 is carrying out full-wave/circuit co-design of the planar antenna and a power amplifier. Both the power amplifiers proposed by KU Leuven and CTTC will be developed for integration with the iMinds antenna. For both, an integrated active transmit antenna are being designed, fabricated and tested. Next, these proofs of concepts will be characterized in terms of energy efficiency by comparing the fully integrated solution to a straightforward interconnection of a PA with the antenna. This work is being performed in close collaboration with KU Leuven and CTTC as their PA solutions must interface with the antenna.

Figure 4-1. Antenna component consisting of closely integrated PA and antenna.



4.2 Partners and roles

The following table illustrates the partner involvement of PoC 2. Table 4-1. PoC 2 partner roles.

Partner Devices Interfaces Role iMinds Passive Planar Antenna Interface of antenna

and PA PoC responsible, development of passive antenna and integration of PA/antenna

KU Leuven

28 nm CMOS Power amplifier

Interface of antenna and PA

Development of PA, support in interfacing and testing interconnected/integrated solution

CTTC Hybrid Power Amplifier Interface of antenna and PA

Development of hybrid PA, support in interfacing and testing interconnected/integrated solution


PoC 2 has selected, among all KPIs identified at project level, the following set of KPIs so as to assess the proper performance of the test bed.

Table 4-2. PoC 2 KPI table. KPI Related Use Case(s) Comment ISF Smart cities

Performance equipment Small dimensions of mmWave wavelength allows for the realization of small footprint antennas (order of 1x1 cm2) Antenna on low profile substrate (250 µm) Compact HW due to co-design

NRG Smart cities Antenna design with high radiation efficiency (> 60%) Efficient PA design: 23% for CMOS and 42% for lumped components PA

BW Performance equipment Antenna with large operation bandwidth (1.5GHz) PA with large operation bandwidth

UDR Performance equipment Connected vehicles (part 2: V2X communications for enhanced driving)

By providing large bandwidth owing to the operation at mmWave frequencies (1.5GHz)

NoU Smart cities Performance equipment

By providing large bandwidth owing to the operation at mmWave frequencies (1.5GHz)

CST Smart cities Performance equipment

PA consisting of off-the-shelf components




The device under test for the PoC is an active SIW cavity-backed slot antenna, which comprises an antenna integrated with a power amplifier. The stand-alone components that form the integrated DUT are:

1) Antenna (iMinds) The antenna design exploits the Substrate Integrated Waveguide technology, which exhibits excellent performance in terms of electromagnetic shielding. This provides high isolation between the radiating antenna and the active components in close proximity, as such heavily reducing the risk on instabilities due to unwanted coupling. A second goal is obtaining a large impedance bandwidth. The substrate integrated waveguide technology is the ideal candidate to leverage bandwidth enhancement techniques. Owing to the operation at mmWave frequencies, high user data rates can be provided and a large number of users can be served. An additional benefit of the SIW technology is the possibility of extremely compact antenna designs. Moreover, due to the excellent shielding properties, stand-alone antennas can be combined in close proximity in a compact array configuration. By opting for a thin substrate material (250 µm), the design is low-profile as well. The SIW antenna is being designed for integration with a PA, as such facilitating easy interfacing.

Figure 4-2. SIW slot antenna.

2) PA (KUL and CTTC) A 28GHz CMOS transformer-based Doherty Power Amplifier is being designed at KUL (Figure 4-3). The approach is to determine how much output power can be generated from the 28 nm CMOS technology at 28GHz, while maintaining acceptable efficiency, linearity and high bandwidth. The foreseen amount of data rate will be enormous and the amplifier is going to operate at mmWave frequencies, hence efficient energy usage is of prime interest. Power combining techniques are being used to boost the output power, but the challenge is to come up with a compact, low loss and broad band solution. Since the PA is realized on chip, the size of the passives needs to be minimized to reduce the overall area. Transformer-based combining is a good candidate on both the energy efficiency and footprint front. An off-the-shelf lumped component Hybrid Power Amplifier in a selected frequency band within the 17-30GHz band is being developed at CTTC (Figure 4-4). The frequency band from 17.7GHz to 19.7GHz has been initially targeted. A high efficiency topology, such as class-F, is targeted to maximize the energy efficiency. Moreover, losses are minimized by optimizing the substrate thickness, permittivity and loss tangent.



Different waveguide technologies, such as microstrip, coplanar waveguide and substrate integrated waveguide, are being explored to optimize the circuit layout and performance, as well as to facilitate easy interfacing with the antenna.

3) Entire DUT The entire DUT is the integrated system consisting of the SIW antenna and the PA. The separate components are going to be interfaced using the feed line of the antenna, which is a grounded coplanar waveguide (GCPW) line, as visible on Figure 4-2. Co-design based on full-wave/circuit simulations is being performed for both developed power amplifiers to fully exploit the potential of the separate components and optimize the performance of the complete system. Specifically, the termination provided by the antenna strongly affects the PAE (Power-Added Efficiency) and gain of the amplifier. The targeted KPIs for the PoC are summarized in Table 4-2 and will be assessed by performing the tests described in Sections 4.3.2 through 4.3.4

Figure 4-3. CMOS power amplifier.

Figure 4-4. Lumped components amplifier.

4.3.2 Elementary test 1: Stand-alone antenna

The goal of this test is to assess the performance of the stand-alone SIW antenna. Sufficient bandwidth needs to be achieved to provide high data rate communication for the envisioned 5G mobile communication networks, as well as ample gain to overcome the severely pronounced losses at millimetre wave frequencies. As energy efficiency is of prime interest, this test will also determine the radiation efficiency of the designed and fabricated antenna. Similar antenna designs for the Ka-band, which are summarized in Table 4-3, serve as a baseline for the assessment of the performance. The baseline SIW antennas in Table 4-3 are manufactured on relatively thick substrates, yielding high impedance bandwidths. As integration, footprint and size is an important KPI for this PoC, the developed SIW antenna is being manufactured on substrate material with a thickness of 250 µm, which reduces the maximum achievable bandwidth. Clearly, a trade-off has to be made, hence we aim for an impedance bandwidth of 1.5GHz for the proposed SIW antenna. The gain of the stand-alone antenna is expected to be about 4 dBi.



Table 4-3. Baseline for SIW antenna performance. Description Freq.

[GHz] BW [GHz]

Gain [dBi]

Configuration Area [mm2]

Substr. Reference

SIW 4x4 array

33 2.34 19 Array 138x99 0.5 mm [Liu09]

SIW horn with dielectric loading

21 3.6 7 Stand-alone 8x7.5 1.8 mm [Tan14]

4.3.2.1 Testbench setup specification

Figure 4-5 depicts the test bench that will be used to assess the performance of the stand-alone antenna. Both the antenna and a Standard Gain Horn will be connected to a Keysight PNA-X inside an anechoic chamber to measure the wireless link. The horn is mounted on a positioning system, which will allow measuring the link for different azimuth and elevation angles. The results of this test bench will be the passive gain in all directions and the reflection coefficient of the SIW antenna. From these results, the radiation efficiency can be calculated as well.

Figure 4-5. Test bench for stand-alone antenna.


After all preconditions are met, the wireless link between the DUT (designed SIW antenna) and the Standard Gain Horn is measured for two different polarization angles.

Objective Measure the bandwidth, gain and radiation efficiency of the designed SIW antenna

Interfaces Keysight PNA-X, Standard gain horn

Preconditions Calibration of PNA-X, align DUT with Standard Gain Horn and measure distance

Priority High

Responsible partners iMinds



Step 1 In this first step, the horn is aligned with the DUT and the performance under co-polarization can be assessed, meaning that the horn and the DUT are both vertically polarized. The S-parameters are captured by the PNA-X and the impedance bandwidth can be extracted from the reflection coefficient of the DUT. Based on the captured S-parameters, the software on the PNA-X computes the gain and directivity of the DUT. As the distance between the DUT and the horn antenna has been measured as a precondition, the path loss can be taken into account. Based on the difference between gain and directivity, the radiation efficiency of the DUT can be calculated. The value for the passive gain of the designed SIW antenna will also enable one to calculate the transducer gain of the power amplifier from the measurements performed on the integrated system of PA and antenna, as described in Section 4.3.3. Step 2 In the second step the horn is rotated over 90° to assess the wireless link under cross-polarization, meaning that the horn is horizontally polarized while the DUT is vertically polarized. An antenna is never purely polarized in a single mode (pure horizontal or pure vertical), hence the assessment of the cross-polarization is used to determine how “pure” the vertical polarization of the designed antenna really is. The cross-polarization is usually defined as a negative power level, indicating how many dB the cross-polarization level is below the desired polarization level. The power level of the cross-polarization is also a measure for efficiency and losses in the antenna, as the power that is used to excite the cross-polarized modes is essentially lost. 4.3.3 Elementary test 2: Stand-alone PA

The goal of this test is to assess the performance of the stand-alone power amplifier. To compensate for the elevated losses at mmWave frequencies, the signal has to be sufficiently amplified by the PA before being delivered to the antenna. Moreover, as minimizing the energy consumption is of prime importance for integrated systems, the efficiency of the amplifier will be determined as well. For the off-the-self lumped components PA, designed by CTTC, the expected performance is based on a baseline 18GHz amplifier performance using the Triquint 2023-2-01 device (as stated in datasheet) and are summarized in Table 4-4. Table 4-4. Baseline 18GHz amplifier performance using the Triquint 2023-2—01 device

[Qor16] Parameter Value Frequency 18GHz

Drain voltage 28 V

Bias current 62.5 mA

Input Power 31 dBm

Output Power 36.7 dBm

PAE 42.4 %

Power gain 5.7 dB



For the CMOS PA, developed at KUL, the expected performance is based on simulation results and compared to the state of the art in Table 4-5.

Table 4-5. Baseline for CMOS PA Simulations [Kay15] [Aga13] Frequency (GHz) 28 72 42

Technology 28 nm CMOS 40 nm CMOS 45 nm CMOS SOI

Supply (V) 1 1.5 2.5/1.2

PSAT (dBm) 22 21 18

PAE max (%) 23 13.6 20

Gain 23 5


The test bench that will be used to characterize the designed stand-alone PA is presented in Figure 4-6. The PA will be driven by a signal generator and a power sensor will register the output power of the PA. An attenuator is placed in between the PA and the power sensor to avoid damage/overload. The results of this test bench will be the output power (OP1dB), power gain and energy efficiency of the power amplifier.

Figure 4-6. Test bench for stand-alone PA.


The DUT (designed power amplifier) is fed and biased by a DC source and amplifies the input signal coming from the signal generator. A sweep is performed on the power level of the input signal to determine the 1dB compression point. At some input power level, the gain response of the amplifier will be compressed, i.e. reduced by 1 dB in this case. The result of this test (OP1dB) is the output power level that corresponds with this 1dB compression point

Objective Measure the maximum output power, power gain and energy efficiency of the designed power amplifier

Interfaces Signal generator, power sensor and meter, DC source

Priority High Responsible partners KUL / CTTC



and the power gain of the amplifier. By monitoring the amount of power that is drawn from the DC source, the energy efficiency of the amplifier can be determined. 4.3.4 Elementary test 3: Integrated antenna and PA

The goal of this test is to assess the performance of the integrated antenna and PA. As co-design based on full-wave/circuit simulations will be used, the performance of the integrated system will be optimal in terms of energy efficiency, gain and bandwidth. 4.3.4.1 Testbench setup specification

Figure 4-7 depicts the test bench for the active SIW antenna, i.e. the integrated antenna and PA. Both the active antenna and a standard gain horn will be placed inside an anechoic chamber to set up a wireless link. The active antenna is driven by a signal generator and a power sensor registers the power received by the standard gain horn antenna. Again, the horn antenna is mounted on a positioning system, which allows measuring the total active gain for both co- and cross-polarization. As the passive gain of the antenna is known from test bench 1, the transducer gain of the amplifier can be extracted.

Figure 4-7. Test bench for integrated PA and antenna


The DUT (integrated antenna and PA) is fed and biased by a DC source and amplifies the input signal coming from the signal generator before it is radiated via the integrated antenna. A sweep is performed on the power level of the input signal to determine the 1dB compression point. The power radiated by the integrated PA-antenna system is captured by the Standard Gain Horn. As the distance between DUT and horn antenna is known, the path loss can be compensated for, yielding the total radiated output power. Again, the 1 dB

Objective Measure the maximum output power, transducer gain and energy efficiency of the PA-antenna integrated system

Interfaces Signal generator, power sensor and meter, DC source

Preconditions Calibration of PNA-X, align DUT with Standard Gain Horn and measure distance

Priority High

Responsible partners KUL / CTTC + iMinds



compression point is determined, as already described in section 4.3.3.2. As the passive gain of the antenna is already determined (Section 4.3.2), the transducer gain of the amplifier can be determined. By monitoring the amount of power that is drawn from the DC source, the energy efficiency of the integrated PA-antenna system can be determined. Similar as in Section 4.3.2, the measurement is performed both for co- and cross-polarization. 4.3.5 Test results

Table 4-6. Test results Requirements Expected results Observed results Comments

Stand-alone antenna Bandwidth 1.5GHz -10 dB impedance

bandwidth

Gain 4 dBi

Radiation efficiency 60 %

Stand-alone PA (lumped components) PAE 40 %

Power gain 5 dB

Psat 36 dBm

Stand-alone PA (CMOS) PAE max. 23 %

Power gain 23 dB

Psat 22 dBm

Integrated antenna and PA (lumped components) Psat 36 dBm

Transducer gain 9 dB Calculated from PA and antenna simulations

Energy efficiency 28 % From load-pull and antenna simulations

Bandwidth 1.5GHz

Integrated antenna and PA (CMOS) Psat 22 dBm

Transducer gain 27 dB Calculated from PA and antenna simulations

Energy efficiency 18 % From load-pull and antenna simulations

Bandwidth 1.5GHz




The introduction of the Massive Internet of Things paradigm requires the deployment of large numbers of wireless devices (NoU) that provide communication, sensing and/or localization functionality while being unobtrusively integrated into the environment (ISF). To successfully implement such a scenario, in particular in a Smart Cities setting, these devices, must be low-cost, for commercial reasons, suited to unobtrusive/invisible integration into their environment, for aesthetical reasons, reliable, for security reasons, autonomous, for practical reasons, and recyclable, for ecological reasons. Although most electronic components have continuously decreased in size, the antenna dimensions must remain in the order of the wavelength to yield good radiation efficiency. In combination with the need for larger bandwidths (BW), enabling performance gadgets, this leads to an increase in operating frequency, corresponding to a smaller bandwidth, hence yielding smaller antennas with larger absolute bandwidths (BW), higher user data rate (UDR) and more connected users (NoU). An important challenge that must be tackled to develop energy-efficient devices operating in the 17-30GHz range is the interconnection between the antenna and the transceiver’s active electronic circuits. Indeed, a long lossy connection at these frequencies will incur losses and signal integrity issues that significantly affect the overall performance of the wireless device. Therefore the aim of this PoC consists in developing an active antenna system consisting of a low-cost planar antenna and a high-performance power amplifier. The full-wave/circuit co-design of this active antenna will prove the benefits in terms of bandwidth and energy efficiency compared to a simple concatenation of a stand-alone antenna and a stand-alone power amplifier (NRG) Also for the use case of Connected vehicles (part: V2X communications for enhanced driving), the mmWave operation of the active antenna provides the benefit of high bandwidth (BW) which is required to support the large date rates (UDR). Due to the co-design losses at the interconnection can be minimized and suboptimal operation of individual components avoided, resulting in energy efficient operation. 4.5 Additional considerations

In the first phase all partners are developing their components individually. iMinds is responsible for the antenna part, whereas KUL and CTTC focus on the PA design. The individual components are designed to be matched to a characteristic impedance of 50 Ω at the input/output. Phase 1 - Key challenges:

- Uncertainty of operation frequency of amplifiers: o KUL: around 28GHz o CTTC: Initially the 17.7GHz to 19.7GHz is considered (final frequency band

selection subject to device limitations). o iMinds needs to adjust the operation frequency of the antennas to match that

of the amplifiers. - Tolerances and packaging:

o KUL PA is going to be packaged in flip chip package. Packaging may influence performance.

o CTTC PA: influences of parasitic effects at frequencies > 17GHz - Tape out timing

Phase two will evaluate the overall performance when connecting the PAs to the antenna. Phase 2- Key challenges:

- Evaluation of interconnection influence on component performance



In the final phase the results of phase one will be used to improve the design. A co-design relying on full-wave/circuit co-optimization will combine the antenna and the active circuit. The antenna and PA will be fine-tuned in order to improve the overall performance. Phase 3 - Key challenges:

- Realization of interface - Agree on impedances at interface

4.6 Time plan and availability

The following table summarizes all intermediate and final milestones scheduled for PoC 2 in accordance with general Flex5Gware milestones.

Table 4-7. PoC 2 time plan. Component /Task

M6 M12 M16 M18 M21 M23 M24

Phase 1: Stand-alone components Low-profile SIW antenna

Definition Design Realization and evaluation

- - - -

28nm CMOS PA (KUL)


- - - -

PA with off-the-shelf components (CTTC)


- - - -

Phase 2: System of individual components CMOS PA flip-chipped to antenna substrate

- - - Realization and evaluation

- - -

PA with off-the-shelf components interconnected with SIW antenna

- - - Realization and evaluation

- - -

Phase 3: Co-design Co-design of SIW antenna and PA

- - - - Design Realization and evaluation

Final demo



5. PAPR reduction and power amplifier predistortion (PoC 3) The multicarrier techniques became the most important technology in the current communication system because it achieves high data transmission and is robust to the frequency selective fading channel [Zou95]. However, the major drawback of this technology is high Peak-to-Average Power Ratio (PAPR) and this drawback causes signal distortion and high energy consumption [Cos99]. It is essential that a transmitter has a power amplifier which provides a suitable power for transmission. The power amplifier is very sensitive to operational area which requires a linear behaviour. High PAPR requires operating the power amplifier at a lower average output power to avoid increased signal distortion due to nonlinear operation. This leads to a lower power efficiency of the power amplifier. In 5G systems, a new waveform is investigated. For example, Filter Bank Multi-Carrier (FBMC), Faster-than-Nyquist(FTN), Non-orthogonal asynchronous waveforms, Generalized Frequency Division Multiplexing, and Universal Filtered Multi-carrier. These are promising techniques to become the radio waveform in forthcoming 5G. However, they still suffer from high PAPR by being a multi-carrier technique. Therefore, new waveforms for 5G systems need a new PAPR reduction technique. In addition, Digital Pre-distortion (DPD) techniques are used to compensate for the non-linear behaviour of the power amplifier. They apply inverse distortion to the input signal of the power amplifier in order to compensate the distortion generated by the power amplifier. DPD algorithms must typically be applied at a sample rate reaching at least 3 or 5 times the baseband signal bandwidth. In 5G systems, we anticipate ultra-wide bandwidth due to very high data rate. Thus, one of key research challenge in 5G is to design high speed DPD algorithms. The goal of this PoC is to investigate a new PAPR reduction technique and DPD technique and evaluate the performance together with partners. 5.1 Short description

In PoC 3, a new PAPR reduction technique and power amplifier predistortion technique for 5G is developed and its performance improvement is demonstrated. In PoC 3, performance of a PAPR reduction technique and digital predistortion technique for 5G power amplifier (PA) is being studied by measurements. Characterisation of integrated PAs is provided in the context of minimizing the cost of the overall solution (e.g., discussing if it is better to have a single large band PA even if it requires harsher DPD or PAPR techniques compared to multiple single band PA). The VTT 5G SDR platform enables to easily begin software based simulations and measurements with real analogue hardware components and then to incrementally migrate from software to hardware implementations of the signal processing algorithms. A new PAPR reduction and a digital predistortion unit is being implemented on the VTT 5G SDR platform. The performance of the predistortion is being studied with and without the PAPR reduction. The complexity and needed FPGA resources of the methods are being evaluated and optimised. For example, the trade-off between the numerical precision in the FPGA implementation and the performance of the methods as well as their optimisation studies are needed for energy efficiency considerations. Energy consumption trade-offs between computing (i.e. the signal processing of the methods) and communication (i.e. the energy consumption of the power amplifier) are considered. IAF develops and provides the amplifier for the measurements. CTTC provides a detailed model of a second power amplifier which will be used to generate realistic performance data. Thus, both power amplifiers are included in the VTT 5G SDR platform and the performance of a PAPR reduction technique and DPD technique will be measured. The development of



the power amplifiers is being done in WP2. Design and implementation of the PAPR reduction and predistortion methods as well as the energy consumption trade-off considerations is being done in WP3. VTT 5G SDR platform is based on ETTUS X310 Software-Defined-Radio platforms as shown in Figure 5-1 and Figure 5-2. We can use both real-time and modifiable LTE based PHY, or custom waveform (generated by Matlab, GnuRadio or LabVIEW). It supports the following use-scenarios: (1) Measurements of the performance improvements of pre-distortion or PAPR-reduction techniques, (2) possibility to connect with an external power amplifier and (3) possibility to use Analog/RF feedback after PA.

Figure 5-1. ETTUS X310 and B200 SDR devices in VTT 5G Lab.

Figure 5-2. User Interface (Real-time LTE-based system).


Table 5-1. summarizes the devices/interfaces and roles of each partners for PoC 3.



Table 5-1. PoC 3 partner roles. Partner Devices Interfaces Role VTT VTT 5G SDR

Platform SMA connector inside VTT 5G SDR Platform

PoC responsible, Development of PAPR reduction and power amplifier predistortion technique.

F-IAF GaN HEMT HPA module

SMA connector (50Ω RF interface)

Provides GaN HEMT HPA of WP2

CTTC Power amplifier

SMA connector (50Ω RF interface)

Provides PA model of WP2

SEQ - - Contributor (envelop tracking feasibility for UE standpoint)


𝑃𝐴𝑃𝑅 = max0≤𝑛≤𝑁

|𝑥𝑛|2

𝐸(|𝑥𝑛|2)

Pr(𝑃𝐴𝑃𝑅 > 𝑌) = 1− (1− 𝑒−𝑌)𝑁 𝑌 > 0

Pr(𝑃𝐴𝑃𝑅 > 𝑌) = 1− (1− 𝑒−𝑌)2.8 𝑁 𝑌 > 0

Pr(𝑃𝐴𝑃𝑅 > 𝑌) = (1− (1− 𝑒−𝑌)𝑁 )𝑈 𝑌 > 0 The KPIs considered for the PoC are listed below with the supported use cases

Table 5-2. PoC 3 KPI table. KPI Related Use Case(s) Comment

NRG 50+ Mbps everywhere, Smart cities and Performance equipment

Typical PAPR of 4G LTE is 7~8 dB. The values depend on IFFT/FFT size, modulation schemes, etc.


Figure 5-3. PoC 3 ToL Testbench.



The VTT 5G development platform will be used for PoC 3 demonstration. The platform is composed of the following parts:

- Hardware Modules : ETTUS X310 SDR Platform including FPGA and ETTUS SBX-120 RF Cards including power amplifier (PA)

- Power amplifier : Conventional PA, GaN HEMT HPA (by F-IAF) and PA (by CTTC) - Interface with other devices : SMA-connectors for RF signal (0.4GHz – 4.4GHz)

Amplitude max ~ 0 dBm (To be defined) - Host PC : Offline processing by Matlab - User Interface: Support signal constellation, BER performance, Waveform, Data

formats, etc. - Channel emulator - Spectrum analyzer

5.3.2 Elementary test 1: PAPR performance 5.3.2.1 Testbench setup specification

The developed algorithms will be demonstrated on VTT 5G SDR platform. The VTT 5G SDR platform includes a pair of Ettus Research USRP X310 SDR platforms with wideband RF daughter boards. USRP X310 has multiple high-speed interfaces, flexible clocking architecture and large user-programmable Xilinx Kintex 7 FPGA for transceiver implementation. VTT 5G SDR platform utilises LTE Framework from National Instruments. A real-time, modifiable LTE PHY downlink is running partly on FPGA’s, partly on Host-PC. The developed PAPR reduction algorithm and DPD algorithm can be implemented by Matlab or FPGA.


In the PoC 3 demonstration, it is being implemented PAPR reduction and DPD techniques and evaluated their energy efficiency improvements. As 5G waveform, OFDM or FBMC waveform is being used in the platform. F-IAF and CTTC provide their PA and the energy efficiency of PA will be test as PAPR value. The implementation scenario is (1) Waveform generation (OFDM, FBMC, etc.), (2) PAPR reduction implementation by Matlab (Offline processing) and DPD technique implementation by FPGA (Real-time signal processing), (3) Connection to external power amplifier (PA) (Conventional PA, GaN HEMT HPA, etc.), (4) Emulated ratio channel and device under test/measurement, (5) Received signal measurement. The performance and complexity of the PAPR reduction and DPD technique is being investigated with and without both techniques. The energy efficiency will be evaluated by enhancing PAPR values. 5.3.3 Test results

The expected results are PAPR values which are measured by user interface of VTT 5G platform or spectrum analyzer. The comparison will be main result when including PAPR

Objective Measure PAPR values of OFDM/FBMC signals with/without PAPR/DPD technique.

Interfaces SMA-connectors (50Ω RF interface) for RF signal Priority High

Responsible partners VTT,



reduction/DPD technique or not. Those comparisons will be carried out using conventional PA and a new PA developed by F-IAF and CTTC.

Table 5-3. PoC 3 test results.

Requirements Expected Results Observed Results Comments

PAPR reduction technique

- - Conventional PA

DPD technique - - Conventional PA

PAPR reduction technique + DPD technique

Typical PAPR value is 7 - 8 dB in 4G. However, this value vary depending on system configuration

- Conventional PA


- - GaN HEMT HPA module by F-IAF

DPD technique - - GaN HEMT HPA module by F-IAF



- GaN HEMT HPA module by F-IAF


- - PA module by CTTC

DPD technique - - PA module by CTTC



- PA module by CTTC


The PoC 3 is mapped with the following use cases: 50+ Mbps everywhere, Smart cities and Performance equipment. These use cases require energy efficiency improvement. The energy efficiency is very important metric in 5G communication and networks. About 3% of the world-wide energy is consumed by the information and communication infrastructures and their power consumption is rising at 15~20% every year. In [Edl08], authors mentioned that base stations in the 3rd generation (3G) mobile network spend 57%, mobile switching systems spend 20%, core transmission parts are responsible to 15% of expenditure and data centre consumes 6%. Thus, a base station is the most energy consuming part of a mobile network. In addition, the energy efficiency of a base station is very low. For example, a traditional base station uses only 4% of the consumed power for transmission [Con12]. About 50 ~ 80 % power of a base station is consumed in power amplifier [Con12]. Thus, PAPR reduction technique and DPD technique enhance the power amplifier efficiency. The PoC 3 is expected to be able to improve energy efficiency of 5G systems.



5.5 Additional considerations

No additional considerations. 5.6 Time plan and availability

The below table shows the plan of the work for PoC 3 in WP6 activities. Table 5-4. PoC 3 time plan.

Component/Task M6 M12 M18 M24

Algorithm development (PAPR reduction technique

and DPD technique)

Preliminary definition

Ready to implement - -

Algorithm implementation - Preliminary

Specification, Implementation

defined

Initial evaluations -

PA module Preliminary specification First prototype

Final prototype and

specification -

PoC setup Preliminary definition

Final definition of PoC setup and

evaluation methodology

Ready to integrate

(GaN HEMT HPA module (F-IAF)/PA (CTTC))

Integration, algorithm

implementation, performance evaluation

PoC demonstration - - - Demo setup.

In the first stage, each partner is developing their component individually. VTT is responsible for a whole test procedure and PAPR reduction/DPD technique development. F-IAF and CTTC focus on the PA design and SEQ focuses on the envelope tracking techniques. From M12 to M18, PAPR reduction/DPD techniques will be evaluated in VTT 5G testbed. From M18 to M24, the integrated evaluation including the PAs of F-IAF and CTTC will be carried out.

Algorithm Ready

Implementation Stage 2

(Integrated evaluation)



6. Multiband transmitter (PoC 4) Base stations supporting concurrent operation of different radio bands are required to increase the operating bandwidth as requested for 5G mobile systems. To deploy areas of different sizes and to assure mobile communication under challenging topographical and environmental conditions, the operation at frequencies below 6GHz is mandatory. At these frequencies, many radio bands are defined for mobile communication with bandwidth mostly below 100MHz. The bandwidths available for single operators are restricted to few tens of MHz per radio band and request for inter-band carrier aggregation, to support the envisaged increase on data rate. As a straight forward approach, base stations operating in different radio bands have several transceivers integrated, which support the operation in single radio bands. This leads to high hardware complexity, due to the number of included transceivers dedicated to single radio bands and duplicated for multiple antenna operation (antenna diversity or MIMO). Multiband transceiver solutions exploit broadband and multiband capabilities of components to realize transceiver chains, which support concurrent operation in multiple radio bands. This allows reducing the hardware complexity by decreasing the number of implemented transceivers. For proving the feasibility of the proposed multiband transceiver concept, a test setup of a multiband transmitter is realized and evaluated, which supports concurrent operation of multiple signal carriers positioned in three different radio bands at frequencies around 2.6, 2.8 and 3.5GHz. 6.1 Short description

Multiband transmitters supporting carrier aggregation in radio bands below 6GHz are considered for validation with the focus on multiband RF signal generation and amplification. The setup contains a multiband transmit-chain as a key block out of a versatile base station, which follows a modular concept with regard to supported radio frequency ranges. This means, multiple transmit-chains can be included in a base station supporting the same radio bands for multi-antenna operation or complementary bands to increase the supported aggregated bandwidth. The setup contains signal conditioning algorithms for multiple baseband signals, D/A conversion and RF signal generation, filtering and amplification. This transmit-chain covers different radio bands between 2.6 and 3.6GHz for concurrent multiband operation.

Figure 6-1. Block diagram of a multiband transmitter test setup.

The setup allows for proving the feasibility of multiband transmitters (TX) with a significantly increased operation bandwidth compared to state-of-the-art and addresses a radio frequency range for mobile communication which is beyond state-of-the-art. It demonstrates solutions

FB

FPGA (MB-TX)

DAC Filter

Filter

PC(Matlab)

Spectrum-analyzer

ADC

PA

MultibandRF signal generation

Multibandamplification

Low power multiband transmitter



for network equipment supporting LTE-Advanced CA (Carrier Aggregation) with carriers placed in different radio bands and expected similar operation within 5G wireless networks. 6.2 Partners and roles

The following table summarizes the devices/interfaces and roles of each partner inside this PoC.

Table 6-1. PoC 4 partner roles. Partner Devices Interfaces Role ALUD Low power multiband

transmitter Frequency bands, power ranges and signal quality at the 50Ω interface

PoC Leader; HW provider; Performance evaluation of the multiband transmit-chain

F-IAF Multiband PA module Frequency bands, power ranges and signal quality at the 50Ω interface

HW provider; Evaluation of multiband PA module


The test setup shown in Figure 6-1 allows evaluating the multiband performance of transmitters in base station transceivers dedicated to high aggregated operating bandwidth in radio bands below 6GHz. The main KPI is the supported radio bandwidth and the aggregated operation bandwidth, which assure an increased throughput in radio bands below 6GHz and thus for inter cell distances of different sizes, respectively in areas of different user densities, including low density regions. The flexibility is given by a reconfiguration of the operation bandwidth and carrier position within a given frequency range.

Table 6-2. PoC 4 KPI table. KPI Related Use Case(s) Comments FVR Crowded Venues

Dynamic hotspots 50+ Mbps everywhere Broadband in vehicles

- re-configuration time of a few seconds expected. - Multiband capability (e.g., 6x20 MHz carriers) - transparent to different RATs

MDV Crowded Venues Dynamic hotspots 50+ Mbps everywhere Broadband in vehicles

To be derived from BW by considering a power level of < 38 dBm / 20 MHz carrier at the frequencies 2.5 to 3.6GHz.

BW Crowded Venues Dynamic hotspots 50+ Mbps everywhere

Up to 120 MHz to be demonstrated as 6 x 20 MHz inter-band CA (considers the operation in three radio bands) targeted.




The device to be tested is a multiband transmitter for base stations with forward path (MB TX FW) and the feedback path (MB TX FB) realized as single signal paths in the analogue front end (Figure 6-2) supporting multiple carriers in multiple radio bands. This is achieved by integrating broadband and multiband components supporting the radio bands of interest. The envisaged three bands are around 2.6, 2.8 and 3.5GHz and are operated with 6x20 MHz carriers distributed over the three bands, providing in concurrent multiband operation a total aggregated operating bandwidth of 120MHz. The multiband high power amplifier is defined to provide close to +38 dBm average output power per 20 MHz carrier, corresponding to medium range base station operation. Following main components are integrated. The DSP (digital signal processor) includes signal conditioning, digital pre-distortion (DPD) and data interfaces to the data converters. The DSP functions are partly implemented in a FPGA and partly in Matlab. The RF-DAC (radio frequency digital to analogue converter) of the forward path receives the three base band signals (A, B, C) dedicated to the three radio bands and provides the RF signal of the 6x20 MHz carriers positioned in the three radio bands. The LPF/BPF (low pass / band pass filter) suppresses unwanted signals from not used Nyquist zones. The Driver provides the required power level at the MB-HPA input. The MB-HPA (multiband high power amplifier) provides the required power level at the transmitter output and the same signal at lower power level for the feedback path. The IQ-demodulator provides I and Q base band signals to the ADCs. A radio band hopping allows a successive down conversion of the signals in each radio band correlated with a successive utilization by the DPD. The ADCs (analogue to digital converters) receive the analogue base band signals and provides digital signals to the DSP.

Figure 6-2. Block diagram of a multiband transmitter (DUT).



6.3.2 Elementary test 1: operating bandwidth 6.3.2.1 Testbench setup specification

The test is elaborated using the setup shown in Figure 6-3. The Matlab interface is used to configure the DUT. The signal power is measured with a power meter, while the signal quality is analyzed with a spectrum analyzer.

Figure 6-3. Block diagram of the test setup.


The operating bandwidth is to be proved by analyzing the aggregated bandwidth with carriers positioned in three different bands around 2.6, 2.8 and 3.5GHz. A total bandwidth of 120 MHz is targeted by positioning two carriers in each of the three bands. The total output power is measured with a power meter. Maximum average power in the range of 40 to 44 dBm is expected. The signal power of each carrier is evaluated based on the total power and on the signal power level of each carrier measured with the spectrum analyzer. The compliance with the spectrum emission mask (SEM) is evaluated with the spectrum analyzer by analyzing the ACLR values for each carrier with the target of < -45 dBc. 6.3.3 Elementary test 2: flexibility, frequency agility 6.3.3.1 Testbench setup specification

The flexibility evaluation is done with the same setup as shown in Figure 6-3.


The flexibility of the implemented hardware addresses the frequency agility of the setup and comprises the reconfiguration of carrier positions within the frequency ranges 2.57- 2.9GHz

Objective Test of aggregated operating bandwidth

Interfaces Computer, DC source, power meter, spectrum analyser

Priority High

Responsible partners ALUD

Objective Test of different carrier aggregation schemes Interfaces Computer, DC source, power meter, spectrum analyser

Priority High




and 3.4-3-6GHz. Different carrier aggregation (CA) schemes are considered for up to 6 carriers of 20 MHz and up to 3 radio bands. A basic configuration of carrier positions considers two carriers of 20 MHz in each of the three radio bands. The frequency agility of the multiband transmitter is tested by altering the radio frequency of the carriers, the carrier bandwidth, and the number of carriers and by evaluating the signal quality for these different configurations. 6.3.4 Test results

The state-of-the-art of multiband transceivers are solutions with support, in a single transmit chain, one or more signal carriers positioned in a single radio band only. In order to operate more radio bands, the number of transmit chains is duplicated by the number of supported radio bands. The operation of a transmit chain with signal carriers positioned in more than one radio band for supporting inter-band carrier aggregation, provides a significant improvement on hardware integration. Test 1 The supported operating bandwidth is evaluated with signal carriers positioned in three radio bands for maximum aggregated bandwidth. The signal quality will be assessed and the results will be presented in Table 6-3.

Table 6-3. PoC 4 test 1 results. Requirements Expected results Observed results Comment Aggregated bandwidth 120 MHz - -

Number of radio bands 3 - -

Max. average output power ~ 40–44 dBm - -

ACLR < -45 dBc - -

Test 2 The frequency agility of multiband transmitters is demonstrated by testing different positions of signal carriers in different radio bands accordingly to the example included in Table 6-4. The applied concepts allow to reconfigure the transceiver within a few seconds.

Table 6-4. PoC 4 test 2 results. Radio band / Nr.

of carriers Radio band / Nr.

of carriers Radio band / Nr.

of carriers CA scheme A (example of planned carrier distribution)

2.6GHz / 2 x 20MHz

(2.62-2.66GHz)

2.8GHz / 2 x 20MHz

(2.84-2.88GHz)

3.5GHz / 2 x 20MHz

(3.46-3.5GHz)

CA scheme B (example of planned carrier distribution)

2.6GHz / 2 x 20MHz

(2.65-2.69GHz)

- 3.5GHz / 2 x 20MHz

(3.5-3.54GHz)




The setup contains key building blocks of versatile base stations with high operation bandwidth of multiband transceivers supporting concurrent transmission of multiple carriers (e.g. up to 6 x 20 MHz) allocated to multiple radio bands (e.g. 3). The power level of the implemented transmit-chain is suitable for medium or large inter-side distances. An increase of radio bandwidth is also achieved due to the supported multiple bands. On concept level, the versatility is given by its potential application for different frequency ranges below 6GHz. Furthermore, it allows combining such transmit-chains for different frequency ranges in a modular way, for increasing the operation and radio bandwidth further, with the corresponding increase of cell capacity. The ability of moving the frequencies of operated carriers within the radio bands and between them by re-configuring the transceiver gives certain flexibility as frequency agility on a degree defined by the implementation complexity. The multiband transmit-chain supports significantly the use cases 50+ Mbps everywhere and Mobile broadband in vehicles as it assures an increased data rate due to the increased bandwidth applicable even for larger cells and due to the concurrent operation in several radio bands below 6GHz. If applied for smaller cells, the concept can support also the use cases Crowded venues and Dynamic hotspots by providing increased data rate to the users. 6.5 Additional considerations


The definition of the proof of concept stays at the beginning of the work and is adapted to the main building blocks, the multiband RF signal generation and the MB-HPA. After an analysis of the components considered for implementation, the whole setup is defined. A first phase of implementation is focusing on the multiband low power transmitter and the MB-HPA individually, followed by the complete integration of the PoC setup. The evaluation and demonstration of the multiband transmitter completes the work. A time schedule for the whole proof of concept is given in Table 6-5.

Table 6-5. PoC 4 time plan. Component/Task M6 M12 M18 M24 Multiband low power transmitter

Preliminary definition/ specification

Specification; implementation defined

Setup for MB signal generation

-

Multiband PA module Preliminary definition/ specification

Specification, first design

Prototype -

PoC setup Preliminary definition/ specification

Final definition of PoC setup and evaluation methodology

- Integration, algorithm implementation, performance evaluation

PoC demonstration - - - Demo setup.



7. Full duplex FBMC (Filter Bank Based MultiCarrier) transceiver (PoC 5) CEA and IMC are investigating the usage of full-duplex (FD) operation of the hardware in consideration from a 5G perspective. More precisely, the proposed approach is to build a demonstrator derived from MIMO transceivers and look at extending capabilities for In Band Full-Duplex (IBFD) operation. The proof of concept should demonstrate the practical feasibility of full duplex with possible new 5G waveforms taking FBMC as a particular option for FD operation. One particular scenario has been taken into account to investigate the benefits IBFD would provide in comparison to standard duplexing operation (TDD or FDD). This scenario has been defined in [San14] and thoroughly described in [Fle31]. It considers IBFD operation only at the base station where TDD operation can be scheduled to be either in TDD uplink, in TDD downlink or in FD mode (Figure 7-1).

Figure 7-1. Interference generated in half duplex and full-duplex for scenario of

[San14]. The proposed scenario allows for increase of capacity of the cell since one resource block is used at the same time for uplink and downlink, without stringent power consumption requirements on the user equipment side (since in the chosen scenario no process is added to the user equipment for IBFD operation, degradation of the link is controlled by the scheduler of the base station). 7.1 Short description

The development of a dedicated hardware platform is considered for the full-duplex demonstration. A digital baseband platform is to be developed and interfaced with RF evaluation boards from ARRadio (AD9361 Software defined RF component) followed by a dedicated LETI full duplex adaptation board (analog cancellers, couplers, baseband filtering and cancellers). Preliminary schematic of the dedicated demonstration card and the associated ARRadio RF card can be found in Figure 7-2. The demonstration card will include both

- digital interfacing to standalone AD9361 evaluation boards (ARRadio cards) by means of a HSMC connector

- analog interfaces using SMA and/or QSE-20 connectors. Analog interface is implemented through multiple alternatives, i.e. differential /single ended options. This is to provide alternative architectures for the full duplex daughterboard card.



Figure 7-2. Planned demonstrator hardware – Digital Baseband board and ARRadio

(AD9361) component. Effort is being put on the design of an RF full duplex board that interfaces with the output of the ARRadio board. Provision for an integrated daughterboard (including AD9361 and FD RF elements) may then be considered. 7.2 Partners and roles


Table 7-1. PoC 5 partner roles. Partner Devices Interfaces Role CEA • Xilinx Zync

XCZ7045 digital platforms. • AD9361 ARRadio daughterboard • RF front-end canceller daughterboard

Conceive and provide platform Provide infrastructure for the demonstration platform Develop RF canceller daughterboard and integrate with digital and ARRadio platform

PoC Leader. HW provider. HW basic element integration SW provide elementary SIC demonstration

IMC • SIC algorithms for implementation

Provide advanced SIC algorithms adapted to the platform

SW provides advanced SIC cancellation technique


The following KPIs have been identified for the technology.



Table 7-2. PoC 5 KPI table.

KPI Related Use Case(s) Comment

UDR Crowded Venues Dynamic hotspot

At least 50 % average data rate increase compared to a TDD system is expected from the technology

FVR Dynamic hotspots Switching between half duplex and full duplex Switching central frequency for the data link

Performance of Full-Duplex operation is mainly dependent on the following parameters in terms of capacity:

• Level of linear and non linear Self Interference Cancellation (SIC) • Level of incoherent noise added by the SIC

When SIC is larger than 65dB and without added noise by the SIC, gain of full-duplex operation is substantial in comparison to half-duplex modes. A system level evaluation of the performance gain as a function of the Signal interference cancellation is given in [D3.1][San14].

Table 7-3. Average performance gain of full-duplex vs half-duplex as a function of interference cancellation level.

Performance of interference cancellation 55 dB 65 dB 75 dB 85 db Downlink 2.0 % 21 % 56 % 69 %

Uplink 0.4 % 4.9 % 33 % 81 %

Therefore signal interference cancellation is a key parameter to validate the KPI for IBFD operation. 7.3.1 Device under test (DUT) scheme

Figure 7-3. PoC 5 Devices under test.

Figure 7-3 presents the proposed architecture of IBFD approach considered in Flex5Gware for demonstration. The transmitted high power signal should be cancelled at the receiver as it



is using the same time/frequency resource as the received signal. Three main areas of cancellations are considered:

• RF signal interference cancellation (RFSIC): this is the level of signal that is expected to be cancelled just after the circulator in the receiver chain. This canceller is only analog.

• Hybrid signal interference cancellation (HSIC) this is the signal cancelled by the auxiliary transmission chain

• Digital signal interference cancellation (DSIC): this is the canceller that is implemented in the digital domain after digitizing the received signal with the remaining transmitted signal

The figure below represents preliminary observed results with HSIC and DSIC. RFSIC has not been implemented yet, but the corresponding arrow points towards the expected power at its output.

Figure 7-4. Illustration of expected interference cancellation along the receiver chain.

The PoC will demonstrate the following KPI Table 7-4. KPI relationship to PoC 5.

KPI description Relevance to the proof-of concept

Other comments

UDR UDR will be demonstrated in the PoC via the level of self interference cancellation, which is itself directly related with the attainable data rate.

We expect that final SIC will be higher than 65 dB.

7.3.2 Elementary test 1: RF SIC performance 7.3.2.1 Testbench setup specification

The goal of this test is to evaluate the performance of the first stage of the signal interference cancellation circuit and algorithms of PoC 5. Impact of the circulator on the RFSIC operation may also be evaluated.



OBJECTIVE Measure of performance of RFSIC

INTERFACES Analog input of the receiver connected to a measurement instrument of type FSW.

PRECONDITIONS (optional)

RFSIC circuit and control algorithm operational

Priority No particular priority for the test

Responsible partners CEA

Figure 7-5. Setup for elementary RFSIC measurement.

HSIC and DSIC are switched off. The objective of the test is to evaluate on real signal RF self interference cancellation (RFSIC) performance and RFSIC additive self-noise. 7.3.2.2 Test procedure description

Full-Duplex transceiver is started and connected to a controlled impedance antenna. A signal and spectrum analyser (type FSW) measures the received power after RFSIC at the input of the receiver. RFSIC output power is measured. HSIC and DSIC control algorithms are switched off to limit self-noise in the system. 7.3.3 Elementary test 2: HSIC performance measurement 7.3.3.1 Testbench setup specification

The goal of this test is to evaluate the performance of the second stage (hybrid signal interference canceller or HSIC) of the signal interference cancellation circuit and algorithms of PoC 5.

OBJECTIVE Measure of performance of HSIC



HSIC circuit and control algorithm operational





Figure 7-6. Setup for elementary HSIC measurement.


Full-Duplex transceiver is started and connected to a controlled impedance antenna. A signal and spectrum analyser (type FSW) measures the received power after HSIC at the input of the receiver. HSIC output power is measured. RFSIC and DSIC control algorithms are switched off to limit self-noise in the system. 7.3.4 Elementary test 3: DSIC performance measurement 7.3.4.1 Testbench setup specification

The goal of this test is to evaluate the performance of the last stage (digital signal interference canceller or DSIC) of the signal interference cancellation circuit and algorithms of PoC 5.

Figure 7-7. Setup for elementary DSIC measurement.



OBJECTIVE Measure of performance of DSIC

INTERFACES Digital interface at the receiver.


DSIC circuit and control algorithm operational. Post-treatment may be performed using Matlab.




Full-Duplex transceiver is started and connected to a controlled impedance antenna. Digital signal received after DSIC is stored and transferred to a PC for post-processing. Post-processing estimation is performed to evaluate amount of linear, non-linear and noise added by the DSIC implemented algorithms. 7.3.5 Elementary test 4: aggregated SIC performance measurement 7.3.5.1 Testbench setup specification

The goal of this test is to evaluate the performance of the three cancellation stages (RF, hybrid and digital signal interference canceller or RFSIC, HSIC, DSIC) of the signal interference cancellation circuit and algorithms of PoC 5.

OBJECTIVE Measure of performance of aggregated SIC performance



RFSIC,HSIC,DSIC circuit and control algorithm operational

Priority Elementary tests 1 to 3 operational


Figure 7-8. Setup for elementary HSIC measurement.




Full-Duplex transceiver is started and connected to a controlled impedance antenna. A signal and spectrum analyser (type FSW) measures the received power after HSIC at the input of the receiver. HSIC output power is measured. Digital signal received after DSIC is stored and transferred to a PC for post-processing. Post-processing estimation is performed to evaluate amount of linear, non-linear and noise added by the DSIC implemented algorithms. 7.3.6 Test results

As mentioned in section 7.3, the main KPI is the self-interference cancellation level. In [Bha13], the Stanford team reached an 110dB SIC level over 80MHz bandwidth at 2.4GHz. However, this result was obtained using a complex RF tap filter, which is an expensive solution. Our goal here is to reach an acceptable SIC, i.e. > 65 db (see Table 7-3), with a less complex solution. Indeed, we plan to reuse existing MIMO 2 antennas transmit architecture to perform the RF cancellation. In the above figures, one can see the ” Main RF Tx chain” and the ”Auxiliary RF Tx chain”, which are both Tx chains of the regular MIMO system. However, when used for Full Duplex SISO, only the Main Tx chain is connected to an antenna and transmits data over the air. The Auxiliary chain uses the RF components of the second RF MIMO chain, but is not connected to any antenna. It is only used to emulate the first RF MIMO chain in the self-interference cancellation. The following Table will be used for all elementary tests.

Table 7-5. PoC 5 test results. Requirements Expected Results Observed Results Comments SIC performance (resp. Aggregated SIC performance for elementary Test 4)

>65 dB - -

Achievable Bandwidth 20 MHz - -


PoC 5 has been considered for inclusion in the following scenarios of Broadband Access in Dense Areas and particularly for Crowded venues and Dynamic hotspots. A full duplex small cell could ideally double the bandwidth. With a real world constraint system and the scenario described in the introduction of the section, expected capacity is significantly increased when self-interference cancellation is larger than 65dB: in that case capacity is already increased on average by 50% [Fle31].

• Crowded venues: Full-Duplex is a particularly promising technology for small cell scenarios that require high capacity. This is the case of crowded venues. For a full duplex base station the higher the power difference between transmitted and received signals, the more complex and expensive the hardware interference canceller . Secondly, since Full-Duplex systems are expected to be more dependent on an accurate channel state information, scenarios where the channel environment is slowing varying may promise more gain in capacity.

• Dynamic hotspot: The proposed architecture enables a fast adaptation to a changing self interference environment. The system architecture enables switching the two transceiver chains between two modes of operation: a MIMO system or a full duplex system, depending on what is favourable in the current scenario. For example in a Line-of-Sight scenario, operating the system as a Full Duplex system clearly



offers a better performance than a MIMO system. However, in order to choose between a Full Duplex and a MIMO system, one has to take into account not only the channel condition but also the bandwidth. Indeed, the larger the bandwidth, the more difficult it is to compensate components non linearity’s. Although the PoC will not demonstrate the capability to switch between MIMO and full-duplex, the demonstrator will be based on MIMO transceiver architecture. The performance results of the PoC will give preliminary elements for the potential of the concept.

7.5 Additional consideration


The following table summarizes all components included in this PoC and the envisaged status of each one coinciding with Flex5Gware milestones.

Table 7-6. PoC 5 time plan. Component/ Task M6 M12 M18 M24

Demonstration platform

DEFINITION, Development of demonstration board

Development of software infrastructure for platform,

Preliminary Prototype available

Final demonstration

SIC Hardware Refinement of the architecture

Finalization of hardware SIC architecture, Refinement of FD architecture

Measurement of transceiver performance

Final report of transceiver performance



8. High-Speed Low Power LDPC Decoder (PoC 6) This PoC addresses the design of cost-effective Low Density Parity Check (LDPC) decoders, suitable for the new generation of communication systems, requiring increased data rates and reduced energy footprint. One important characteristic of LDPC decoders is that the memory and interconnect blocks dominate the overall area/delay/power performance of the hardware design. To address this issue, our approach is to integrate imprecision mechanisms for message computing and storage in LDPC decoders, which is seen as an enabler for cost-effective, high-throughput, and/or low-power decoder designs. This also requires designing novel impreciseness-resilient decoding algorithms and hardware architectures, able to provide reliable error protection, even though they rely on imprecise computing and storage units. This PoC will demonstrate the findings of the research conducted in WP4, through the implementation of a high-throughput low-power LDPC decoder. The main novelty comes from expansion of the design space, so as to harness the potential benefits of imprecise computing and storage in pursuit of the above goals. The expected benefits are to meet 5G requirements in terms of end-user data rates, while reducing power consumption at terminal node. 8.1 Short description

The objective of this PoC is to validate the proposed architecture(s) for a high-speed low power resilient LDPC decoder. As future 5G cellular networks will consider higher data throughput, notably thanks to usage of larger frequency bandwidth available in the mmWave spectrum, new high-speed forward error correction decoders will be required. Power consumption should however be constrained and the overall complexity should be contained in order to guarantee the commercial and technical viability of the new physical layers. The main outcome is to meet 5G requirements in terms of end-user data rates, while reducing power consumption at terminal node. The most promising impreciseness-resilient LDPC decoder architecture will be implemented on an FPGA target and evaluated in terms of throughput and power consumption. This will help to compare throughput and power estimates of the proposed design with SoTA.

• The proposed architecture is being implemented on an already available proprietary platform based around a Xilinx Kintex-7 FPGA (Figure 8-1) and compared with standard LDPC architectures. Encoder and decoder are located either on the same physical board or split across multiple physical platforms depending on the test requirements. Control and validation of operation of the LDPC decoder is being done via a personal computer interface, as depicted in Figure 8-2.

Figure 8-1. Proposed electronic card to be used for design validation



Figure 8-2. Proposed hardware for design validation

Proof-of-concept demonstration will be interfaced with a personal computer using the proposed hardware platform. The PoC will be completed by poster information to explain the results that have been derived during the course of the project for ASIC targets. 8.2 Partners and roles

The following table summarizes the devices/interfaces and roles. Table 8-1. PoC 6 partner roles.

Partner Devices Interfaces Role CEA FPGA based

demonstration board associated with PC interface

PC interface to drive the demonstrator

PoC responsible, Development of LDPC decoder and implementation on FPGA board


The following KPIs have been identified for the technology:

• Energy Consumption • User data rate Throughput

Table 8-2. PoC 6 KPI table. KPI Related Use Case(s) Comment NRG Dynamic Hotspots

Crowded Venues The goal is to provide an architecture that is highly optimized for power and energy consumption. Comparison with SoTA is to be performed if possible under similar design constraints. .



UDR Dynamic Hotspots Crowded Venues

The goal is to provide an architecture with high throughput of around 1 Gbps.

8.3.1 Device under Test (DUT) scheme

The device under test is the implementation of the LPDC decoder either on a FPGA Kintex-7 platform or on an ASIC target platform (typically CMOS C65). Demonstration will be only performed on FPGA platform.

Table 8-3. PoC 6 Devices under Test. Devices Usage FPGA demo platform FPGA based platform to validate FPGA architecture

CAD Tools Synthesis, Place and route tools for ASIC evaluation

Simulation Environment Evaluate power consumption of proposed design on targeted technologies (CMOS) at a maximum attainable frequency.

A brief description of the proposed design flow is here given in order to better understand the elementary tests that are being performed on the developed technology. The overall iterative design flow to evaluate and optimize the high speed LDPC decoder is shown in Figure 8-3. The technology developed during Flex5Gware and evaluated in the PoC 6 is based around a VHDL description of the High Speed LDPC decoder (core IP) and its comparison with a decoder (min-sum LDPC decoder) from the literature. The architecture is designed in VHDL and verified via simulations both before and after synthesis on ASIC using Design Compiler (a computer assisted design (CAD) tool used for ASIC development). Emulation in FPGA completes the validation flow. Reports are generated providing information about power consumption, area and maximum attainable frequency for a given target technology (expected technology CMOS C65). The reports obtained for architecture from SoTA provide the reference metric for design optimization using the CAD Tools. The most optimized LDPC decoder architecture in terms of power consumption and throughput is then synthesized and emulated on FPGA for extensive validation and constitutes PoC 6.

Figure 8-3. Iterative design flow considered for PoC 6



8.3.2 Elementary test 1: ASIC Synthesis Results

The first elementary test results that are of significant relevance to the designed LDPC decoder consists of the synthesis results of the designed core decoder. Once a complete and functional VHDL description of the decoder is finalized, preliminary synthesis will be performed on the design for 65 nm technology libraries. These results will be used to provide estimate of silicon area cost when the design is integrated into an ASIC. 8.3.2.1 Testbench setup specification

The goal of this test is to evaluate the silicon area cost. Selected LDPC Decoder first designed in VHDL, then VHDL is used as input of the scripts used by Design Compiler tool. These scripts are written for performing design synthesis using 65nm Technology libraries.

OBJECTIVE Estimation of silicon area cost of the designed LDPC decoder. Comparison with SoTA.

INTERFACES .


Synthesis of the designed LDPC decoder




Using the various scripts, Design Compiler analyzes, links and elaborates the VHDL design. Then we define design environment such as wire load model and operating conditions. Next, timing and area constraints are defined. By running the concerned scripts, the tool will synthesize the design and generate reports, which will provide estimation of Silicon area cost. 8.3.3 Elementary test 2: ASIC Power Consumption estimated

Once ASIC synthesis results provide satisfactory results, a second elementary test will be performed. Post-layout simulations are performed to evaluate the power consumption of the design. Estimation of Power Consumption will be reported for the synthesized design. Both static and dynamic power consumption will be estimated. Static power consumption is usually proportional to the area of the design and considers an estimation of the current necessary to power the different cells of the design. Dynamic power consumption on the other hand, estimates the current necessary for the implemented logic to perform the required operations that are implemented on the design. Dynamic power consumption is heavily dependent on the statistics of the signals operating through its nodes. 8.3.3.1 Testbench setup specification

The goal of this test is to estimate Power Consumption. The VHDL description of the LDPC decoder will receive inputs from a testbench. The tool will be used to generate reports regarding the Static and Dynamic Power Consumption: performance will be tuned by the means of simulation scripts. 8.3.3.2 Test procedure description

A representative set of stimuli is used to test the design and give a current power consumption figure related to the activity of the design.



Expected outcome: Power consumption and comparison with SoTA for 65nm technology node.

OBJECTIVE Power consumption estimation and comparison with SoTA for 65nm technology node.

INTERFACES Simulation scripts.


ASIC synthesis results provide satisfactory results



8.3.4 Elementary test 3: FPGA Emulation 8.3.4.1 Testbench setup specification

Finally, extensive functional coverage of the design is performed by FPGA emulation. The same design will be synthesized, mapped and routed to the FPGA platform for extensive functional verification.

Figure 8-4. Envisaged demonstration setup as expected in month 23


A set of stimuli testbench is used to evaluate extensive coverage of the design in different modes.

OBJECTIVE Extensive functional coverage of the design performed by FPGA emulation and demonstration.

INTERFACES N/A PRECONDITIONS

(optional) ASIC synthesis results provide satisfactory results. Power consumption estimation at least as SoTA.





8.3.5 Test results

This section summarizes the results that will be obtained for NRG and UDR KPI. The following tables will be filled with more information once the previously described test procedures will be performed on PoC 6 (i.e. a complete and final report of these tests will be contained in final deliverable D6.2). The goals are to provide an architecture with high throughput of more than 1 Gbps and to provide an architecture that is highly optimized for power and energy consumption. The following table summarizes the three elementary tests results

Table 8-4. PoC 6 test results.


Silicon Area Cost

Better than SoTA ( 11,4 mm2)

- -

Power Consumption

Better than SoTA (145mW)

- -

Functional performance

of implemented

LDPC

BER vs SNR

- The goal is to compare theoretical performance of LDPC with that of implemented version.


PoC 6 has been considered for inclusion in the following scenarios of Broadband Access in Dense Areas and particularly for Crowded venues and Dynamic hotspots. In these two scenarios, the KPI of user data rate (UDR) is crucial, and so is energy efficiency (NRG) for Dynamic Hotspots. The LDPC decoder will contribute to fulfil these two objectives. Indeed, increase in user data rate will be enabled by achieving higher decoding throughput. Moreover, energy efficiency will be addressed by reducing the power consumption of the LDPC decoder. We note that decoder’s throughput and power consumption depend only on the hardware implementation and are independent of the channel model, RF impairments, etc. 8.5 Additional considerations


Table 8-5. PoC 6 time plan. Component/Task M6 M12 M18 M24

Specifications Choice of demonstration Platform

Specifications of Decoder, Choice of demonstration platform

- - -

Architecture Definition of an architecture

Development of a baseline Architecture-

- -



Design - Preliminary Validation of design

Preliminary prototype available,

-

Results - Performance evaluation results

Refined performance evaluated

Final evaluations, Reporting in WP6 deliverable

Demonstration - - - Final Demonstration



9. HW/SW function split for energy aware communications (PoC 7) The inability to tune the operation of a device in terms of e.g. functionality vs. energy consumption, caused by the inability to change the operation of hardware, precludes a fine-grained optimisation of the energy consumption of wireless access networks. To enable a more efficient operation of such networks towards 5G, we advocate for a flexible partitioning and reconfiguration of the hardware-accelerated (HWA) and software (SW) baseband building blocks which are distributed across different processing domains of the radio access network (RAN). The flexible HW-SW function partitioning applied in this proof-of-concept (PoC) focuses on delivering energy efficient 5G mobile networks, as a top-up feature or technology enabler of network function virtualization (NFV), software defined networking (SDN) and mobile edge computing (MEC) (all of which are essential building blocks for developing 5G networking ecosystems). Moreover, the PoC 7 HW-SW function partitioning can be used to build flexible and energy efficient cellular systems, where both the processing elements and wireless communication parameters can be reconfigured at run-time. Hence, the idea of this PoC is to demonstrate in a practical way the energy saving benefits that the flexible partitioning and reconfiguration of hardware-accelerated (HWA) and software (SW) functions can bring to 5G networks. 9.1 Short description

The PoC is based on the architecture shown in Figure 9-1. It is mainly meant to form part of the Dynamic Hotspots use case, but it has also relevance with the use cases related to vehicular communications: “Broadband in Vehicles” and “V2X communications for enhanced driving”. Under these use cases, the architecture utilized in this PoC assumes a number of small cells deployed in places where the coverage, number of subscribers and overall capacity requirements cannot be sufficiently served by the macro base stations (BS). Such places include among others shopping malls, university campuses, large venues, central train stations, public libraries or other large public service buildings. The central idea of this PoC is that the HWA and SW baseband and networking functions of the dynamic hotspots (i.e., we consider LTE-based small cells in this PoC due to the absence of a 5G air interface) can be reconfigured, partitioning their operation across different nodes in 5G networks; this would be made feasible by connecting the small cell nodes either with intermediate nodes (IN) that will include micro data centres, or directly with Cloud computing solutions by employing high speed communication links (e.g. fibre optic). In our case, the IN can been seen as a MEC-like node running virtualized communications stack functions as an additional type of application. In the context of this project the network reconfiguration will not be dynamic, but it would rather be based on offline switching between given configurations.

Figure 9-1. A high-level overview of the PoC 7 architecture.



In order to provide a flexible HW/SW partitioning and reconfiguration of the baseband and networking HWA and SW functions, different drivers, applications and I/O interfaces are being developed in WP4. A limited number of network configurations have to be thus defined. Reconfiguration from one network configuration to another may occur according to different triggers that are defined by the KPIs. A generic flexible framework of any possible network (re)configuration would require on-the-fly cognitive decision making based on real-time processing of different network metrics and measurements at component or sub-system level; however this implies a far more profound and complex development at WP4 and thus falls out of the scope of this PoC (i.e., it can be envisaged as a future extension of the work that will be presented in this PoC). Although the mentioned small cell reconfiguration can satisfy different KPIs, PoC 7 focuses on the KPI related to energy savings. This is particularly relevant considering that unlike conventional base stations where the baseband processing consumes a small fragment of the total energy budget, in small cells this does not hold true anymore since the baseband processing is one of the main contributors (see Figure 9-2 for more details). Apart from the energy savings, other OPEX benefits are also expected, although they will not be analysed in the framework of this PoC.

Figure 9-2. DC power consumption breakdown for different types of BSs at maximum load [Ear10].

As already mentioned, there is a myriad of different use-cases that can be demonstrated in this PoC, since distributing and reconfiguring the baseband HWA and SW functions can result in a large number of different network configurations targeting different KPIs. Nonetheless, in this PoC we have limited down these cases to reduce the implementation complexity as well issues related to integration, deployment and so on. The projected network flexibility can be achieved by switching from a given network configuration (NETCFG) to another featuring a different partitioning of its underlying SW and HWA communication stack functions, in order to achieve KPIs related to energy savings. In more detail, this PoC considers the following NETCFGs:

• NETCFG#1: the physical-layer (L1) is configured locally at the eNB node, whereas higher eNB layers (L2 and above) together with the evolved packet core (EPC) run in the Cloud, aiming at a partial Cloud offload.

• NETCFG#2: the L1 is configured locally at the eNB node, whereas higher eNB layers (L2 and above) are configured in a MEC-like application running in the intermediate node (IN); the EPC runs in the Cloud. This configuration is clearly thought to serve or complement MEC paradigms.



• NETCFG#3: The eNB is used in this case is just hosting a remote radio head (RRH), while the entire eNB communication stack is configured in the Cloud together with the EPC, following a typical fully centralized CRAN setup.

The network flexibility can also be achieved by modifying specific wireless communication parameters (WCP) or a functional set of L1 blocks. In more detail, this PoC considers a subset of the following WCPs:

• WCP#1 applies bandwidth scaling (i.e., 1.4, 5, 10 and 20 MHz). • WCP#2 constraints the maximum allowed modulation and coding scheme –MCS-

(index 0-28)1

• WCP#3 applies waveform switching (e.g., from 4G LTE to a candidate 5G) or in-band waveform aggregation.

.

• WCP#4 modifies the antenna scheme (e.g., from SISO to MIMO). • WCP#5 applies adaptive transmitter power tuning (i.e., -4,-1, 0, 1, 3, 4 dBm steps). • WCP#6 modifies current consumption and gain in power amplifier (PA) back-off

conditions. The conditions that would trigger this reconfiguration are envisioned to be emulated for the validation needs of PoC 7. Hence, the final goal of this PoC is to evaluate the benefits of the flexible partitioning and reconfiguration of the HWA and SW baseband building blocks by reproducing realistic data traffic load conditions of representative small cells operating scenarios. The energy savings are shown at eNB level. Hence, each one of the three NETCFGs with variations of specific WCPs are measured at specific components of the eNB to assess the energy cost. These eNB components include the baseband processing IC, the RF transceiver IC, the chipsets related to the high speed communication links (e.g., GigE) and optionally the power amplifier (PA). All these components are generic off-the-shelf and principally used for prototyping means, instead of targeting end-products. Hence the energy measurement campaign of the NETCFGs and WCPs applied on these devices provide a relative yet indicative order of magnitude of the energy footprint. An illustrative example that could find a practical and realistic use is described hereafter:

We assume a public library where a number of small cells operate. The mobile operator wants to benefit from the fact that the data-traffic decreases during lunch time, between 12:30 pm and 2:00 pm. We assume that the traffic volume patterns and tendencies are known a priori. Hence at this time slot, the operator scales the signal bandwidth of the small cells from 20 to 5 MHz and also switches from one network configuration to another, in order to achieve energy savings at baseband processing and RF transceiver level. 9.2 Partners and roles

Table 9-1 summarizes the devices/interfaces and roles of each partner inside this PoC. 1 The CQI might be overridden in case the targeted KPI imposes a more conservative MCS (e.g., for energy savings purposes)..



Table 9-1. PoC 7 partner roles. Partner Devices Interfaces Role

Name HW modules

SW modules Name Devices

connected Protocol

used

CTTC

Xilinx Zynq-7000

ZC706 [XIL16]

The HWA L1 (DL)

and part of the L1-L2 interface

runs on the PL area of the Zynq FPGA-

based SoC device

Apps, drivers and part of the L1-L2

SW interface run on the PS of the

Zynq FPGA-based SoC

device

GigE, 10GigE

General purpose server

(Extreme testbed)

IEEE 802.3

PoC 7 leader. CTTC

9.1

develops (WP4), integrates and experimentally validates (WP6) the 3 network configurations mentioned in section , on top of the procurement of the PoC boards and T&M equipment.

HW/SW provider: HW: FPGA-accelerated LTE baseband functions

SW: LENA open source LTE EPC Network Simulator

Integration with other partners: Power measurement solutions at component or subsystem level provided by UC3M (offline measurements)

Serial I/O

Two Xilinx ZC706 boards

CPRI

Spec. V6.0

FMC

Analog Devices

FMCOMMS3 board

VITA-57.1

JTAG Xilinx ZC706 and a PC JTAG

Analog Devices

AD-FMCOM

MS3

FMC board

[ADF16]

AD9361 RF

transceiver

IC

Linux app to control the AD9361

FMC Xilinx ZC706 VITA-57.1

Power Amplifier

evaluation board

NA SMA Power amplifier NA

Extreme Testbed [EXT06]

Generic purpose servers

configure either as a data-center

or split across the network.

Host the IN or CRAN solution

where LENA [Len16] eNB

L2 and above stack together with the LTE EPC run. Part of the L1-L2

SW interface reside in the

IN or the Cloud.

GigE, 10GigE

Xilinx ZC706 boards hosting

either the eNB (L1 DL)

or UE (L1 DL)

IEEE 802.3

UC3M

Power measure-

ment solution for the Zynq

device

TI DAQ module

TI Fusion Power

Designer GUI

USB

PC running the TI GUI interfaced with the

Xilinx ZC706 board

through the TI USB DAQ

module

USB/

custom

UC3M

NI PCI-6289 DAQ

assists on the characterization of the energy consumption of the different elements of the eNB prototype node. To this aim, UC3M is adapting the methodology for fine-grained characterization of 802.11 devices for

High-accuracy

DAQ solution.

NA Custom I/O

AD-FMCOMMS3

-EBZ, NA



device 32 analog inputs using 2

SCB-68A connect blocks

PA,

GigE chip (ZC706 board)

the case of cellular schemes, based on a combination of commercial, off-the-shelf equipment and ad-hoc circuitry.

Hardware/Software provider: HW: DC power supply, National Instruments DAQ, custom three-port circuit.

SW: Command-line tool based on Comedi drivers and libraries.

Linux PC

This HW is being used to host the

DAQ device

Comedi drivers + libraries;

Linux program performs measure-

ments

PCIe bus

The DAQ device

connected to the Linux PC

PCIe

Custom con

version circuitry

Custom circuits that

1) adapt voltage

signals and 2) convert and adapt

current signals for the DAQ device.

NA Custom

FMCOMMS3 RF

transceiver board, Power

Amplifier unit, Xilinx

ZC706 board and with the DAQ device.

NA


PoC 7 focuses on the energy efficiency related KPI. However it can also serve different KPIs for different use cases as highlighted in Table 9-2 that follows.

Table 9-2. PoC 7 KPI table. KPI Related Use Case(s) Comment

FVR Dynamic hotspots, Connected vehicles (part 1)

One of the main objectives of this PoC is to be able to reconfigure the network through different pre-characterized HWA-SW partitioning. On top of this, certain WCPs could be tuned serving likewise a rich and versatile reconfiguration environment.

NRG Dynamic hotspots

The flexible HWA-SW partitioning across 5G network elements and the tuning of WCPs (e.g., bandwidth, multi-antenna scheme, 4G-5G waveform switching) that this PoC aims at demonstrating can be used to fulfil specific energy budgets (dropping in parallel OPEX costs). When traffic data loads and trends are known a priori (or could be predicted through offline calculations/estimations) the reconfiguration of the HWA and SW functions would be able to yield significant energy savings.

UDR Dynamic hotspots, Connected vehicles (part 1)

The flexible tuning of WCPs (e.g., multi-antenna scheme, MCS, 4G-5G waveform switching) in this PoC can be used in a different way compared to the previous KPI, in order to increase the user data rate.



LAT Connected vehicles (part 2) The different NETCFG modes considered in this PoC could be used to flexibly satisfy the needs of tighter or relaxed latency requirements according to different data traffic and user density conditions.


As already mentioned before, in the absence of a 5G air interface, the 4G LTE is used instead. In more detail, the LTE stack is based on the following SW and HWA building blocks:

• SW: The LENA LTE open source simulator-emulator (eNB, UE & EPC) born and maintained at CTTC [Len16].

• HWA: The LTE-based DL L1 FPGA implementation developed at CTTC [Fon15].

The mentioned SW and HWA building blocks are currently sustaining significant modifications and extensions in WP4. Their modular integration, validation and testing with the hardware platform introduced in Table 9-1 (and further described in this section) is ongoing. The DUT is provided and operated by CTTC. The energy efficiency (NRG) KPI will be measured and validated using an eNB prototype assembled by commercial off-the-shelf (COTS) development boards. In order to measure and evaluate NRG KPI, the test and measurement solution (TMS) detailed in Table 9-2 is provided and operated by UC3M. The versatility of PoC 7 might be exploited in the future to measure and evaluate other KPIs, which nevertheless does not fall within the scope of WP6 tasks. The relation of this PoC with the principally targeted KPI (NRG) and with other KPIs is detailed in Table 9-3.

The testing and validation of PoC 7 is divided in two following stages: Offline

measurement campaign

The NRG KPI will be evaluated with an extensive measurement campaign which will be conducted offline, as described in section 9.3.2 detailing the elementary tests 9.3.2.1, 9.3.2.2 and 9.3.2.3.

Real-time demonstration

Part of the PoC 7 setup will showcase in real-time the NRG KPI and other KPIs potentially related to FVR, UDR and LAT (during the final review of the project), as described in section 9.3.2.4.

The NRG is the main KPI targeted in this PoC and it will be validated through a measurement campaign.

Table 9-3. The KPIs that PoC 7 targets. KPI Relevance to the proof-of concept Comment

NRG

Modifying the distribution of HWA and SW baseband processing functions across different network elements (NETCFGs) and tuning WCPs can be used to fulfil specific energy budgets. This is especially important when traffic data patterns are known a priori (or could be predicted through estimations).

The energy efficiency could also be associated with cost reduction (OPEX)

FVR

The PoC is featuring inherent ability to reconfigure specific HWA and SW processing blocks of the LTE communication stack in flexible network configuration setups, as well as modify specific WCPs.

The degree of flexibility and re-configurability is defined by the NETCFGs and WCPs.



UDR

Although this KPI is not directly addressed in this PoC, the flexible tuning of WCPs (e.g., multi-antenna scheme, coding, 4G-5G waveform switching) can be used to increase the user data rate.

No measurement campaign will be performed related to this KPI; metrics might be demonstrated.

LAT

The different NETCFGs could be used to flexibly satisfy the needs of tighter or relaxed latency requirements according to different data traffic and user density conditions.

No measurement campaign will be performed related to this KPI; metrics might be demonstrated.

The DUT employed to evaluate the energy efficiency KPI include the following general purpose prototyping boards and servers: eNB and UE L1 DL baseband processing

• HWA processing blocks are hosted in the Zynq FPGA-based SoC device of the Xilinx ZC706 board (Figure 9-3). Precisely, the eNB and UE L1 DL and part of the L1-L2 interface are hosted in the programmable logic (PL) side of the Zynq SoC device. The Xilinx ZC706 board is connected with the remaining of the eNB DL system (residing in different server configurations) either using a GigE/10GigE connection or a custom serial I/O cable connection (i.e., defined in the Xilinx CPRI reference design).

• SW processing blocks: a number of Linux applications/drivers and part of the eNB and UE L1-L2 interface is currently developed (WP4) to be hosted in the processing system (PS) of the Xilinx Zynq FPGA-based SoC device.

eNB and UE mixed signal and RF signal processing • HW modules: The Analog Devices AD-FMCOMMS3-EBZ RF transceiver board

(Figure 9-4) is interfaced with the Xilinx ZC706 board through an FMC connector/bus. A PA unit, a RF band filter and an antenna will also be used for the eNB, while UEs will use equivalent RF band filters and antennas.

• SW modules: A Linux kernel space application that runs at the PS side of the Xilinx Zynq SoC device (Xilinx ZC706 board) is used to control and program the AD9361 RF transceiver IC.

Figure 9-3. The Xilinx ZC706 board.

Figure 9-4. The AD-

FMCOMMS3-EBZ board.



CTTC’s EXTREME Testbed • HW modules: The EXTREME testbed [EXT06] (Figure 9-5) comprises generic

purpose servers configured either as a datacenter or distributed throughout the network.

• SW modules: the EXTREME testbed hosts LENA’s SW-based eNB stack (i.e., L2 and above implemented as IN or as CRAN setup), UEs stack (L2 and above) and the EPC. EXTREME is interfaced with the ZC706 boards of the eNB and UEs using GigE/10GigE connections. Figure 9-6 shows an overview of the native functionality featured in LENA (i.e., before the extensions and modifications developed in WP4).

Figure 9-5. CTTC’s EXTREME

testbed.

Figure 9-6. Overview of LENA’s LTE-EPC simulation model.

Figure 9-7 shows a high-level representation of the entire PoC setup

which might be used in the future for a number of different experimental evaluations. The L1 HWA processing blocks and the L1-L2 interface of the eNB and UEs are transforming a LTE simulator like LENA to a real-time experimentation environment. Indeed, given CTTC’s LTE L1 FPGA-based implementation (DL), this is the most straight forward way that LENA UEs could receive real-life DL signals transmitted over-the-air.

Figure 9-7. The DUT and interfaces of the PoC 7.



9.3.2 Elementary Tests

The devices, interfaces and evaluation of the focused NRG KPI of this PoC are depicted in the three network NETCFG figures shown in the following subsections. The dark blue boxes represent different processing elements that will host the HWA and SW communication stack functions developed by CTTC in WP4. The illustrated power meter devices represent the offline energy consumption measurement campaign that will be conducted by UC3M at the following components:

• Xilinx Zynq SoC • Ethernet chipset • AD9361 RF transceiver IC • Power Amplifier (optionally, in case WCP#6 will be applied)

Table 9-4 presents a summary of those test cases where each NETCFGs or WCPs separately (in blue or light blue colour) can be modified to achieve the eNB energy reduction KPI

Table 9-4. The test cases involving NETCFGs, WCPs and different KPIs.

(NRG, in light green colour). The same applies to other KPIs that this PoC could target. In the table, “→” denotes NETCFG transition or WCP modification, “↓↑” denote decrease and increase of a WCP index respectively and “” denotes activation or selection of a NETCFG or WCP to achieve a given KPI.

KPI

NETCFGs & WCPs that can be modified or selected to serve a specific KPI NETCFG#1

(partial cloud off-load)

NETCFG#2 (MEC-

based IN)

NETCFG#3 (CRAN)

WCP#1 (BW)

WCP#2 (MCS)

WCP#3 (waveform)

WCP#4 (antenna scheme)

WCP#5 (Tx

power)

WCP#6 (PA

backoff) NRG 1 → 3 2 → 3 ↓ ↓ → → ↓ ↓ UDR 1 → 2 3 → 2 ↑ ↑ → → NA LAT 1 → 2 3 → 2 NA NA → (tbc) NA NA NA

FVR 1 → 2 1 → 3

2 → 1 2 → 3

3 → 1 3 → 2

↑↓ ↑↓ → → →

↑↓ ↑↓

In order to assess the benefits of an energy-aware reconfiguration of the network, a specific test case of energy profiling is selected to be used as a baseline for comparing different combinations of NETCFGs and WCPs under different traffic conditions. The baseline configuration represents the one that is anticipated to have the lower energy footprint, when quantifying the energy profile at the ICs of interest, as showing in Table 9-5. As it can be observed the baseline configuration includes the low-rank specifications of an eNB.

Table 9-5. The baseline configuration specifications. Baseline test case specifications

# of UEs NETCFG WCP#1 WCP#2 WCP#3 WCP#4 1 3 1.4 0-9 4G LTE SISO

9.3.2.1 NETCFG#1: partial Cloud off-load 9.3.2.1.1 Testbench setup specification

The energy profiling of the Xilinx Zynq SoC, the Ethernet IC and the AD9361 RF transceiver residing at the eNB prototype will be evaluated in the NETCFG show in Figure 9-8.



Figure 9-8. The NETCFG#1.

An overview of the testbench setup is given in Table 9-6. Table 9-6. NETCFG#1 testbench setup.

Objective Measure the NRG KPI using the NETCFG#1 and modifying the WCP#1 and WCP#2 for a varying number of users. Other secondary KPIs that PoC 7 targets (LAT, UDR) might also be measured in this NETCFG.

Interfaces The NRG TMS solution provided by UC3M will be interfaced with the Xilinx ZC706 board and the Analog Devices AD-FMCOMMS3-EBZ.

Preconditions Measuring the consumed energy at the AD-FMCOMMS3-EBZ board might imply removing an on-board component (e.g., 0 Ohm resistance). A preliminary measurement campaign has to be planned a priori.

Priority High (all configuration have basically equal importance).

Responsible partners

UC3M leads the measurement campaign, CTTC provides support throughout the process.

9.3.2.1.2 Test procedure description

In this test, each value of WCP#1 is combined with each value of WCP#2 for a varying number of users and traffic conditions as described in Table 9-7 that follows and partially shown in Figure 9-9. The energy measurement campaign is meant to be conducted for each configuration separately in the specified ICs.

Table 9-7. The test procedure steps. Procedure description 1. Bandwidth is set to 1.4MHz.

PoC 7 is configured with NETCFG#1

2. Number of active UEs is set to 1. 3. A value from the first MCS index group is selected (i.e., QPSK).

a. DL traffic is generated for a specific number of frames (e.g., full buffer or different constant bit rate).



i. The TI Power Fusion software measures and logs the consumed power at the Zynq XC7045 device (Xilinx Zc706 board).

ii. The UC3M TMS measures and logs the consumed power in the AD-FMCOMMS3-EBZ board and also in the GigE IC of the Xilinx ZC706 board.

iii. From network level perspective metrics like the throughput and the one-way delay required by the transport links might be evaluated by means of the ns-3 simulator, Wireshark or software tools that inject traffic for measuring in real-time (e.g., MGEN, NETFLOW or NETSAS).

4. A value from the second MCS index group is selected (i.e., 16-QAM) and the previous inner-loop process is repeated (3.a.i to 3.a.iii).

5. A value from the third MCS index group is selected (i.e., 64-QAM) and the previous inner-loop process is repeated (3.a.i and 3.a.ii).

6. The previous steps (3 to 5) are repeated for 2 and 3 active UEs. 7. The entire procedure is then repeated for the remaining bandwidths (5, 10

and 20 MHz) and for up to 6 active UEs (steps 1 to 6).

Notes • All logged data are compared with the baseline configuration. • The number of active UEs is limited to 6, given the fact that the

deployment of more UEs has practical, technical and budgetary limitations.

Figure 9-9. A snapshot of the measurement campaign log-file (due to be conducted for

this test case). 9.3.2.1.3 Expected Output

• The effect of the number of active UEs on the NRG and LAT KPI (possibly also on the end-to-end and QoE metrics)

o It is not clear if the number of active UEs will have any effect at all on the energy consumed by the ICs of interest. If the allocated data for each active UEs remain the same, then there might be an energy reduction in the Ethernet IC consumption when the number of active UEs reduces (for the same bandwidth).

o It is expected that the number of UEs will impact the transport network in terms of throughput and one-way latency.

• The effect of bandwidth scaling on the NRG and LAT KPI (possibly also on the end-to-end and QoE metrics)

o Reducing the bandwidth is expected to drop the energy consumption of Xilinx Zynq SoC, the Ethernet IC and the AD9361 RF transceiver IC.

o End-to-end metrics might be affected by the reduction of the bandwidth in case the new bandwidth does not support the UE QoS requirements.

XC7045 AD9361 GigE PHY1.4 5 10 20 from 0 to 9 from 10 to 16 from 17 to 28

Wireless Communication Parameters (WCP)Energy measurements (for a given number of DL

frames & measurement resolution)#2: Modulation & Coding Scheme index

Number of active UEs

1 2 3 4 5 6

NETCFG

#1: Bandwidth (MHz)#1 #2 #3



• The effect of the MCS on the NRG and LAT KPI (possibly also on the end-to-end and QoE metrics)

o It is likely that a higher MCS index might result in a marginally higher energy consumption of the Ethernet IC and the AD9361 RF transceiver IC.

o The MCSs has a trade-off in terms of bandwidth and latency, in fact by increasing the MCS the first grows, while the second decreases.

9.3.2.2 NETCFG#2: exploiting MEC topologies 9.3.2.2.1 Testbench setup specification



The setup of the energy measurement campaign is the same as in NETCFG#1. 9.3.2.2.2 Test procedure description

The test procedure is the same as in NETCFG#1. 9.3.2.2.3 Expected Output

The expected outputs for the NRG KPI coincide with those of NETCFG#1. 9.3.2.3 NETCFG#3: CRAN 9.3.2.3.1 Testbench setup specification





The setup of the energy measurement campaign is the same as in NETCFG#1 and NETCFG#2. 9.3.2.3.2 Test procedure description

The test procedure is the same as in NETCFG#1 and NETCFG#2. 9.3.2.3.3 Expected Output

• The effect of the number of active UEs on the NRG KPI o Similar with that of NETCFG#1 and NETCFG#2.

• The effect of bandwidth scaling on the NRG KPI o While the energy consumption of the AD9361 RF transceiver IC will not be

affected, the Xilinx Zynq SoC device is expected to consume less energy when compared to each of the equivalent test cases of NETCFG#1 and NETCFG#2. A serial I/O connection (CPRI traffic) will replace the GigE connection of NETCFG#1 and NETCFG#2.

• The effect of the MCS on the NRG KPI o Similar with that of NETCFG#1 and NETCFG#2.

9.3.2.4 Real-time Demonstration 9.3.2.4.1 Testbench setup specification

The energy profiling of the Xilinx Zynq SoC residing at the eNB prototype will be evaluated in the real-time demonstration shown in Figure 9-12. Moreover, a set of network-level parameters can be provided, together with some QoE statistics on video transmission quality.



Figure 9-12. The PoC 7 setup for the real-time demonstration.

An overview of the testbench setup is given in Table 9-8 Table 9-8. Real-time demonstration testbench setup.

Objective Measure the NRG KPI and modifying the WCP#1 and WCP#2 for a varying number of users in order to evaluate the effects on a video-streaming transmission. Other secondary KPIs that PoC 7 targets (LAT, UDR) might also be measured in this NETCFG.

Interfaces The TI Power Fusion software runs on a PC that is connected through a TI USB device to the Xilinx ZC706 board from where electric current and electric potential data is extracted from the Zynq XC7045 SoC device. A video-streaming application will be running on the UE and video server sides.

Priority High.

Responsible partners

CTTC will lead the activity whereas UC3M will provide support if required.

9.3.2.4.2 Test procedure description

In the real-time demonstration, some representative values of WCP#1 are combined with a subset of values WCP#2 for a varying number of users and traffic conditions as described in Table 9-9 that follows.

Table 9-9. The test procedure steps. Procedure description

1. PoC 7 is configured with NETCFG#1 2. Bandwidth is set to 1.4MHz. 3. Number of active UEs is set to 1. 4. A value from the first MCS index group is selected (i.e., QPSK).

a. DL video traffic is generated for a specific number of frames. i. The TI Power Fusion software measures and displays in

real-time the consumed power of the XC7045 device.



ii. From network-level perspective metrics like the throughput and the one-way delay required by the transport links might be evaluated.

iii. The QoE can be evaluated in order to have also a user metric for instance by using video quality analyser (e.g., with MSU – Moscow State University - software). In addition, end-to-end metrics can be evaluated by software tools that inject and measure traffic in real-time (e.g., MGEN, NETFLOW or NETSAS).

5. A value from the second MCS index group is selected and the previous inner-loop process is repeated (4.a.i to 4.a.iii).

6. The entire procedure is then repeated for two more representative bandwidths and for more active UEs (steps 1 to 4).

7. PoC 7 switches from NETCFG#1 to NETCFG#3 a. Steps 4.a.i to 4.a.iii are repeated

Notes • The number of active UEs will be less than those used in the offline measurement campaign considering that the final review will take place off-site, in order to simplify technical and logistic issues.

9.3.2.4.3 Expected Output

• The effect of the number of active UEs on the NRG and LAT KPI (possibly also on the end-to-end and QoE metrics)

o It is not clear if the number of active UEs will have any effect at all on the energy consumed by the IC of interest.

o The number of UEs will have an impact on the transport network (front/back-haul) in terms of bandwidth and latency.

• The effect of bandwidth scaling on the NRG KPI and LAT KPI (possibly also on the end-to-end and QoE metrics)

o Reducing the bandwidth is expected to drop the energy consumption of Xilinx Zynq SoC.

o The QoE might be affected by a bandwidth reduction in case the requested data-rate of the video cannot be satisfied by the new bandwidth configuration.

• The effect of the MCS on the NRG KPI and LAT KPI (possibly also on the end-to-end and QoE metrics)

o No energy impact is expected on the Zynq SoC device. o Higher MCSs imply transport block of higher size, which in turns translates in

higher bandwidth requirements from transport network perspective. On the other hand, it reduces the latency.

9.3.3 Tests Results

This section summarizes the results that will be obtained during the offline measurement campaign related to the NRG KPI. The following tables will be filled once the previously described measurement campaigns will be performed on PoC 7 (i.e. a complete and final report of these test will be contained in final deliverable D6.2).



9.3.3.1 Test1: NETCFG#1

Table 9-10. PoC 7 NETCFG#1 Results. Requirements Expected Results Observed Results Comments

Start from 1 active UE and increase them accordingly for a given bandwidth

NRG: minor impact on the GigE consumption if the allocated data for each UE remain the same when the number of active UEs reduces (for the same bandwidth). LAT: the number of UEs will impact the transport network in terms of throughput and one-way latency

NRG: LAT (optional)

Maximum of 6 active UEs due to HW and PoC setup limitations. Results will be extracted following the procedure shown in Figure 9-9.

Modify WCP#1

NRG: Reducing the bandwidth is expected to drop the energy consumption of Xilinx Zynq SoC, the Ethernet IC and the AD9361 RF transceiver IC. LAT: End-to-end metrics might be affected by the reduction of the bandwidth in case the new bandwidth does not support the UE QoS requirements.

NRG: LAT (optional)

1.4, 5, 10 and 20 MHz

Modify WCP#2

NRG: It is likely that a higher MCS index might result in a marginally higher energy consumption of the Ethernet IC and the AD9361 RF transceiver IC. LAT: The MCSs has a trade-off in terms of bandwidth and latency, in fact by increasing the MCS the first grows, while the second decreases.

NRG: LAT (optional) Index 0-28




NRG: minor impact on the GigE IC energy consumption if the allocated data for each UE remain the same when the number of active UEs reduces (for the same bandwidth). LAT: Reduced impact when compared to NETCFG#1 (due to the portion of the transport network that carries the S1 traffic).

NRG: LAT (optional)

Maximum of 6 active UEs due to HW and PoC setup limitations. Results will be extracted following the procedure shown in Figure 9-9.

Modify WCP#1

NRG: Reducing the bandwidth is expected to drop the energy consumption of Xilinx Zynq SoC, the Ethernet IC and the AD9361 RF transceiver IC. LAT: Better LAT results are expected when compared to NETCFG#1.

NRG: LAT (optional)

1.4, 5, 10 and 20 MHz

Modify WCP#2 NRG: It is likely that a higher MCS index might result in a marginally higher energy consumption of the




Ethernet IC and the AD9361 RF transceiver IC. LAT: Better metrics are expected when compared to NETCFG#1.




NRG: similar output is expected with that of NETCFG#1 and NETCFG#2. LAT: it will be increased in respect to NETCFG#1 due to the typical high requirements of CPRI traffic both in terms of latency and throughput.

NRG: LAT (optional)

Max 6 active UEs due to HW/PoC setup limitations. Results will be extracted following procedure shown in Figure 9-9.

Modify WCP#1

NRG: Reducing the bandwidth is expected to drop the energy consumption of Xilinx Zynq SoC and the AD9361 RF transceiver IC. LAT: Reducing bandwidth will reduce the requirements of the CPRI traffic that, in turn, will mitigate the effect on latency and throughput.

NRG: LAT (optional)

1.4, 5, 10 and 20 MHz

Modify WCP#2 NRG: similar to NETCFG#1 and NETCFG#2 LAT: similar to NETCFG#1 and NETCFG#2



PoC 7 is mapped with the following use cases:

• Dynamic hotspots (Broadband access in dense areas). By definition the dynamic hotspots must feature some sort of re-configurability in order to provide flexibility of operation, along with energy efficiency, scalable BW, adaptive coverage and higher data rates, which are basically the KPIs that can be served by this PoC 7 (though the focus will be on energy savings).

• Mobile broadband in vehicles and V2X communications for enhanced driving (Broadband access everywhere, Massive Internet of Things). The reconfiguration capacity and flexibility of the HW and SW functions of PoC 7 can be exploited in environments with high vehicular mobility where rapid changes in the propagation channel take place, in order to guarantee the perceived quality of service (e.g., in terms of achieved rate. latency or link reliability).


• Plethora of network configuration options, thus heavy development is envisioned o This was the reason that NETCFGs were limited to 3 for the specific PoC 7

purposes.

• UC3M will provide the energy measurements of the baseband chip, the RF transceiver IC and the GigE communication link (other communication interfaces can be possibly considered). Optionally, energy measurements of the Power Amplifier linked to WCP#6 will also be considered. Before that, CTTC would have to develop and test in the final



hardware platform the three NETCFGs. Hence, the energy profiling of the previous components is a sequential and iterative task that depends on CTTC’s development (WP4), HW integration and run-time testing advances (WP6). This might entail a risk of delays.

o The development of the three network configuration modes from CTTC’s side is sequential and independent one from the other. Hence once the first will be made available, UC3M will be able to make their energy measurement campaign.

o The energy profiling of the components mentioned before and the familiarization of UC3M with the HW platform may start at an earlier stage without necessarily CTTC having one of the 3 configuration modes developed and tested.

9.6 Time plan and availability

The preliminary PoC 7 work plan from CTTC side for the period M1 - M23 is presented in the following. Since CTTC is involved in WP4 (development) and WP6 (integration of WP4 development and validation of PoC) the work plan is a mixture with iteration steps of the two WPs.

• Activity 1: Preliminary analysis of the Hardware-accelerated building blocks (part of W4.1 & W6.1), M1-M6.

• Activity 2: Preliminary analysis and specifications of the Software building blocks (part of W4.1 & W6.1), M1-M6.

• Activity 3: Extending, modifying and developing L1 FPGA-based building blocks to serve the three network configurations (part of W4.3), M3 – M23.

• Activity 4: Implementation of embedded Linux kernel space SW applications and APIs for L1-L2 interfacing (part of W4.3), M3 – M23.

• Activity 5: LENA L2 and above development and modifications (part of W4.3), M3 – M23.

• Activity 6: PoC validation (part of W6.2), M6 – M23. The Gantt chart of the previously described tasks is the following:

First year Second year Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 T1 T2 T3 T4 T5 T6

Figure 9-13. Gantt chart of PoC 7. Table 9-13. PoC 7 time plan.

Tasks M6 M12 M18 M24

1

Preliminary analysis of the Hardware-

accelerated building blocks (part of W4.1

& W6.1)

- - -

2

Preliminary analysis and specifications of the Software building blocks (part of W4.1

& W6.1)

- - -



3 Initial study and HDL simulations

Implementation and verification of HWA L1 building blocks

and L1-L2 Integration based on test vectors

NETCFG#1 NETCFG#2, NETCFG#3,

developed and validated in

conjunction with T4 and T5

M23 final integration and validation

4 Initial study Development of the L1-L2 SW interface



conjunction with T3 and T5


5 Initial study Adaptation of LENA’s SW modules of UE

and eNB



conjunction with T3 and T4.


6 Exploration stage Initial validation of the PoC

Initial validation of NETCFG#1

NETCFG#2 and NETCFG#3

Final validation of NETCFG#1,

NETCFG#2 and NETCFG#3



10. Reconfigurable and programmable radio platform (terminal side) and SW programming performed and injected by the network (PoC 8) The goal of this PoC is demonstrating the whole adaptation loop of 5G technologies, by reconfiguring the radio behaviour according to advanced context estimates and different optimization criteria. The main idea is abstracting the wireless device resources regardless of the specific internal architecture, by exposing simple programming interfaces able to read the state of the resources and to enforce a desired configuration, according to decisions taken by a local SW agent interacting with a remote network controller. To this purpose, different types of resources are considered:

i) multiple programmable radio interfaces, with heterogeneous technologies (e.g., WiFi, LTE-A/LTE-U-based cellular technologies, plus outband or inband device-to-device), exposing a common set of API for configuring the physical channels and the medium access rules;

ii) sensors, such as those commonly available in commodity smartphones, including gyroscopes, cameras, accelerometers, etc., as well as specific other sensors (temperature, humidity, pressure, etc.) available in monitoring or metering devices;

iii) additional resources that are made available to the controller, such as battery, storage resources, timing and localization information, forwarding tables (or other data structures).

10.1 Short description

The general view is summarized in Figure 10-1, in which it is enlightened the architectural elements, in terms of HW/resource abstractions and interfaces, as well as the focus of the different partners involved in this integrated demonstration.

Figure 10-1. Reconfigurable programmable radio platform.



PoC 8 considers the following relevant operation modes, in which advanced sensing information allows to identify specific operation contexts:

i) multi-cell dynamic resource allocations, by considering the tracking of user positioning for estimating the time-varying and location-dependent interference;

ii) configuration of device medium access rules, for operating in relay-mode or direct access mode, according to battery state and relay node availability;

iii) switching to/from one technology to another according to the link quality (e.g. mmWave technology under different weather conditions) or activating new resources (e.g. device-to-device links to enable on/off loading as required).

iv) Multi-node dynamic HW/SW partitioning for both device and network element functions either inside or between network stack layers, according to monitored KPIs.

Figure 10-1 contains a graphical representation of the PoC together with the partners’ involvement in the different components of the PoC. The storyline behind the technical PoC 8 motivation previously defined consists on identifying and exploiting specific use cases on which the state of the art network reconfiguration decisions are not intelligent enough to identify all potential situations. In contrast, already existing context aware information provided by sensors could help determining some external events influencing the quality of the network, such as:

• Environmental monitoring is a common application embedded on today’s smart cities. The way the network is organized and reconfigured nowadays is based on a reactive approach, enabling or disabling resources based on the detected scenario (i.e. higher or lower amounts of users connecting to a hotspot). The use of environmental sensor data will help 5G networks to become proactive and able to predict network variations, or fully determining the causes of a lack of quality so as to perform the best counter policy.

o Predicting/measuring weather changes such as rain/snow forecasts in opposition to sunny/warm weather can be effective on preparing resources in advance. Good weather usually means more people outside and higher car speeds, so the resources could be allocated to serve this scenario, whereas bad weather implies people staying indoors and lower car speeds.

o Some emerging 5G technologies such as millimeter Waves (mmWave) are deeply affected by environmental conditions such as humidity and/or rain. Detecting these potential situations will help identifying the cause of a coverage loss, differentiating this case, for instance, with respect to obstacles on the line of sight or user tracking errors.

o On a similar approach, visible light-based communication systems may also use luminosity/fog detection sensors so as to assess the current channel conditions and adapt the modulation scheme.

• User location is also critical for some 5G use cases, on which the user position is a key input to select the best communication option. Apart from using signal strength-based measurements of the cellular connection, it is possible to make use of already existing technologies and infrastructures, such as GPS, WiFi, Bluetooth, NFC…, to further refine the location algorithms, detect proximity to certain network elements and reconfigure the network or the devices themselves accordingly. This topic is specially relevant when talking about i) dynamic resource allocations for estimating the time-varying and location-dependent interference and ii) D2D communication, as detecting a potential D2D partner nearby is critical.



There is a wide plethora of other examples of already existing measurements/technologies susceptible to be used on 5G networks. This PoC aims at demonstrating a subset of the already identified ones in an attempt to validate the concept and prove the reconfiguration features derived from Flex5Gware innovations framed inside the project technical work packages (especially WP5 /Software Architecture). All in all, the overall picture of the concrete functionalities and devices (which will be described along the following subsections) and the mapping to the corresponding project partners involved in the PoC can be seen at Figure 10-2.

Figure 10-2. PoC 8 devices, functionalities and roles.



Table 10-1. PoC 8 Partner roles. Partner Devices Interfaces Role CNIT 802.11-based platforms WMP-

Enhanced boards (WARP, Broadcom), SDR for physical layer monitoring and PHY analysis

HW operations for enhanced PHY layer functions and SW integration in XFSM.

PoC Leader, PHY/MAC enhancement XFSM description and implementation. Extra WMP API integration.

UC3M / IMDEA

802.11-based platforms enhanced for re-configurability (small PCs with Broadcom cards, Atheros) plus programmable LTE-A and LTE-U based platforms using FPGA (NI PXI, USRP). Dual-interface devices to support D2D for offloading. Atheros or Broadcom interfaces for accurate localization mechanisms

Extension of API to support advanced sync. Schemes. Remote activation of D2D communications and D2D mode selection. Monitoring interface for context estimation.

Definition of software agents to orchestrate the MACs of nodes (one or many hops away). Algorithms for node positioning. Activation of offloading techniques based on content information.

WINGS Intelligent Program • Performance-aware

Resource Management

Generic front-end/back-end for sensors abstraction

Design and implementation of software modules in the

[TST

] Sen

sors

[WINGS] Dynamic functional recomposition

[UC3M/IMDEA] Localization – Interface reconfiguration

[CNIT] MAC/PHY adaptations



(software) • Monitoring Library

(software) Remote Network Controller

• Dynamic Functional Re-composition (software)

• Dynamic HW/SW partitioning

Local Resource Controller

• Cooperative control agent(s)

(software) • Monitoring Agent

(software)

Interfaces among Intelligent Program, Remote Network Controller and Local Resource Controller

Remote Network Controller for dynamic functional re-composition and in Intelligent Programs for performance aware resource management. Implementation of software modules in the Local Resource Controller for local control and context awareness. Abstraction of sensors.

TST Sensors/actuators hardware components Sensors/actuators firmware

API between sensors/actuators and Local Resource controller

Sensor integration and programming Communication of sensors with the remote network controller


From the use cases described in D2.1 [Fle21], PoC 8 uses just a subset of KPIs to assess the performance of the proposed enhancements. The following table summarizes the list of KPIs considered, together with a comment related to PoC 8 expectations.

Table 10-2. PoC 8 KPI table. KPI Related Use Case(s) Comment FVR Dynamic hotspots

Smart Cities Connected vehicles

Ability to automatically reconfigure the radio platform (both Device and Remote Network) setup depending on context info.

- Reconfiguration time - Number of potential setups - Number of reconfigurable / programmable

components NRG Dynamic hotspots

Smart Cities How much time the devices can operate without performing maintenance operations.

- Operating time - Stand-by time - Energy consumption

Reduction of active HW functions which compose the network elements and devices.

LAT Smart Cities Connected vehicles

Seamless and continuous communication of nodes (or users) to application servers on an end-to-end manner. Reduction on the time needed for communicating internal and external HW/SW blocks.

- Execution time



- Mean time between failures (MTBF) - Mean time to failure (MTTF) - Mean Time to Repair (MTTR)

ISF Smart Cities Reduction on the device size due to the fact that some tasks can be offloaded to the new sensor gathering module.

- SW memory utilization - HW footprint


Figure 10-3. DUT elements.

The devices used for this PoC 8 are:



• Monitoring Library (Software): This library collects raw measurements from the sensors and transforms them into meaningful information (e.g. prediction of critical events).

• Dynamic Functional Re-composition (Software): Manages the reconfiguration process and decides the suitable functional composition (e.g. optimal HW/SW function split).

• Performance-aware Resource Manager (Software): The Performance-aware Resource Manager provides an integrated solution for enhanced performance and energy reduction. Based on high-level policy information (application/user requirements, QoS, energy efficiency, scalability) and lower level context information (traffic levels/variations, HW capabilities), it proceeds with either the direct reconfiguration (parameterization) of individual resources or the management and configuration of multiple resources (through the Dynamic Functional Re-Composition module).

• Network Controller Server. It collects sensor and network information and implements optimization algorithms based on sensors API, WiFi and LTE configuration tools. The controller server takes control of the overall adaptation loop and sends the configuration commands to the flexible wireless nodes.

• PC Engines Alix or Soekris Boards. Embedded PC equipped with mini-pci port is used to setup WMP-enabled nodes and the APs used for ToF measurements (ToF APs). WMP-enabled nodes are able to run completely different state machines (from legacy DCF to TDMA) which can be configured, injected and loaded by exploiting the WMP control interface. ToF APs give fine-grained localization information and are used by the network controller for running the location-based optimization algorithms.

• Commercial WiFi cards by Broadcom, BCM4318 802.11bg. For these wireless cards it is available a firmware implementing the WMP architecture. They are used with the embedded PCs for building WMP-enabled nodes.

• Commercial WiFi cards by Atheros, legacy WiFi abgn chipset. These commercial WiFi cards are used for device-to-device links, thanks to the availability of a well documented driver on top of which specific management operations and collection of statistics can be easily implemented.

• SDR WARP boards. For these boards it is available an implementation of the WMP architecture, which supported more advanced PHY configuration actions, including the bandwidth dynamic adaptation.

• Programmable Environmental Sensors boards. Based on the hardware and software architecture identified on Flex5Gware for sensor nodes, environmental nodes are used to collect other data useful for optimizations. These nodes cover the assumption of IoT devices deployed on the area of interest and posting data to the Internet. The network controller gathers sensor information for triggering decisions at network level. The following devices are provided:

o 2 Environmental nodes including Temperature, ranging from -40 to 80ºC with 0.1ºC sensibility. Humidity, ranging from 0 to 100% and 1% sensibility. Rain gauge, used to display daily and accumulated rainfall with

0.2mm granularity SigFox interface so as to post data on the Internet

• Programmable Bluetooth Low Energy (BLE) iBeacons. These devices are intended to be placed near to a base station or AP in order to broadcast the capabilities and the configuration options used in each cell, by exploiting an out-of-band signalling channel based on a different technology. By using a TTL (transistor-transistor logic)



serial port, it is possible to configure the information to be broadcasted by the beaconing mechanism.

• Intelligent BLE receivers. The role of this element is to allow that wireless nodes receive the information broadcasted by the BLE beacons. It embeds location algorithms on its code to identify the nearest base station or AP and inform the user.

• Bluetooth 4.0 USB adapters. They are commodity adapters, used to receive the information broadcasted by the BT, which are supported by GNU/Linux with a specific API.

• Ettus B210: It is used as a low-level channel sniffer, thanks to the software modules able to provide a trace describing the channel idle and busy times.

• NI PXI: The required hardware for emulating LTE UEs and eNBs is emboxed in an NI PXI 1082 chassis that contains: (i) NI PXIe 8135 Real-Time controller operating on an Intel Core-i7-3610QE CPU. This controller hosts LabVIEW Real-Time that executes MAC and PHY control algorithms with micro-second resolution; (ii) NI FlexRIO module with Xilinx Kintex 7/Virtex 5 FPGA, which executes PHY operations; and (iii) NI 5791 FlexRIO Adaptor Module (FAM) that is used as an RF transceiver operating with a 100 MHz bandwidth in the frequency range from 200 MHz to 4.4GHz. This is used for Digital to Analog Conversion (DAC), Analog to Digital Conversion (ADC).

• Environmental platform o Wireless Sensor Network (WSN) Board o Indoor Environmental Conditions sensing devices (temperature, humidity,

luminosity) o Breadboard for sensing devices hosting

The general goal of PoC 8 tests is exploiting heterogeneous information provided by sensors and wireless cards (by means of in-band and out-of-band signalling channel) for estimating a specific network context and perform context-specific reconfigurations. By exploiting the programmability offered by WMP-enabled nodes and systems composed by flexible and reconfigurable sensors and/or embedded devices, PoC 8 works on a set of experiments devised to validate the flexibility of these solutions and quantify the flexibility performance gain in specific conditions. Performance gain will be monitored by measuring throughput, delay and other application-level figures, as well as low-level channel figures, such as collision probability, channel occupancy, etc. Device adaptations will be performed at the PHY level (by working on transmission power, frequency tuning, bandwidth configuration, antenna modes, modules activation/de-activation etc.) and/or at the MAC level (by selecting medium access modes or by configuring specific medium access parameters). In what follows, the logic of the adaptation loop is proposed, based on network events and monitoring of some measurements:

1. Event Bootstrap/Attach: This event signals to the controller that the node is attached to their base station.

2. Event Update: This event is locally detected by the sensors (at the node level) when the aggregation of elementary sensor measurements (accelerometer, gyroscope orientation, etc.) reveal that the user is moving out of the cell region or when a beacon sent by a different base station or AP reveals that the user is in proximity of a novel cell.

3. Measurement 1 power consumption: Measurements about the power consumption are continuously sent to the network controller as input parameters for context estimation.



4. Measurement 2 position estimation: Measurements about position estimation are continuously sent to the network controller. The technology to be used for these estimates is dynamically selected by the controller according to the context estimate.

5. Measurement 3 Number of users estimation: Measurements about weather conditions are sent to the monitoring library which translates them to meaningful information regarding prediction of increased number of users.

6. Enforcement Change PHY/MAC behaviour: Context estimates are used by the network controller not only for selecting the best positioning system, but mainly for configuring the PHY/MAC of the wireless nodes. Examples of this configuration are the tuning of the contention windows for mitigating the channel capture effects, the tuning of the LTE schedules for improving the coexistence with WiFi in unlicensed bands or implementing more LTE functions in SW rather than HW, in order to reduce energy consumption.

Table 10-3. The KPIs that PoC 8 targets. KPI

description Relevance to the proof-of concept

Other comments

LAT Reduce overall latency The latency incurred by all components implemented in either in HW or SW, communication between

components and external interfaces NRG Reduce energy

consumption The energy consumption of the selected HW

components FVR Improve flexibility The degree of reusability of the selected HW/SW

mixed model ISF Reduce

footprint/Computational capacity

As some computational tasks are offloaded to sensors, the overall SW memory utilization on 5G

nodes can be reduced 10.3.2 Elementary test 1: Adaptation Mechanisms in WiFi – LTE-U co-existence Scenario

PoC 8 provides a set of experiments devised to: i) evaluate the effects of cross-technology interference between coexisting WiFi and LTE-U networks (baseline scenario), and ii) demonstrate the effectiveness of different coexistence strategies based on the characterization of the predictable interference patterns generated by LTE-U links. More into details, it is planned to consider the possibility to dynamically tune the WiFi bandwidth and the central frequency for avoiding the interference with LTE links (frequency dimension), as well as the possibility to introduce some forms of cross-technology TDMA, in which the time intervals allocated to each technology are chosen as a function of the relevant traffic. 10.3.2.1 Testbed setup specification

For these experiments, testbed includes: 1. LTE-U-eNB, LTE-U-UE, used for implementing the LTE links with the possibility of

using blank sub frames. 2. 2 IEEE 802.11 WMP-enabled nodes, used for implementing the WiFi links with

programmable MAC rules and advanced MAC/PHY reconfigurations based on the monitoring of low-level PHY measurements and statistics;

3. Network controller Server, used for aggregating the context information provided by all the WiFi/LTE wireless nodes, and deciding about the optimal configuration of the coexistence mechanism.



OBJECTIVE To investigate the reconfiguration of LTE-U access period and WiFi MAC scheme in order to mitigate cross-technology interference

INTERFACES Channel Monitoring (Busy time, Packet errors) Environment Monitoring (Proximity sensors, beacon) Dynamic LTE-U access period selection / WiFi MAC and PHY adaptation

Priority TBD later on the test phase

Responsible partners CNIT, UC3M, IMDEA, TST, WINGS


This test is focused on the demonstration of the performance improvements that can be achieved in case of coexistence between WiFi and LTE networks, by implementing a coexistence strategy that can rely on a central controller. The performance will be compared with the baseline scenario in which no coexistence mechanism is deployed, for different traffic scenarios (e.g. low loaded LTE networks, low loaded WiFi networks) and for different orders of traffic flows activations. Two experiments are planned:

• Co-existence #1: In this experiment WiFi and LTE coexistence is improved by working on the allocations (re-allocations) of the central frequency and/or on the tuning of the WiFi transmission bandwidth, in order to make to two coexisting network completely orthogonal (frequency domain coexistence). The Network Server decides if the current frequency planning has to be changed or not, according to the performance experienced by the coexisting networks in terms of throughput, error statistics, and proximity sensors. The decision is performed by taking into account the estimates of the traffic demands in each network and the estimates of the interfering conditions among the network, in terms of central frequency and operating bandwidth for both the technologies. When the reconfiguration message is sent to the WiFi or LTE base stations, the beacon information and the sensors BLE are updated accordingly.

• Co-existence #2: In this scenario, the optimization is based by also considering the time domain, i.e. the activity patterns (if regular) of the traffic experience in both the WiFi and LTE networks. The Network Server can implement some cross-technology coordination mechanisms, based on the allocation of time intervals in which the channel access can be performed by a single technology. For example, WiFi nodes can be configured for avoiding periodically accessing the channel, when the scheduling of LTE frames is expected.

10.3.3 Elementary test 2: Location-based capture effect mitigation

This test deals with the demonstration of context-based optimizations and in particular on the exploitation of positioning information for improving the performance fairness among the nodes. Indeed, it is well known that all cellular networks suffer of problems related to the simultaneous presence of near and far nodes. For WiFi networks, the presence of mobile users in proximity of the AP may largely obstruct the Fresnel zone (affecting the SNR) for farthest nodes. This increases the probability of capture phenomena, i.e. the probability that the AP correctly demodulates the packets sent by close nodes in case of collisions. The phenomenon results in an unfair share of the channel resources, because far nodes increase their contention windows and reduce their channel access, while close nodes experience much lower contention levels.



In order to detect a network scenario in which near/far stations suffer of uneven channel shares, PoC 8 proposes to use proximity sensors embedded in APs for estimating node positions. Specifically, it is possible to simultaneously collect in-band localization information, by exploiting the measurement of propagation delays, and pervasive out-of-band information collected by iBeacons, as well as additional information gathered by inertial sensors (gyroscope, accelerometer), for estimating the network topology and the physical distance among the nodes. The proposal is to configure a specific network topology in which the near/far phenomenon is evident and compare the following cases:

• Baseline: quantification of the unfair allocations of the channel resources, when one near node is coexisting with a far node associated to the same AP.

• Advanced: mitigation of the unfair allocations and optimization of the energy consumptions, by using MAC layer adaptations (e.g. heterogeneous tunings of the contention windows).

10.3.3.1 Testbed setup specification

OBJECTIVE Optimizations for crowded wireless networks with positioning-based reconfigurations of nodes. Mitigation of the capture effects.

INTERFACES Position information provided by BLE beacons, WiFi localization techniques. WiFi MAC adaptation

Priority TBD later on the test phase

Responsible partners CNIT, UC3M, IMDEA, TST, WINGS


The plan is to dispose one or two nodes in close proximity of an AP and one or two nodes at a larger distance, in order to create a scenario with capture phenomena (which typically arise when the AP receives the frame transmitted by near and far nodes with at least 10dB of difference). Typically the RSSI measurement is the first technique adopted to highlight potential captures effect. However, in real scenarios reliable RSSI measurements are not always available and therefore cannot infer about the occurrence of capture effects.

Figure 10-4. Capture effect experiment setup

For this reason there is a need to rely on other information, for example positioning estimates. The plan is to activate the near/far nodes sequentially, demonstrating the capability of identifying capture problems and correct these problems by reconfiguring the contention parameters to give priority to the far nodes.



10.3.4 Elementary test 3: Reconfiguration of an LTE eNodeB network stack

The first tests on network reconfiguration consider measurements of sensors that are processed by the monitoring library, which performs prediction (proactive case) or monitors the evolution (reactive case) of network load “explosion” due to hotspot, and triggers the optimal reconfiguration of an LTE eNodeB network stack. The Dynamic Functional Re-composition module performs a cognitive dynamic HW/SW partitioning, providing the optimal decision on the HW or SW implementation of the eNodeB functions. 10.3.4.1 Testbench setup specification

For these experiments, the developed testbed (Figure 10-5) includes: i) Environmental platform

a. Sensors (temperature, humidity, luminosity) b. Arduino sensor gateways c. Supporting environmental conditions monitoring service

ii) Monitoring agent (software): Gathers measurements from the sensors and performs a first processing/filtering

iii) Monitoring library: Solution for load prediction in time and space iv) Dynamic Functional Re-composition

a. Dynamic HW/SW partitioning i. Dynamic functional partitioning according to KPIs and algorithmic

(optimization problem) solutions ii. Reconfiguration of network deployment and operation according to

context and optimization criteria

Figure 10-5. PoC 8 Test#3 testbed



OBJECTIVE To investigate the reconfiguration of an LTE eNodeB network stack in terms of HW/SW function split.

INTERFACES Monitoring library < Sensors API Dynamic Functional Re-composition<> Monitoring library

Priority TBD on a later testing phase

Responsible partners WINGS (WINGS)


Four main phases can be identified in each of experiments (Figure 10-6).

Figure 10-6. Experimental procedure

1) Monitoring: Measurements from sensors To predict either the network load “explosion” due to hotspot or the network load “evolution” in the hotspot and to trigger the network configuration process

2) Analysis: Indication for a hotspot 3) Decision on network reconfiguration

i) Optimal functional composition (cognitive dynamic partitioning / functional composition / placement)

4) Execution: Enforcement of reconfiguration decision (eNodeB reconfiguration) 10.3.5 Test results

Regarding Tests 1 and 2, expected results correspond basically to the comparison between baseline scenario, which is composed shared traffic transmission of WiFi and LTE-U links and PoC 8 adaptation solutions, and analysing performance improvements. On another side location-based information will be used to reduce capture effect conditions. On Test 3, the results showed LAT reduction close to 1.7ms per function, in terms of execution time, when the function is moved from SW to HW; NRG reduction up to 34mW per function, referring to HW components’ consumption; FVR in terms of reusability, improved by 13% per function, by moving a function from HW to SW, and finally ISF reduction by 57% in terms of SW memory utilization when SW functions are moved to HW.



Table 10-4. Test results


WiFi + LTE-U traffic without adaptation algorithm

Expected Performance degradation

- -

WiFi + LTE-U traffic WITH adaptation algorithm

- - -

Unfair positioned WiFi traffic

Expected Throughput degradation due to capture effect

- -

WiFi position-based MAC adaptation

Expected Performance improvement

- -

LAT - Reduction close to 1.7ms per function, in terms of execution time

Reconfiguration targeting execution time minimization

(1 more function implemented in HW )

From 52.664ms to 50.907ms

NRG - Reduction up to 34mW per function, referring to HW components’ consumption

Reconfiguration targeting energy consumption minimization

(1 more function implemented in SW )

From 41.6mW to 7.68mW

FVR - Improved by 13% per function (in terms of reusability)

(1 more function implemented in SW )

Reusability improvement from 84.098% to 97.064%

ISF - Reduction by 57% in terms of SW memory utilization

(1 more function implemented in HW )

SW memory utilization reduction from 73.168% to

15.769%


PoC 8 has been included in two of the three use cases families described by WP1 in D1.1 [Fle11] document, namely “Broadband access in dense areas”, “Massive IoT”. Inside these high level scenarios, Flex5Gware has also selected particular and more concrete use cases aligned with the project expected contributions. From those particular scenarios, PoC 8 has been included in the following ones:



• Dense Urban --> Dynamic hotspots. PoC 8 can demonstrate how the network configurations can be changed dynamically in response to the variation of the traffic spatial distribution. In particular, it will be possible: i) to activate/deactivate different access points, relay nodes and nodes’ HW/SW components; ii) to allocate extra bandwidth in the hotspots, including non-licensed bandwidth; iii) to estimate the dynamic variability of the hotspot traffic by aggregating the information gathered by the available sensors in order to predict future configurations.

• Broadband Everywhere ->Mobile broadband in vehicles. To support broadband in vehicular environments, when the speed of devices and the additional attenuation constitute notable constrains, the ability to activate and select the most appropriate interface(s), connect to the available resources, and dynamically reconfigure their operation is mandatory to maximize performance. The ability to activate mechanisms such that D2D-based offloading (so one device connects to the macro-cell and acts as relays for the rest of the devices inside a vehicle) or context-aware content dissemination (for e.g. real-time streaming) can lead to substantial improvements in highway or urban scenarios.

• Massive IoT --> Smart Cities. This PoC 8 perfectly fits inside the Smart Cities scenario, in the sense that the proof of concept itself integrates IoT devices. This means both that the traffic generated by those devices should be considered and handled on an optimum way and that data coming from sensors should be used to perform intelligent operations at device level. In particular, from the subset of IoT applications covered on Smart Cities and also mentioned in the definition of the use case at Flex5Gware IR1.1 document, PoC 8 aims at including the following ones:

• Environmental monitoring. The idea behind the use of this sensor data relies on the fact that some of them (i.e. pressure) provide valuable information that can be used for non-environmental applications such as, for instance, indoor location. The final set of variables to detect in PoC 8 will be proposed on a later stage.

• Vehicle and human detection. It is very useful to detect traffic patterns or citizen behaviour in key places along the city so as to be able to early react to congestion situations, as well as for accident prevention/road user’s protection. Roads experiment predictable traffic jams. If the data is properly processed preventive and mitigation actions can be automatically triggered.

• Massive IoTV2X communications for enhanced driving. For the case of V2X communications to support enhanced driving, this PoC is also relevant as in dense or rapidly changing environments a fast reconfiguration of the interfaces is mandatory to promptly select the most efficient communication scheme. In this way, for the case of see-through applications, changes in e.g. relative localization and/or channel quality may trigger the use of a different communication protocol. For the case of automatic driving applications, to achieve the required delivery guarantees the use of e.g. multiple paths might be triggered when abrupt fading is detected.


It is expected that the proposed state-machine based programming model will allow to easily integrating the information collected by the sensors into the device and network control logic. Indeed, it is enough to define an interface between the sensors and the network card in terms of events triggered by the aggregation of different sensor measurements. For example,



an event can be triggered when a parameter monitored by the sensors overcome a given threshold (e.g. a critical level of the device battery) or reaches a specific value and even when multiple conditions are verified on different parameters. Similar considerations may allow integrating some actuators into the intelligent network devices, by exposing the relevant actions to the controllers as extensions of the elementary actions available on the transceivers. As far as concerns the extensions of the transceiver flexibility towards a more advanced MAC/PHY cross-layer reconfigurations, it is expected that a key challenge will be the design of a PHY architecture able to fulfil the flexibility requirements (mainly in terms of bandwidth and central frequency adaptations) while maintaining low reconfiguration latency. 10.6 Time plan and availability

A time schedule for the whole proof of concept is given in Table 10-5. Table 10-5. PoC 8 Time plan.

Component/Task

M6 M12 M18 M24

Application selection

DEFINITION - - -

Radio 1 (commercial NIC)

API EXTENSIONS

FIRST EVALUATION OF ACTION CHAINS

FINAL PROTOTYPE

INTEGRATED

Radio 2 (SDR) DESIGN OF PHY ARCHITECTURE

FIRST EVALUATION OF PHY API

FINAL PROTOTYPE

INTEGRATED

Sensors SELECTION PROTOTYPE FINAL INTEGRATED

Hardware abstraction

- TEST SENSOR API -

Local resource controller DESIGN FIRST

PROTOTYPE / EVALUATION

FINAL PROTOTYPE / INTEGRATION

FINAL INTEGRATION / VALIDATION / DEMONSTRATION

Remote Network controller

DESIGN FIRST PROTOTYPE / EVALUATION

FINAL PROTOTYPE / INTEGRATION

FINAL INTEGRATION / VALIDATION / DEMONSTRATION

D2D-capable devices HW selected

and deployed TEST PROTOTYPE INTEGRATED



11. Flexible, scalable and reconfigurable small cell platform (PoC 9) The goal of this PoC is to assess the viability of 5G reconfigurable base stations based on virtualized technologies. That is, given a radio interface and a general purpose computing element, assess if a platform with multi-tenancy can be provided ensuring that 5G requirements are still met. Signal processing elements or higher level functions/elements, instead of being static, could be deployed as virtual machines - a virtual machine corresponding to a specific function. Given that virtualized environments natively provide security and isolation, multi-tenancy would be an obvious consequence of such platform, enabling the possibility of multiple operators (or MVNOs) sharing the same physical resource while still guaranteeing segregation. Another advantage of virtualization is the easiness of deployment (and thus flexibility and re-configurability). Functions could be deployed on the edge on demand by sending such functions (i.e. virtual machines) from the core to the edge and instantiating them as necessary as well as linking multiple functions together (chaining). In order to provide such infrastructure, multiple parameters should be taken into consideration:

• Instantiation time / deployment time - time to reconfigure the system • Data volume - the communication capabilities between functions • Latency - time constrains might exist

All the characteristics are an indication of the type of applications that can be deployed in the platform: compositions requiring fast reconfiguration time will have a maximum reconfiguration time as threshold); different functions will have different data volume and latency requirements. The latter two also provide a lead on something fundamental: understanding if an SDR only base station is possible or if only higher level functions can be deployed (or a mix of both). Despite the obvious focus on the platform itself, this PoC intends to demonstrate an application built on top of such system: preamble detection as a first step for accurate user location. 11.1 Short description

The main purpose of this PoC is to build a flexible, scalable small cell platform able to allow third parties to deploy localized processing based on raw samples or higher-layer traffic (e.g., TCP/UDP). Localized processing can include a wide range of applications, including accurate mobile user location based on samples (the target of the PoC’s first prototype), edge based content caching, and network services such as ad blocking, firewalling or storage services, to name a few. Because multiple independent tenants might be running processing on the same shared platform, the PoC targets the use of virtualization technologies (either Xen or KVM) as a means to isolate the various types of processing.



Figure 11-1. Overall PoC Architecture.

Figure 11-1 above illustrates the general idea. For this PoC we are using an Ettus Research USRP N210 software radio connected via a 1Gb Ethernet cable to a commodity hardware host. Initially, the host consists of an x86 server, which can either be a configured for a rack server setup, or a single-board PC such as the Intel NUC for deployments where physical space is limited. Alternatively, we are likely to look into using ARM32 single-board PCs (e.g., a Raspberry Pi 2 or Cubietruck) to provide a low energy option.

Figure 11-2. Use case: accurate user location.

Data are transmitted from the USRP N210 to the host over UDP. On the host, the UHD (Universal Hardware Driver), a user-level driver, is in charge of receiving the packets but also of sending control messages to the N210 in order to configure it. Next, we need a multiplexing mechanism to deliver the packets/samples among the potentially multiple virtual machines that are executing processing for the various tenants. The exact mechanism for this is yet to be defined, but we can envision using a software switch (e.g., Open vSwitch, commonly used as the back-end switch for virtualization technologies such as Xen and KVM) to redirect packets to the VMs. If needed, we could further include a module between the UHD driver and the redirection mechanism to rewrite certain packet header fields (e.g., destination port) depending on which VM the packet should go to. Rules in the software switch could then be used for redirecting the packets towards the VMs’ ports on the switch.



To drive the development of the PoC we have chosen to target, as a first virtualized application, accurate user location based on raw samples. Figure 11-2 shows the basic design of this prototype. Once samples arrive, the first challenge is to efficiently detect the preamble. To achieve this, we create windows whose starting point differ by a single sample and assign each subsequent window to a different CPU core in order to parallelize the preamble search (refer to Figure 11-2 above for an illustration of the process). The preamble detection can be done in the host itself or can be developed as yet another virtualized application and so offloaded to a VM. Once the preamble is detected, all subsequent samples, which were up to now kept in a circular buffer, are flushed to a separate VM in charge of running the user location algorithm. This algorithm is developed by CNIT, with whom we are collaborating for this application. Beyond this, we are likely to look into performance optimizations to do with running the processing in specialized or minimalistic virtual machines in order to reduce the application start-up times, memory consumption and overall efficiency. As briefly mentioned, PoC 9 also looks into testing the possibility of an ARM32-based version of this platform, trading off processing power and memory for smaller physical size and lower energy consumption. 11.2 Partners and roles

This is a standalone testbed. NEC activities are summarized in the table below. Table 11-1. PoC 9 partner roles.

Partner Devices Interfaces Role NEC - Ettus Research USRP N210

- x86 server - ARM32 server (e.g., Raspberry Pi 2, Cubietruck) - Virtualization technology (e.g., Xen or KVM)

Interface for installation of virtualized, localized processing.

PoC Leader, developer of base platform.


As described on previous sections, the goal of this PoC is to provide a flexible, scalable small cell platform. The selected KPIs (among the ones proposed on Flex5Gware WP1) for this purpose are described on the following table.

Table 11-2. PoC 9 KPI table. KPI Related Use Case(s) Comment FVR Dynamic hotspots

50+ Mbps

Ability to deploy virtualized processing at the edge whenever needed. Flexibility by multiplexing VMs on shared platform (Cloud model). Possibility of multiple platforms such as low-cost devices (e.g., Intel NUC, ARM32) or high-performance servers.

MDV 50+ Mbps Ability to deploy processing all the way at the edge of the network, satisfying network bandwidth requirements while keeping delay to a minimum.

NRG Dynamic hotspots Ability to run on low-power, ARM32 devices.




The devices used for the PoC are simply:

• A USRP N210 • An x86 server

The devices under testing are the software components/blocks and the software interfaces (i.e. communication between VMs and VMs and the USRP).

Figure 11-3. Components of the device under test.

Table 11-3. KPI relationship to PoC 9. KPI description Relevance to the proof-of concept Comments

FVR The goal is to show the possibility of reconfiguring a base station (through the fast deployment of processing functions)

-

MDV Objective is to show fulfilled high data volume demands while still satisfying latency requirements. For that, both network bandwidth/capacity and communication time must be measured. The numbers should take into account 5G expectations.

-

11.3.2 Elementary test 1: Re-configurability time

Since each VM corresponds to a signal processing function that either increases the system’s processing capabilities (i.e. scale out through multiple cores) or adds another signal processing element, the time to re-configure is directly correlated with the time to start and stop VMs. This test measures that time. 11.3.2.1 Testbench setup specification

OBJECTIVE Measure re-configurability time

INTERFACES Hypervisor, tools to launch VM

Priority Highest priority

Responsible partners NEC




1. Prepare machine (x86 server) a. With hypervisor and host OS (dom0 in case of Xen) b. Verify that tools to launch VMs are in place

2. Measure time to launch a single VM (baseline) 3. Measure time to stop a single VM (baseline) 4. Measure how start/stop time is affected with an increased number of VMs running

concurrently a. This number corresponds to the time to re-configure given a number of

specific signal processing elements running (i.e. VMs) 5. Apply system optimizations (hypervisor, tools, micro-VMs) 6. Measure time to launch and stop the micro-VMs and how it is affected by the number

of simultaneously running elements a. And compare to the baseline numbers

11.3.3 Elementary test 2: network bandwidth-latency correlation

This test consists of network bandwidth and latency measurements. That is, network bandwidth and latency between:

• Radio platform and a virtualized processing element • Different (chained) processing elements

Regarding the latest, both metrics will vary according to the total number of elements involved, which shall also be measured. The obtained numbers will correspond the time (at a given bandwidth) to process samples given a number of processing elements. Finally, the results should be compared to 5G expected numbers. 11.3.3.1 Testbench setup specification

OBJECTIVE Measure bandwidth, latency and their correlation

INTERFACES Ethernet (from USRP to virtualized element), hypervisor communication interfaces (communication between elements)

Priority Medium priority

Responsible partners NEC


1. Prepare machine (x86 server) a. With hypervisor and host OS (dom0 in case of Xen) b. Apply system optimizations (hypervisor, tools, create micro-VMs) c. Verify that tools to launch VMs are in place

2. Prepare USRP a. Verify that UHD driver is working and collecting samples b. Verify that samples are redirected to a VM

3. Measure Bandwidth a. Measure bandwidth from the USRP to a VM b. Measure VM-to-VM bandwidth



c. Measure how bandwidth is affected through service/VM-chaining (i.e. how bandwidth is affected by the number of processing elements)

4. Measure Latency a. Measure time since a packet arrives until it is delivered to a VM b. Measure time between sending a packet from a VM until it is received in other

VM c. Measure how delay is affected through service/VM-chaining (i.e. how delay

increases with the number of processing elements) 5. Correlate the two metrics 6. See how it compares to 5G expectations

11.3.4 Test results

Table 11-4. PoC 9 results.


Re-configurability time

TBD ms - -

VM-to-VM data volume

> 10Gbit/s - -

Latency < 1ms - 5G latency requirements

Linear Scaling nX delay where n is the number of VMs and X the delay of a single VM

- -


In this short section we present how this PoC maps to the use cases defined in WP1. As reference, here are the two use cases that apply to this PoC, along with their KPIs:

• Dynamic hotspots. This PoC provides the ability for third parties to deploy processing on-the-fly, whenever it is needed, and at the right place in the network. The use of fast-booting, low-consumption VMs allows for a dynamic platform able to quickly react to increasing and weaning demand.

• 50+ Mbps everywhere. Allowing processing of data right at the edge (e.g., one could envision serving video content directly from this small cell platform) would go a good ways towards achieving high data rates.



A time schedule for the whole proof of concept is given in Table 11-5.



Table 11-5. PoC 9 Time Plan. Component/Task M6 M12 M18 M24 Prototype definition Definition - - -

Preamble detection Definition Preliminary version Final version Integrated

Platform Design / metrics and baselines definition

Baseline values / initial evaluation

Evaluation with preamble

application

Final evaluation / integrated

Demonstration Definition First prototype Final prototype Integrated



12. Flexible resource allocation in CRAN/VRAN platform (PoC 10) UniPI and TI design and evaluate flexible SW solutions in 5G networks for centralized RAN environments, through virtualization of BSs, consisting in, e.g.: baseband unit (BBU) pool allocation algorithms, constrained Remote Radio Head (RRH) activation patterns, energy-efficiency maximization, resource allocation, robustness and reliability, using SoTA optimization techniques to strike the best trade-offs between performance and energy, scale vs. resources. The purpose of this PoC is to analyse the effects of resource allocation algorithms for CRAN/VRAN networks, focusing in particular on advanced CoMP techniques, dynamic RRH activation/deactivation and BBU allocation and association with RRH, as developed in WP5. In a CRAN/VRAN solution, the eNB functionalities are split among two different entities: the Baseband Units (BBU) and the Remote Radio Head (RRH). The BBUs are centralized and each BBU can control more than 1 RRH. The RRHs are deployed in the cell sites and their connection to the BBU is called Fronthaul (FH). The scenario of application of this PoC is shown in the following figure: the Macro cells sites are placed considering a hexagonal grid assuming the presence of three sectors per site; two Micro cells per Macro sector have been considered. There are some CRAN/VRAN servers used for the BBU allocation and each BBU controls several RRHs (Micro and Macro).

Figure 12-1. Hexagonal cell with Macro and Micro layer.

The Micro layer has been inserted within the Macro layer to offload the traffic from the Macro cells with the goal to obtain an improved user experience. The introduction of the CRAN/VRAN allows managing the interference among Micro and Macro using CoMP techniques and also introducing the possibility to switch on/off some cells that are not fully used during a part of the day/month. These two capabilities introduce an improvement of cell/edge throughput and energy consumption. This PoC focuses mainly on these two aspects; the realization of the PoC scenario is better explained below. 12.1 Short description

The goal of this PoC is to test flexible solutions in 5G networks for centralized RAN environments, through virtualization of BSs split in baseband unit (BBU) and Remote Radio Head (RRH);



The envisaged outcomes are laboratory test results and prototype realization showing the intelligent programs implemented. In particular they focus on advanced CoMP techniques, dynamic RRH activation/deactivation and BBU allocation and association with RRH, as developed in WP5;

Figure 12-2. Elements involved within the PoC.

The General Purpose PC (GPP) coordinates Macro and Micro layers to obtain the above mentioned goals: reduce the Micro/Macro interference and improve the energy efficiency by switching off some USRP boards (representing the RRHs) when they are not useful. 12.2 Partners and roles

PoC 10 aims at testing in 4G/5G HW/SW prototypes, connected together through real equipment, following the work and output of WP5. For this purpose, OAI platform is being used as a starting point and extended where/if needed. The following table summarizes the devices/interfaces and roles of each partner in this PoC.

Table 12-1. PoC 10 partner roles. Partner Devices Interfaces Role TI • Ettus USRP

B210 • Commercial dongle/smartphone

Provide Intelligent Program using OAI software.

PoC Leader. HW provider. Provide guidelines for the design, host the demo. Main effort on testing of the platform.

UNIPI • Ettus USRP B210 • Commercial dongle/smartphone

Provide Intelligent Program using OAI software.

HW provider. SW design and implementation (and providing support for the testing).


The tests contained in this section are based on the first year of implementation, and after the finalization of this phase D6.2 deliverable will contain an updated version of specific tests performed for this Proof-of-concept. Goals of the present PoC 10 are:

• Flexible CoMP-Coordinated Scheduling used to obtain the RBs allocation map; • Flexible Activation/Deactivation used to switch on/off the USRP board.



The entire KPIs list is defined within WP1; therefore the KPIs considered for the present PoC 10 are a sub-set of them. In particular some KPIs are specialized in order to have measurable KPI. Draft list of KPIs at PoC level.

Table 12-2. PoC 10 KPI table. KPI Related Use Case(s) Comment Energy Consumption (NRG)

Dynamic Hotspots

50+ Mbps Everywhere

% of Energy saving in comparison with the solution where all the hotspots are transmitting.

User data rate (UDR)

Dynamic Hotspots

50+ Mbps Everywhere

User/cell Throughput (comparison with and without CoMP technique).

Flexibility, versatility, re-configurability (FVR)

Dynamic Hotspots

50+ Mbps Everywhere

Time requested to adapt the system to a change of network configuration (switch on/off of one or more cells and reallocation of the resources).


The devices used for this PoC are:

• Server • Laptop • LTE USB dongle • Shielded Box • Ettus B210: used to perform the Remote Radio Head (RRH) of the eNB.

Figure 12-3. Ettus B210.

The overall connections among all the elements have been depicted in the following figure:

Figure 12-4. Overall connections.



In particular the PoC shows a Macro cell and two Micro cells recreated by means of three Ettus B210 platforms. An additional B210 is used to emulate the surrounding intercell interference. The commercial LTE dongles act as UEs, and are connected to the Macro or to one of the Micros. Therefore the recreated scenario is the following:

Figure 12-5. General Test Scenario (1 macro cell and 2 micro cells).

UE 3 could be connected to the Macro or to the Micro depending on its position. Going deeper within the shielded box, the USB dongles are wired connected to the B210 in order to ensure a stable connection. On the contrary the interferer uses antennas and this ensures that all the USB dongles receive it; indeed even if the LTE dongles are wired connected they can listen the signal by means of their antennas. The wiring diagram is the following:

Figure 12-6. Wiring diagram.

Several tests will be done in order to show that the proposed algorithms match the KPIs analysed in Table 12-2. In the table below the KPIs and the relevance for the PoC are analysed:

Table 12-3. KPI relationship to PoC 10. KPI Relevance to the proof-of concept Other comments

NRG The PoC shows in small scale the energy saving achievable through the switching off of a small cell when it is unused.

EE (Energy Efficiency) is defined according to [EAR12]

UDR The PoC shows in small scale the Downlink (DL) throughput improvement for the cell edge users enabling a CoMP algorithm.

-

FVR The PoC shows in small scale the possibility to reconfigure the network. The time for the reconfiguration is considered.

This test is closely linked to the energy consumption tests.



12.3.2 Elementary test 1: assessing the energy efficiency

Goal of this test is the demonstration of the energy efficiency reachable thanks to the algorithm designed and implemented in WP5 [Fle51]. This algorithm ensures to disable a cell if it has no UE to serve or if the number of UEs attached to it is lower than a threshold. Obviously, in the second case the UEs should be able to attach to another eNB. On the other hand, when the traffic is increased, sleeping cells are switched off again. In particular a number of test repetitions, all identical but with different traffic setup (identifying different periods of the day), will be done. For each test instantiation, a (limited) number of terminals are producing a predetermined amount of traffic. In each scenario and traffic condition, two elementary measurements are performed:

• Power consumption PBASELINE (measured without WP5 algorithms activated)

• Power consumption PFRONTLINE (measured without WP5 algorithms activated) Comparing Baseline and Frontline, the EE gain is calculated as the relative difference. A possible offered traffic could be taken by EU project EARTH [Ear23]

Figure 12-7. Offered traffic.


For the Energy Efficiency (EE) evaluation a HW device and a SW toolkit will be used:

• Current clamp (hardware), used to measure the power consumption;

Figure 12-8. Current clamp.

• XCAL (software), used to monitor some LTE KPI concerning the different LTE dongles.



OBJECTIVE Measure the Ettus B210 power consumption in different scenario and with WP5 algorithm disabled (BASELINE) and enabled (FRONTLINE).

INTERFACES Ettus B210

Priority High priority test

Responsible partners TI/UNIPI


The energy efficiency test starts analyzing the normal LTE network behaviour. We call this setup as BASELINE (because it gives the baseline performances for the comparison).

Figure 12-9. Step1.

Figure 12-10. Step 2a.

Figure 12-11. Step 2b.

The test procedure is described as follows:

Step 1Preconditions:

:

TI/UNIPi WP5 energy efficiency algorithms disabled 1 UE per eNB as in the figure All the UE with UL/DL traffic

Test: Measure the eNBs total power consumption by means of a Current Clamp

Step 2a (Option with mobility of UE3)Preconditions:

:

TI/UNIPi WP5 energy efficiency algorithms disabled 2 UEs attached to the Macro eNB and 1 UE attached in a Micro eNB All the UE with UL/DL traffic


Step 2b (Option with UE 3 switched off)Preconditions:

:

TI/UNIPi WP5 energy efficiency algorithms disabled 1 UE attached to the Macro eNB and 1 UE attached in a Micro eNB All the UE with UL/DL traffic


It will be probably chosen just one realization of step 2 (2a or 2b).



Once the BASELINE tests are performed, the WP5 algorithm will be enabled and the FRONTLINE tests will be performed.

Figure 12-12. Step 3.

Figure 12-13. Step 4a.

Figure 12-14. Step 4b.

The needed steps in this case are presented below:


:

TI/UNIPi WP5 energy efficiency algorithms enabled 1 UE per eNB as in the figure All the UE with UL/DL traffic


Step 4aPreconditions:

:

TI/UNIPi WP5 energy efficiency algorithms enabled 2 UEs attached to the Macro eNB and 1 UE attached in a Micro eNB All the UE with UL/DL traffic


Step 4bPreconditions:

:

TI/UNIPi WP5 energy efficiency algorithms enabled 1 UE attached to the Macro eNB and 1 UE attached in a Micro eNB All the UE with UL/DL traffic


The selection of step 4a or 4b will be done on the basis of the choice made among 2a or 2b. Once both tests are finalized, a comparison of power consumption measured in Steps 1/2/3/4 will be made.

• Steps 1/2/3 show the same power consumption;

The expected output for this test is:

• Step 4 show a power saving due to the eNB deactivation

• According to E3F methodology in EARTH project, overall saving is evaluated by considering different periods of the day, e.g. by using EARTH daily traffic profile.



• As a consequence, this test is repeated several times, according to different traffic loads in the system (and corresponding to different hours in the day).

12.3.3 Elementary test 2: assessing the user data rate improvement

Goal of this test is the analysis of the system behaviour obtained by enabling the CoMP-Coordinated Scheduling realized in WP5. The CoMP algorithm is realized by means of a coordinator that receives information by the single nodes connected to it and averaging them, it is able to get a long-term perspective, and allocates a number of RBs to each coordinated node with the goal to reduce the inter-cell interference. The coordinator (Global Scheduler) communicates its result to the coordinated nodes (Local Scheduler) in the form of a mask. Figure 12-15 shows the High-level architecture of the CoMP scheme. In particular several tests will be done in order to underline the differences with and without the CoMP. In particular, cell edge UE will be considered with different traffic conditions.

Figure 12-15. High-level architecture and interfaces.

In each scenario and traffic condition, two elementary measurements are performed:

• LTE KPIBASELINE (measured without WP5 algorithms activated)

• LTE KPIFRONTLINE (measured with WP5 algorithms activated) Then, the user data rate improvement is calculated by relative difference. 12.3.3.1 Testbench setup specification

For the user data rate improvement evaluation software and hardware toolkits will be used:

• IPERF (software), used to monitor and record the DL throughput of all the UEs; • XCAL (software), used to monitor some LTE KPI concerning the different LTE dongles.

Monitored DL LTE KPIs: o Throughput o CQI o MCS



o Number of used Resource Blocks (RBs) • Spectrum Analyzer (hardware) with LTE capabilities used to check the DL RBs used.

OBJECTIVE Measure the DL throughput improvement for the cell edge UEs obtained when the CoMP algorithm is enabled (FRONTLINE) compared with the BASELINE (CoMP disabled).

INTERFACES Ettus B210 Priority High priority test



The CoMP tests start analyzing the normal LTE network behaviour. We call this phase as BASELINE. Also for these tests the scenario under analysis is the one showed in Figure 12-5 (1 macro and 2 micros with 1 UE per cell) and it is realized by means of the wiring showed in Figure 12-6. The first step needed for the realization of these tests is the overall system setup. System Setup A (@ 5 Mbps) • TI/UNIPi CoMP WP5 algorithms disabled • 1 UE per eNB as in Figure 12-16 • All the UEs with full DL traffic • Change the attenuations showed within the wiring diagram of Figure 12-6 in order to

obtain that UE2 and UE3 reach almost 5 Mbps of throughput. With this procedure we define UE2 and UE3 as cell edge users; indeed they have to be attached to the micros, but due to the macro interference they are not able to reach the maximum throughput.

• The Attenuation values defined in the following steps remain always the same.

Figure 12-16. System Setup A.

Step A.1Preconditions:

: BASELINE

TI/UNIPi CoMP WP5 algorithms disabled 1 UE per eNB as in Figure 12-16 All the UEs with full DL traffic

Test: Measure the UEs throughput by means of Iperf tool Verify the UE2 used RB by means of the spectrum analyzer Measure the above mentioned KPIs of the UE2 by means of XCAL monitoring tool.



Step A.2Preconditions:

: FRONTLINE

TI/UNIPi CoMP WP5 algorithms enabled 1 UE per eNB as in Figure 12-16 All the UEs with full DL traffic


System Setup B (@ 10 Mbps) • TI/UNIPi CoMP WP5 algorithms disabled • 1 UE per eNB as in Figure 12-16 • All the UEs with full DL traffic • Change the attenuations showed in Figure 12-6 in order to obtain that UE2 and UE3

reach almost 10 Mbps of throughput. With this procedure we define UE2 and UE3 position; they have to be attached to the micros, but due to the macro interference they are not able to reach the maximum throughput.

• The attenuation values defined in the following steps remain always the same.

Figure 12-17. System Setup B.

Step B.1Preconditions:

: BASELINE

TI/UNIPi CoMP WP5 algorithms disabled 1 UE per eNB as in Figure 12-17 All the UEs with full DL traffic




Step B.2Preconditions:

: FRONTLINE

TI/UNIPi CoMP WP5 algorithms enabled 1 UE per eNB as in Figure 12-17 All the UEs with full DL traffic


After the tests a comparison among the tests will be done. In particular test 2a will be compared with 3a and test 2b will be compared with 3b in order to obtain a percentage of variation in test a and a percentage of variation in test b.

• Step 3a should perform better than step 2a;

The Expected Output for this test is:

• Step 3b should perform better than step 2b; • The percentage of variation in test a should be higher than in test b

12.3.4 Elementary test 3: assessing the flexibility

The goal of this test is the demonstration of the flexibility of the system when a change occurs. An example is the switching off/on of a cell. For this test the scenario is the same considered above and represented again in Figure 12-18.

Figure 12-18. Scenario.

Switching off the UE3 the micro where it was connected becomes unused. Therefore it is useful to switch off that micro (Figure 12-19).

Figure 12-19. Network changes.



For this test it is not possible to consider a Baseline, but it could be possible to consider that currently this kind of changes in the network need a human control. In our PoC some network changes are managed by the coordinator that automatically adapts the network. 12.3.4.1 Testbench setup specification

OBJECTIVE Measure the time needed to switch of/on a cell.

INTERFACES Ettus B210

Priority High priority test




: Switch off an unused cell

TI/UNIPi WP5 energy efficiency algorithms enabled 1 UE per eNB as in Figure 12-18 All the UE with UL/DL traffic

Test: Switch off the UE3 and measure the time needed by the coordinator to switch off the micro where the UE3 was attached.


: Switch on a cell

TI/UNIPi WP5 energy efficiency algorithms disabled 1 UE per eNB as in Figure 12-19 (1 macro and 1 micro) All the UE with UL/DL traffic

Test: Measure the time needed by the coordinator to switch on the micro.

The coordinator automatically adapts the network topology after changes of UEs deployment.

The Expected Output for this test is:

12.3.5 Test results

This section summarizes all the results obtained during the test phase. 12.3.5.1 Test1: assessing the energy efficiency

Table 12-4. PoC 10 Test 1 Results.


Step 1 See expected results in section 12.3.2.2

- Energy consumption will be measured

Step 2a or 2b See expected results in section 12.3.2.2


Step 3 See expected results - Energy consumption will be measured



in section 12.3.2.2

Step 4a or 4b See expected results in section 12.3.2.2


12.3.5.2 Test2: assessing the user data rate improvement



Step A.1 See expected results in section 12.3.2.2

- Throughput [Mbps], CQI, Used RB, MCS will be measured

Step A.2 See expected results in section 12.3.2.2


Step B.1 See expected results in section 12.3.2.2


Step B.2 See expected results in section 12.3.2.2


12.3.5.3 Test3: assessing the flexibility




- Reconfiguration time will be measured


- Reconfiguration time will be measured


PoC 10 has been included within the use case families:

• Broadband Access in Dense Areas and in particular to the use case Dynamic Hotspots; • Broadband Access Everywhere and in particular to the use case 50+ Mbps Everywhere. These use cases have been described by WP1 in D1.1 document (Use cases and scenarios for 5G systems) [Fle11].

• Dynamic Hotspots. The hotspot is defined as a region of the coverage area where there is a requested network capacity higher than the average network capacity requested in the entire network. Usually the hotspots are densely populated only for a limited period of the day/month, while in the rest of the day/month the requested capacity is similar to the majority of the urban locations. The PoC scenario consists of two Micro layers per Macro layer that are useful to offload the traffic increasing the network capacity. In particular the PoC shows only a part of the entire network (1 Macro and 2 Micro), while the adjacent cells interference is simulated.



The PoC shows the availability to manage the hotspot by means of advanced CoMP techniques and dynamic RRH activation/deactivation.

• 50+ Mbps Everywhere. 50 Mbps refer to the minimum guaranteed throughput everywhere available for the users. In particular this value has to be considered as the minimum user data rate and not a single user’s theoretical peak rate. Also flexible, energy and cost efficient solutions should be considered in order to guarantee the minimum target value in suburban and rural areas. To achieve these ambitious goal it become important the ability to accurately estimate network conditions and dynamically adapt to them. Therefore the above mentioned techniques (advanced CoMP techniques and dynamic RRH activation/deactivation) could be considered for this use case.


The overall tests presented in this document are relative to a small scale prototype demonstrator, and thus the related results can show just in small scale the desired network behaviour introduced by the coordinator. Indeed, it is complex to recreate a large scale deployment that could better approximate the real network deployed. Also the number of contemporary UEs in the macro is small compared to the real case. Nevertheless, more general evaluations will be performed in WP1, in order to derive useful insights also suitable for higher deployment scales. In any case, the goal of the present tests is to show the improvements given by the coordinator in terms of cell-edge throughput, energy efficiency and flexibility. 12.6 Time plan and availability

A time schedule for the whole proof of concept is given in Table 12-7. Table 12-7. PoC 10 time plan.

Component / Task

M6 M12 M18 M24

Testbed Definition of the testbed in TIM labs PoC integrated

and ready Demonstration in

final event

Starting purchasing process Server acquired - -

Software integration

Starting SW integration in TIM

server

First porting of WP5 algorithm

Final WP5 algorithm ready (possible fine tuning)

Procedures Definition of testing assumptions -

Refinement of testing

assumptions -

Tests - First preliminary evaluations - Final evaluations



13. Multi-Chain MIMO Transmitter (PoC 11) Massive MIMO is a key candidate for addressing the rising demand of mobile data volume in an economic and efficient way for 5G mobile systems and beyond. Massive MIMO especially shines in rich scattering environments with a high number of users per area, e.g. crowded venues. However, the Massive MIMO concept relies on massive numbers of active transceivers to exploit the diversity of the channel. The simplest solution is to implement as many of the state-of-the-art RF transceiver chains as independent controlled RF outputs are required. This increases size and costs linearly with the number of outputs. This approach is benefiting from the fact that RF transceiver chip manufacturers already have products with more than one TRX in a single chip for which higher integration is planned. Nevertheless, an economic single chip solution for massive numbers of transceivers using conventional RF circuitry is unlikely in the “low band” (below 6GHz carrier frequency). However, duplication and parallelization is not a problem in the digital domain. This is a huge motivation for an all-digital transmitter: generating the RF signal in digital processing unit by purely digital means. Such a device could provide a high number of RF signals by utilizing the digital I/Os as RF outputs. Even though digital transmitter concepts are already published, they lack of providing the required performance and/or are too complex to be implemented effectively. The key performance indicators are signal quality (i.e. ACLR (Adjacent Channel Leakage Ratio) and EVM (Error vector magnitude)), coding efficiency (ratio of wanted to unwanted output power) and the implementation effort. The goal of this PoC is to demonstrate a feasible all-digital transmitter approach at small scale with 8 transmit branches. Based on the measurement results, the all-digital Massive MIMO transmitter architecture is evaluated. 13.1 Short description

For proving compact solutions for the implementation of MIMO base stations, a setup using a compact multi-chain transmitter enabling multiple RF signal generation is considered. It enables the generation of 8 or more RF signals in one single device. Only one of these chains is connected to a power amplifier (PA) for the sake of reducing the complexity of the test setup. The PA is optimized for MIMO applications and the maximum output power in the range of 1W meets the requirements for transceivers with tens of antennas, typical for massive MIMO applications. The PA connected to one output of the compact multi-chain transmitter allows testing one complete transmit path, while the additional (e.g. 7) not connected transmitter outputs allow to test its multi-chain capability. In a real system each transceiver output has to be connected to an individual PA. The signal carrier of ≥5 MHz bandwidth is placed between 3.4 and 3.8GHz, the range should be covered by the PA. These building blocks for multi-chain RF signal generation and amplification support the realization of massive MIMO base stations by integrating them multiple times to feed the envisaged number of antennas.



Figure 13-1. Block diagram of a multi-chain transmitter test setup.

The setup demonstrates the feasibility of a compact solution for key building blocks of MIMO or massive MIMO base stations with the benefit of decreased size and costs for hardware implementation. 13.2 Partners and roles


Table 13-1. PoC 11 partner roles. Partner Devices Interfaces Role ALUD Low power compact

multi-chain transmitter Frequency band, power range and signal quality at the interface

PoC Leader; HW provider Evaluation of the multi-chain performance; Evaluation of a the single transmit chain

F-IAF PA module Frequency band, power range and signal quality at the interface

HW provider; Evaluation of the PA module


The PoC setup shown in Figure 13-1 allows to evaluate the MIMO capabilities of the multi-chain transmitter for base station transceivers. This solution supports the use cases Crowded venues, Dynamic hotspots and 50+ Mbps everywhere by supporting a more cost efficient MIMO usage. The listed KPIs are based on performance parameters of the setup which determine the MIMO performance.

Table 13-2. PoC 11 KPI table. KPI Related Use Case(s) Comments NRG Dynamic hotspots

50+ Mbps everywhere Reduced power consumption due to a reduced number of components by using a compact multi chain transmitter

Low power compact

multi-chain transmitter

PC(Matlab)

.

.

.

.

PA

Multi-chainRF signal generation

Amplification

Spectrum-analyzer



MDV Crowded Venues Dynamic hotspots 50+ Mbps everywhere

To be derived for massive MIMO operation by considering 5 to 20 MHz BW, 3.5GHz carrier frequency, 30 dBm power level per antenna and an array of 32 to 128 antennas.

NoU Crowded Venues Dynamic hotspots

To be derived for massive MIMO operation by considering 5 to 20 MHz BW, 3.5GHz carrier frequency, 30 dBm power level per antenna and an array of 32 to 128 antennas.


The device to be tested is a multi-chain transmitter for base stations (Figure 13-2) consisting of a multi-chain RF signal generation component (the low power multi-chain transmitter) and a power amplifier. The low power transmitter component uses a standard-compliant baseband signal as the input. A set of complex weights may be applied to the input signal and converted to an RF output signal. By these means beam forming may be applied. The PA provides the power level required at the antenna within the frequency range 3.4 to 3.8GHz and shows restricted volume and power dissipation suitable for multi-antenna systems. Its realization on GaN-on-Si assures competitive fabrication costs.

Figure 13-2. Block diagram of a multi-chain transmitter.

The test is split into three parts: 1) testing the RF signal generation, 2) testing the PA performance, and 3) testing the system performance based on a single RF signal generation chain combined with the dedicated PA. 13.3.2 Elementary test 1: assessing the multi-chain RF signal generation 13.3.2.1 Test bench setup specification

An LTE test signal will be either provided by a signal source or locally stored in the low power multi-chain transmitter. The signal is converted to multiple RF signals. The RF outputs are connected via SMA cables to different measurement instruments, e.g. spectrum analyzer, oscilloscope, power meter, to obtain the key performance criteria for mobile communication transceivers, e.g. power level, EVM, ACLR, wide band noise emissions.

Objective Test of the multi-chain RF signal generation

Interfaces Computer, DC source, spectrum analyser

Priority High





This signal is standard-compliant so that all relevant measures can be taken and compared with the requirements. The chains are measured individually and combined. Moreover, measurements over the air are carried out. Also, the impact of multiple RF signal generation chains being enabled at the same time is investigated, e.g. signal quality distortion and cross-talk. The aim of the tests is to prove the multi-antenna and MIMO capability based on the performance parameters defined in Table 13-2. The number of transmit chains supported by the low power compact multi-chain transmitter is to be tested directly at the component output. 13.3.3 Elementary test 2: assessing the PA performance

In this test the PA is evaluated as a stand-alone part. 13.3.3.1 Test bench setup specification

The PA is connected to a CW signal generator. The output is measured using a spectrum analyzer. The power supplies are monitored to measure the applied voltage and current.


Based on the setup a single and two tone test is carried out. Over the specified frequency range, the output power, input power and power consumption is measured. By these means the gain and power added efficiency is measured over the supported BW. In a second step the linearity of the PA is measured over varying input power. This is done by applying two tones at the input and calculating the IMD3 (Inter Modulation Distortion from the third order of a circuit). 13.3.4 Elementary test 3: assessing the system performance

In this test a PA is attached to one of the RF outputs of the multi-chain transmitter. The signal quality and PA efficiency based on a modulated input signal is determined. 13.3.4.1 Test bench setup specification

The PA is connected via SMA cables to a single RF signal generation chain. An additional conventional driver amplifier might be used depending on the gain and input requirements of the PA. Based on test 13.3.2 and the measurement of the PA output, the performance of the PA can be characterized. The gain and efficiency of the amplifier are key figures, but also the added distortion and the usable frequency range are evaluated.

Objective Performance test of one transmit chain Interfaces Computer, DC source, spectrum analyser

Priority High


Objective Test of the PA performance

Interfaces Signal generator, DC source, spectrum analyser Priority High

Responsible partners F-IAF




The PA is connected to one signal generation chain and its output is measured with different measurement instruments, e.g. spectrum analyzer, oscilloscope, power meter. Furthermore, the power consumption is measured to calculate the efficiency of the PA stage. 13.3.5 Tests results

The test results are split into three parts based on the three tests described before. Test 1 The base line for multi-chain RF signal generation is a solution where only one signal chain is active within one digital component. The key challenge for the low power compact multi-chain transmitter is to meet the ACLR specifications with a very low output amplitude resolution. Typically, low resolution leads to low SNR. Advanced signal processing is applied to compensate for that.

Table 13-3. PoC 11 test 1 results. Requirements Expected results Observed results Comment Number of transmit chains ≥ 8 - -

Operating signal bandwidth ≥ 5 MHz - -

Average output power ~ -10 dBm - -

Coding efficiency > 20% - -

ACLR < -45 dB - -

The number of minimum 8 chains expected to be implemented in a single digital component, which leads to significant reduction on number of components used for multi-chain transmitters with the related potential on cost and volume reduction. Furthermore, the power consumption is decreased compared to the conventional case using separate analogue transmitter chains. State-of-the-art solutions only support carrier frequencies up to about 5GHz as they are limited by the local oscillator frequency. In contrast, the low-power multi-chain transmitter derives the carrier frequency digitally. Consequently, the carrier frequency is only limited by the Nyquist criteria. I.e., an output bit rate of 24Gbit/s implies a maximum carrier frequency of 12GHz. Test 2 Conventional amplifiers considered for similar applications are realized in semiconductor technologies based on GaN-on-SiC or GaAs. The realization of the PA as MMIC on GaN-on-Si provides a technology with significantly decreased manufacturing cost of the semiconductor device. The feasibility of the envisaged device is to be proven on GaN on SiC by the experimental characterization of the parameters listed in the table below, and will be compared to the performance on GaN on Si. As memory effects will play a critical role for the linearity of the chip setup, the comparison will be helpful. As no pre-distortion is applied, a simplified architecture could be considered by not implementing a feed-back path for monitoring the quality of the output signal. This leads to volume reduction, which is beneficial for designing multi-antenna systems.



Table 13-4. PoC 11 Results of test 2 results. Target values Measured values Frequency Range 3.4 – 3.8GHz -

IMD3 ≥ 35 dB -

Peak output power (CW) ~ 40 dBm -

Drain Efficiency (CW) 40-50% -

Test 3 A transmit chain, usually contains a digital front-end followed by components for data and frequency conversion and amplifiers and includes a feedback path, if pre-distortion is implemented. One transmit chain of the proposed multi-chain transmitter contains only one part of the low power multi-chain transmitter (e.g. 1/8 part, if 8 chains are included) followed by an amplifier module. At output power level of around 30 dBm average, the spectrum emission specification (ACLR < -45 dBc) and an acceptable power added efficiency (PAE) must be met.

Table 13-5. PoC 11 test 3 results. Requirements Expected results Observed results Comment Center frequency 3.5GHz

Average output power ~ 30 dBm - -

PA Power added efficiency

> 40%Max. for ACLR of -45 dBc

- -

ACLR < -45 dBc - -

Test 3 proves the feasibility of the proposed multi-chain transmitter concept. 13.4 Use case mapping

The setup includes key building blocks for MIMO transmitters to be realized in a more cost efficient and compact way. These improvements in integration and size are based on a reduced number of components required for implementation leading to improvements on energy efficiency. By duplicating the HW implementation a significantly increased number of transmit-chains can be supported, enabling massive MIMO operation with the benefit on mobile data volume and number of connected users. The multi-chain MIMO transmitter supports the use cases Crowded Venues, Dynamic hotspots, and 50+ Mbps Everywhere by supporting a more cost efficient MIMO usage with the benefit on increased data rate for a higher number of users. 13.5 Additional considerations

The test setup is composed of two main building blocks, the low power multi-chain transmitter and the PA. They are based on concepts elaborated within activities to mixed-



signal solutions and to RF front-ends. A joint specification of the building blocks assures the definition of the test setup of a multi-chain transmitter. Both main building blocks are developed individually and characterized on component level. Afterwards they are interconnected and build the test setup for the proof of concepts used for performance evaluation and demonstration. The low power multi-chain transmitter has been implemented for 8 transmit chains and provides promising intermediate results. The linear PA is based on a new semiconductor technology (GaN-on-Si) and requires at first some technology evaluation as basis for the MMIC (Monolithic Microwave Integrated Circuits) design. 13.6 Time plan and availability

The definition of the proof of concept and the included building blocks stays at the beginning of the work. The design and realization of the multi-chain RF signal generation in the low power transmitter and the linear PA is done individually, followed by an integration of these building blocks. The evaluation and demonstration of the multi-chain transmitter completes the work. A time schedule for the whole proof of concept is given in Table 13-6.

Table 13-6. PoC 11 time plan. Component/Task M6 M12 M18 M24 Low power multi-chain transmitter

Preliminary definition

Specification; implementation defined; preliminary performance results

Setup for multi-chain signal generation; performance results

-

PA module Preliminary definition

Specification, module design

Prototype Performance evaluation

PoC setup Preliminary definition

Final definition of PoC setup and evaluation methodology

- Integration, algorithm implementation, performance evaluation

PoC demonstration

- - - Demo setup.



14. Conclusions Eleven PoC demonstrators are being developed as part of the Flex5Gware project. These demonstrators address the needs of representative application use cases and aim to improve on critical KPIs which will allow the transition from 4G to 5G systems. This deliverable presented the description of each of the PoCs, serving as reference for later Flex5Gware technical deliverables. The selected PoC demonstrators cover a wide range of emerging topics, which include 5G system hardware with operating frequencies both below 6GHz as well as in the millimetre wave range, integrated circuit (IC) design and hybrid hardware platforms integrating baseband electronics and microwave and mmWave circuits, and which address multi-band, multi-antenna (MIMO) and full duplex system concepts and finally, reconfigurable radio and resource allocation algorithms for virtual RAN prototype. The results of the various demonstrators aim to advance the state-of-the-art in their respective KPIs and serve as the basis for the widespread application of 5G systems. The last step on demonstrator activities will be reflected on both the final WP6 deliverable (D6.2) and the final Flex5Gware demo (D6.3), expected both at the end of the project. These two main outcomes will include the final definition of all PoCs together with the performance evaluation and main results, concluding for each PoC the achieved level of enhancement with respect to the state of the art.



15. References [ADF16] Analog Devices AD-FMCOMMS3 FMC board. Link: Information available at:

https://wiki.analog.com/resources/eval/user-guides/ad-fmcomms3-ebz [Aga13] A. Agah, H.-T. Dabag, B. Hanafi, P.M. Asbeck, J.F.Buckwalter, L.E. Larson,

"Active Millimeter-Wave Phase-Shift Doherty Power Amplifier in 45-nm SOI CMOS," in Solid-State Circuits, IEEE Journal of , vol.48, no.10, pp.2338-2350, Oct. 2013.

[Agr16] A. Agrawal, A. Natarajan, “a Scalable 28GHz Coupled-PLL in 65nm CMOS with Single-Wire Synchronization for Large-Scale 5G mmWave Arrays”, IEEE ISSCC 2016, pp. 38-39

[And15] Anders S. G. Andrae and Tomas Edler, “On Global Electricity Usage of Communication Technology: Trends to 2030”, Challenges 2015, 6, 117-157; doi:10.3390/challe6010117

[Bax04] R.J. Baxley and G.T. Zhou, “Power saving analysis of peak-to-average power ratio reduction in OFDM,” IEEE Trans. Consumer Electronics, vol.50, pp.792-798, Aug. 2004.

[Bax07] R.J. Baxley and G.T.Zhou, “Comparing selected mapping and partial transmit sequence for PAR reduction,” IEEE Trans. Broadcasting, vol. 53, no. 4, pp.797-803, Dec. 2007.

[Bha13] Bharadia, D., McMilin, E. and Katti, S. Full Duplex Radios, 2013 Conference on SIGCOMM, New York, US: ACM, 2013.

[Chi15] Y.-C. Chiang, Y.-H.Chang, “A 60GHz CMOS VCO using a fourth-order resonator”, IEEE MWCL, pp. 609-611, 2015.

[Con12] A.Conte, “Power consumption of base stations,” Trend Plenary Meeting, Ghent, 14-15 Feb. 2012.

[Cor13] Peter Corcoran and Anders S.G. Andrae, "Emerging Trends in Electricity Consumption for Consumer ICT", 2013, available at researchgate.net.

[Cos99] E. Costa, M. Midro and S. Pupolin, “Impact of amplifier nonlinearities on OFDM transmission system performance,” IEEE Comm. Let., vol. 3, pp.37-39, Feb. 1999.

[Ear10] Energy Aware Radio and Network Technologies - EARTH, “Energy efficiency analysis of the reference systems, areas of improvements and target breakdown,” INFSO-ICT-247733 EARTH.Deliverable 2.3. December 2010.

[Ear12] EARTH project (Energy Aware Randio and Network Technologies). FP7 (INFSO-ICT-247733). January 2010 – June 2012.www.ict-earth.euwww.ict-earth.eu

[Ear23] EARTH project deliverable D2.3: “Energy efficiency analysis of the reference systems, areas of improvements and target breakdown”; link: https://bscw.ict-earth.eu/pub/bscw.cgi/d71252/EARTH_WP2_D2.3_v2.pdf

]

[Edl08] T. Edler, “Green Base Stations – How to Minimize CO2 Emission in Operator Networks,” Proc. Bath Base Station Conference, 2008.

[EIN13] The EINS Consortium.Overview of ICT energy consumption (D8.1). Report FP7-2888021. European Network of Excellence in Internet Science. February 2013.

http://www.ict-earth.eu/

http://www.ict-earth.eu/



[ETS03] ETSI TR 102 200 V1.1.1 (2003-07), Methods for Testing and Specification (MTS); UMTS Testing Methodology

[EXT06] EXTREME testbed, CTTC. Link: http://networks.cttc.es/mobile-networks/extreme_testbed/

[Fan99] P.Y.Fan and X.G.Xia, “Block coded modulation for the reduction of the peak to average power ratio in OFDM Systems,” IEEE Trans. Cons. Elect, vol. 45, no. 4, pp.1025-1029, Nov. 1999.

[Fei14] W. Fei, H. Yu, H. Fu, J. Ren, K. S. Yeo, ”Design and analysis of a wide frequency-tuning-range CMOS 60GHz VCO by switching inductor loaded transformer”, IEEE TCAS-I, pp. 699-711, 2014.

[Fle11] Flex5Gware D1.1 – 5G system use cases, scenarios, and requirements break-down, 2015.

[Fle21] Flex5Gware Project, “Deliverable 2.1: Requirements and concepts for the analogue HW in 5G mobile systems”, 2015.

[Fle31] Deliverable D3.1, Mixed-signal strategies for 5G: requirements and concepts, Flex5Gware, H2020 Grant Agreement Number: 671563, December 31, 2015.

[Fle41] Deliverable D4.1, Requirements and concepts for the digital HW in 5G transceivers, Flex5Gware, H2020 Grant Agreement Number: 671563, December 31, 2015.

[Fle51] D5.1 Flex5Gware project deliverable D5.1: “System level architecture specification”; Link:

[Fon15] O. Font-Bach, N. Bartzoudis, A. Pascual-Iserte, M. Payaro, L. Blanco, D. López, M. Molina, “Interference Management in LTE-based HetNets: a Practical Approach”, Transactions on Emerging Telecommunications Technologies (Wiley), Vol. 26, Issue 2, Pages 195-215, February 2015, SN - 2161-3915.

http://www.flex5gware.eu/images/documents/Flex5Gware_D51.pdfhttp://www.Flex5Gware.eu/images/documents/Flex5Gware_D51.pdf

[Goy14] Goyal, S., Liu, P., Panwar, S., DiFazio, R.A., Yang, R., Li, J., and Bala, E., ‘Improving Small Cell Capacity with Common Carrier Full Duplex Radios, IEEE ICC 2014 – Wireless Communications Symposium, Syndey.

[ICT13] ICT footprint Pilot testing on methodologies for energy consumption and carbon footprint of the ICT-sector, final report, a study prepared for the European Commission (Digital Agenda for Europe), DG Communications Networks, Content & Technology, 2013.

[Jai13] H. Jai, B. Chi, L. Kuang, Z. Wang, “A resonant switchable VCO with 47.6-71GHz tuning range based on π-type LC network”, Proceedings of IEEE ASSCC, pp. 321-324, 2013.

[Jon94] A.E.Jones, T.A.Wilkinson and S.K. Barton, “Block coding scheme for reduction of peak-to-average envelope power ratio of multicarrier transmission systems,” IET Elect.Let., vol. 30, no. 8, pp.2098-2099, Dec. 1994.

[Kay15] E. Kaymaksut; P. Reynaert, "Dual-Mode CMOS Doherty LTE Power Amplifier With Symmetric Hybrid Transformer," in Solid-State Circuits, IEEE Journal of , vol.50, no.9, pp.1974-1987, Sept. 2015

[Key12] Key World Energy Statistics. International Energy Agency (2012).

http://www.flex5gware.eu/images/documents/Flex5Gware_D51.pdf

http://www.flex5gware.eu/images/documents/Flex5Gware_D51.pdf



[Len16] LENA LTE Open Source simulator-emulator, CTTC. Link: http://lena.cttc.es/manual/lte-design.html

[Li98] X.Li and L. Cimini, “Effects of clipping and filtering on the performance of OFDM,” IEEE Comm. Let., vol. 2, no. 4, pp. 131-133, May 1998.

[Liu09] B. Liu, W. Hong, Z. Kuai, X. Yin, G. Luo, J. Chen, H. Tang, and K. Wu, Substrate Integrated Waveguide (SIW) Monopulse Slot Antenna Array, Antennas and Propagation, IEEE Transactions on, vol. 57, no. 1, pp.275-279, Jan 2009.

[Mal11] P. Malathi and P.T. Vanathi, “Peak to Average Power ratio (PAPR) Reduction Techniques for OFDM-MIMO System,” International Journal of Computer Science Issues, Special Issue, vol. 1, issue 1, pp.92- 96, Nov. 2011.

[Och00] H. Ochiai and H. Imai, “Performance of the deliberate clipping with adaptive symbol selection for strictly band-limited OFDM systems,” IEEE Journal Select. Areas Comm., vol.18, no. 11, pp.2270-2277, Nov. 2000.

[Qor16] Qorvo, “6 Watt Discrete Power GaN on SiC HEMT”, TGF2023-2-01 datasheet, 2016 [Rev D 01-22-16]

[San14] Sanjay Goyal et al., Improving Small Cell Capacity with Common-Carrier Full Duplex Radios, IEEE ICC 2014 - Wireless Communications Symposium

[Ser12] Serrano, P., la Oliva, A., Patras, P., Mancuso, V., & Banchs, A. (2012). Greening wireless communications: Status and future directions. Computer Communications.

[Sir15] T. Siriburanonet. Al. “A 28-GHz Fractional-N Frequency Synthesizer with Reference and Frequency Doublers for 5G Cellular”, IEEE ESSCIRC 2015, pp. 76-79.

[Tan14] Y. Tang, Z. Wang, L. Xia, and P. Chen, A novel high gain K-band H-plane SIW horn antenna using dielectric loading, in Microwave Conference (APMC), 2014 Asia-Pacific, Nov 2014, pp. 372-374.

[Tell99] J. Tellado, “Peak to Average Power Ratio Reduction for Multicarrier Modulation,” PhD thesis, Stanford University, 1999.

[Wal11] J. L. B. Walker, “Handbook of RF and Microwave Power Amplifiers”, Cambridge University Press, ISBN 0521760100, 2011.

[XIL16] Xilinx Zynq-7000 ZC706. Link: Information available at: http://www.xilinx.com/products/boards-and-kits/ek-z7-zc706-g.html

[Yan06] L. Yang, R.S. Chen, Y.M. Siu and K.K. Soo, “PAPR reduction of an OFDM signal by use of PTS with low computational complexity,” IEEE Trans. Brod. Vol. 52, no. 1, pp.83-86, Mar. 2006.

[Yoo06] S.S. Yoo, S. Yoon, S.Y. Kim and I. Song, “A novel PAPR reduction scheme for OFDM systems: Selective mapping of partial tones,” IEEE Trans. Cons Elect, vol. 52, no. 1, pp.40-43, Feb. 2006.

[Zou95] W.Y. Zou and Y. Wu, “COFDM : An overview,” IEEE Trans. Broadcast., vol. 41, no.1, pp.1-8, Mar. 1995.



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Research and Innovation Action - Flex5Gware and Innovation Action ... use case mapping and related activities time plans. ... Dieter Ferling ALUD [email protected]