Requirements AN946: PCI-Express 4.0 Jitter - Silicon Labs · 1. Clocking Architectures In the application note, "AN562: PCI Express 3.0 Jitter Requirements", there are three different

AN946: PCI-Express 4.0 JitterRequirements

PCI-Express (PCIe) is a point-to-point serial communicationstandard that supports 2.5 GB/s, 5 GB/s, 8 GB/s and 16 GB/s da-ta rates. All of these standards require a 100 MHz ± 300 ppm ref-erence clock (Refclk). Given the evolution and refinement of thesePCIe standards, 4.0 specifically, there has been the addition ofthe 16 GB/s (base 4.0 standard), the removal of separate clock,and expansion of Gen1 and Gen2 transfer functions that createsadditional requirements for the reference clocks to be used in thesystem at all data rates. In particular, the peaking value for 2.5 Gand 5 G data rates has been lowered to 0.01 dB to be in align-ment with the 8 G and 16 G data rates. This specification also in-creases the number of possible filter scenarios for Gen1 (2.5 G)data rates. Currently, this document is based on the PCI-ExpressBase Specification 4.0. Since the generation 4 PCI-Express speci-fications are still pending finalization, this documentation will un-dergo updates as appropriate.

KEY POINTS

• Describes new PCIe Gen 4 Requirements• Demonstrates how to determine the filter

functions to process your data forcompliance

• Provides recommended test setup to makeyour measurements

silabs.com | Building a more connected world. Rev. 0.2

1. Clocking Architectures

In the application note, "AN562: PCI Express 3.0 Jitter Requirements", there are three different clocking architectures supported by pre-vious PCI-express specifications. Each one of these clocking architectures comes with very different jitter filtering characteristics whichwill impact the overall jitter performance of the system. For the PCI-Express 4.0 specification, there are only two types of architecturessupported: Common Refclk (CC) and Independent Refclk.

Common Refclk Rx Architecture

PCIe LinkPCIe

Device A

100 MHz ±300ppm

PCIe Device B

Independent Refclk Rx Architecture

PCIe LinkPCIe

Device A

100 MHz ±300ppm

PCIe Device B

100 MHz ±300ppm

Figure 1.1. Clocking Architectures

AN946: PCI-Express 4.0 Jitter RequirementsClocking Architectures

silabs.com | Building a more connected world. Rev. 0.2 | 2

2. Filters Applied to Data

The PCI-Express specifications have traditionally specified multiple types of filtering to be applied to raw data. For Gen4, two types offiltering are required. The first is edge filtering of the raw data, which minimizes jitter caused by the finite sampling rate of the test equip-ment. This filtering is typically implemented by applying a 5 GHz bandwidth filter to the data. The second type of filtering, which is theprimary topic of this application note, is through the use of PLL difference functions that are inherent in the combination of RX PLL, TXPLL, and CDR that are part of the PCI-Express system. The proper use of these filters will yield the effective Refclk jitter as it appearsat the sample latch of the receiver.

AN946: PCI-Express 4.0 Jitter RequirementsFilters Applied to Data


3. Reference Clock Jitter Requirements

PCI-Express has very strict requirements for bit error rate of the system that is directly impacted by the jitter of the system. This jittercan be in the form of both random and deterministic components that originate from various parts of the system. The most direct andcomplex contributor to the jitter in the system is the Refclk. As such, the PCI-Express standards impose specific performance require-ments on the Refclk to ensure that bit errors in the system are minimized. Because the Refclk can have such a major impact on thesystem, a Refclk with low jitter can easily improve the overall performance of the system.

AN946: PCI-Express 4.0 Jitter RequirementsReference Clock Jitter Requirements


3.1 Gen4 Common Clocked Requirements

In the common clocked architecture, the Refclk is distributed to both the transmitter and receiver of the two PCI-Express devices in thesystem. In this case, the overall transfer function for the Refclk that impacts the amount of jitter appearing at the receiver latch is de-fined by the difference function between the transmitter and receiver PLLs multiplied by the receiver latch high pass characteristic. Thisis further impacted by the transport delay difference between the two inputs to the RX and TX PLLs. Since the delay impacts the trans-fer function, thus affecting the jitter seen by the CDR, the delay should be applied to the TX PLL and the RX PLL transfer functionseparately and the worst case jitter from the two scenarios would be the result.

Figure 3.1. Gen4 Common Clock Requirements

H (s) = (H1(s) �e −s.T − H2(s)) �H3(s) H(s) = (H2(s) �e −s.T − H1(s)) �H3(s)PCI-Express 4.0 has modified the filter scenarios for 2.5 G and 5 G, bringing them in alignment with the minimum 0.01 dB peaking seenin the 8 G and 16 G specifications.



Table 3.1. PLL and CDR Characteristics for All Data Rates Based on the PCI-Express 4.0 Specification

The jitter specifications in the table below continue to be the same values given in past specifications. The most notable difference be-ing that the Gen1 (2.5 GB/s) specification is expressed as a pk-pk value rather than an RMS like the rest of the generations of thespecifications. This is due to the combination of the PLL to CDR bandwidths that exist. In particular with the CDR bandwidth being lowat 1.5 MHz and the PLL bandwidths being equal or higher, then that allows SSC effects to pass through to the CDR as deterministicjitter. So, in that case it makes more sense to specify the jitter in terms of pk-pk rather than RMS.



Table 3.2. Jitter Limits for Common Clock Architecture

Data Rate CC Jitter Limit

2.5 G 108 ps pk-pk

5.0 G 3.1 ps RMS

8.0 G 1.0 ps RMS

16.0 G 0.5 ps RMS

3.2 PCI-Express 4.0 Independent Refclk Requirements

Currently the PCI-Express 4.0 specification does not define the jitter transfer function and jitter limits for the Independent Refclk archi-tecture. Instead, the approach taken is to allow the implementation and associated reference clock jitter and transfer function trade-offsthat impact the overall transmitter jitter to be handled by the implementer. However, to minimize potential issues related to the systemclock, Silicon Labs recommends that the maximum PLL BW and CDR filters be used as outlined in PCI-Express 3.1 specification tofilter the reference clock jitter and that this result be less than the common clock jitter budgets divided by sqrt(2). The reason for dividingthe limit by sqrt(2) is that if both the separate transmit and receive clocks each meet this rms jitter limit, then their combined rms jitter(which adds as the sqrt of the sum of the squares) will be less than the maximum system budget for Refclk jitter listed above.



4. Spread Spectrum Clocking and Bit Rate Tolerance

PCIe devices are specified to reliably transmit data when using a Refclk with a spread spectrum modulation rate of 30–33 kHz andmodulation amplitude of 0 to –0.5% (i.e., downspread 0.5% in reference to the carrier frequency). Because each PCIe device musttransmit within a bit rate of ±300 ppm of each other, the same Refclk must be supplied to both devices if SSC is used. In some systemimplementations, separate clocking architecture will therefore not work if SSC is turned on unless both clocks are synchronized to acommon source. When the system is SRIS capable, the CDRs will be designed with loop filter characteristics such that the SSC can betracked independently by the receiver allowing for SRIS support. Using SSC is possible for the Separate Reflck, Common Clocked RXArchitecture, and Data Clocked RX Architecture. In addition to the SSC modulation rate and modulation amplitude, there is also a re-quirement for the maximum rate of change of the frequency on a Refclk with SSC active at 1250 ppm/µs. Refclks with the SSC activewill need to meet additional phase jitter requirements at low frequency as shown in the table below.

Table 4.1. Limits for Phase Jitter from the Reference Clock with SSC Active

Frequency Maximum Peak-to-Peak Phase Jitter (ps)

30 kHz 25000

100 kHz 1000

500 kHz 25

AN946: PCI-Express 4.0 Jitter RequirementsSpread Spectrum Clocking and Bit Rate Tolerance


5. Refclk Test Setup

The reference clock test setup as defined in the 3.1 specification assumes that only the reference clock generator is present. It takesthe approach of measuring with the worst case system degradation in place using a 12-inch differential trace that is terminated by two 2pF capacitors. GEN 4.0 has refined the specification to a 15 dB loss at 4 GHz and a 2 pF load.

Figure 5.1. Refclk Test Setup

AN946: PCI-Express 4.0 Jitter RequirementsRefclk Test Setup


6. A Typical PCI Express Application

Silicon Labs offers a variety of clock devices that allows for flexible PCIe Refclk distribution. For example, the Si5338 I2C Programma-ble Any-Frequency, Any-Output Quad Clock Generator is an ideal device for generating PCIe clocks:• Compliant with PCI Express 4.0 and legacy standards (2.1, 1.1)• PCI Express 4.0 jitter = 0.12 ps RMS (4x lower than the requirement)• Generates up to four 100 MHz HCSL output clocks but is programmable with other frequencies and signal formats. This allows one

clock device to generate PCIe Refclks and other board clocks of different frequencies and signal formats.• Output frequencies are programmable per output from 5 MHz to 710 MHz.• Independent VDDO for each output clock enables integrated level translation.• Output signal formats are programmable per output as HCSL, LVDS, LVPECL or LVCMOS.• Excellent jitter performance allows Refclk generation for Common Refclk RX, Data Clocked RX, and Separate Clock Architectures.• Spread spectrum can be enabled or disabled per output with programmable modulation rate and modulation amplitude per output.• Built-in HCSL terminations.• Small 4x4 mm package

A typical use of the Si5338 in a PCIe application is shown in the figure below. In this example the Si5338 replaces a 100 MHz clockoscillator with spread spectrum, a 1:2 HCSL buffer, a 66.6667 MHz clock oscillator, and a 125 MHz clock oscillator.

PCIe DeviceCPU

Si5338 Quad Clock Generator66.66 MHzLVCMOS

100 MHz HCSL

25 MHz XTAL

+/- 100ppmOSC

Multi- Synth 0

PLL

Motherboard

PCIe Device

100 MHz HCSL

Add-In Board

Ethernet

125 MHzLVCMOS

Multi- Synth 1

Multi- Synth 2

Multi- Synth 3

Figure 6.1. PCIe Application Using the Si5338 as the Refclk Generator

AN946: PCI-Express 4.0 Jitter RequirementsA Typical PCI Express Application


Appendix 1. PCI Express Compliance Report

AN946: PCI-Express 4.0 Jitter RequirementsPCI Express Compliance Report


Data File Overview

File Type Time Domain Differential

Waveform File C:\tmp\Si5338_SN001_waveform_85C_MinV.bin

Waveform File Creation Date 2017-06-15 15:17:37 GMT-04:00

Edge Filtering On

Clock Frequency 100.001 MHz

Number of Edges 256,252

Sample Interval 50.000 ps

Average Threshold Voltage 0.000 V

Jitter Summary

# ClassDataRate

Architecture SpecsPLL1BW

PLL1Peak

PLL2BW

PLL2Peak

CDRBW

CDRPeak

Specification Analysis Result ComplianceResultHF RMS LF RMS Pk-Pk HF RMS LF RMS Pk-Pk

1 GEN1 2.5 Gb/s Common Clock 1.12.13.1

22 MHz 3 dB 1.5 MHz 3 dB 1.5 MHz 0 dB 86 ps 698.96 fs 350.34 fs 6.67 psPASS

2 GEN2 5 Gb/s Common Clock 3.1 5 MHz 0.5 dB 16 MHz 0.5 dB N/A N/A 3.1 ps 3 ps 461.94 fs 178.90 fs 4.50 ps PASS

3 GEN2 5 Gb/s Common Clock 3.1 5 MHz 1 dB 16 MHz 0.5 dB N/A N/A 3.1 ps 3 ps 477.08 fs 166.71 fs 4.62 ps PASS

4 GEN2 5 Gb/s Common Clock 3.1 8 MHz 3 dB 16 MHz 0.5 dB N/A N/A 3.1 ps 3 ps 477.91 fs 50.41 fs 4.40 ps PASS

5 GEN2 5 Gb/s Common Clock 3.1 5 MHz 0.5 dB 16 MHz 1 dB N/A N/A 3.1 ps 3 ps 470.58 fs 191.85 fs 4.59 ps PASS

6 GEN2 5 Gb/s Common Clock 3.1 5 MHz 1 dB 16 MHz 1 dB N/A N/A 3.1 ps 3 ps 487.30 fs 180.73 fs 4.69 ps PASS

7 GEN2 5 Gb/s Common Clock 3.1 8 MHz 3 dB 16 MHz 1 dB N/A N/A 3.1 ps 3 ps 476.12 fs 63.36 fs 4.48 ps PASS

8 GEN2 5 Gb/s Common Clock 2.13.1

5 MHz 0.5 dB 16 MHz 3 dB N/A N/A 3.1 ps 3 ps 493.55 fs 198.47 fs 4.91 psPASS

9 GEN2 5 Gb/s Common Clock 1.12.13.1

5 MHz 1 dB 16 MHz 3 dB N/A N/A 3.1 ps 3 ps 515.29 fs 189.41 fs 5.04 psPASS


8 MHz 3 dB 16 MHz 3 dB N/A N/A 3.1 ps 3 ps 498.40 fs 73.03 fs 4.78 psPASS


2 MHz 0.01 dB 2 MHz 0.01 dB 10 MHz 0 dB 1 ps 63.95 fs 4.93 fs 572.41 fsPASS


2 MHz 2 dB 2 MHz 0.01 dB 10 MHz 0 dB 1 ps 71.64 fs 26.13 fs 693.22 fsPASS


4 MHz 0.01 dB 2 MHz 0.01 dB 10 MHz 0 dB 1 ps 117.69 fs 20.54 fs 1.08 psPASS


4 MHz 2 dB 2 MHz 0.01 dB 10 MHz 0 dB 1 ps 97.40 fs 34.63 fs 897.86 fsPASS


2 MHz 0.01 dB 2 MHz 1 dB 10 MHz 0 dB 1 ps 65.39 fs 14.58 fs 604.23 fsPASS


2 MHz 2 dB 2 MHz 1 dB 10 MHz 0 dB 1 ps 57.65 fs 15.97 fs 549.57 fsPASS


4 MHz 0.01 dB 2 MHz 1 dB 10 MHz 0 dB 1 ps 123.26 fs 28.36 fs 1.17 psPASS


4 MHz 2 dB 2 MHz 1 dB 10 MHz 0 dB 1 ps 103.18 fs 39.49 fs 934.09 fsPASS




2 MHz 2 dB 5 MHz 0.01 dB 10 MHz 0 dB 1 ps 156.08 fs 41.50 fs 1.52 psPASS




4 MHz 2 dB 5 MHz 0.01 dB 10 MHz 0 dB 1 ps 152.09 fs 17.79 fs 1.38 psPASS




2 MHz 2 dB 5 MHz 1 dB 10 MHz 0 dB 1 ps 144.40 fs 44.61 fs 1.39 psPASS

PCI Express Compliance ReportPage 1 of 26

Prepared by Silicon Labs PCIe Clock Jitter Tool v1.3 on 2017-06-16 09:26:07 GMT-04:00Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.

http://www.silabs.com/

http://www.silabs.com/pcie-jittertool

# ClassDataRate

Architecture SpecsPLL1BW

PLL1Peak

PLL2BW

PLL2Peak

CDRBW

CDRPeak

Specification Analysis Result ComplianceResultHF RMS LF RMS Pk-Pk HF RMS LF RMS Pk-Pk




4 MHz 2 dB 5 MHz 1 dB 10 MHz 0 dB 1 ps 130.23 fs 11.12 fs 1.14 psPASS

27 GEN4 16 Gb/s Common Clock 4.0 2 MHz 0.01 dB 2 MHz 0.01 dB 10 MHz 0 dB 500 fs 63.95 fs 4.93 fs 572.41 fs PASS

28 GEN4 16 Gb/s Common Clock 4.0 2 MHz 2 dB 2 MHz 0.01 dB 10 MHz 0 dB 500 fs 71.64 fs 26.13 fs 693.22 fs PASS

29 GEN4 16 Gb/s Common Clock 4.0 4 MHz 0.01 dB 2 MHz 0.01 dB 10 MHz 0 dB 500 fs 117.69 fs 20.54 fs 1.08 ps PASS

30 GEN4 16 Gb/s Common Clock 4.0 4 MHz 2 dB 2 MHz 0.01 dB 10 MHz 0 dB 500 fs 97.40 fs 34.63 fs 897.86 fs PASS

31 GEN4 16 Gb/s Common Clock 4.0 2 MHz 0.01 dB 2 MHz 1 dB 10 MHz 0 dB 500 fs 65.39 fs 14.58 fs 604.23 fs PASS

32 GEN4 16 Gb/s Common Clock 4.0 2 MHz 2 dB 2 MHz 1 dB 10 MHz 0 dB 500 fs 57.65 fs 15.97 fs 549.57 fs PASS

33 GEN4 16 Gb/s Common Clock 4.0 4 MHz 0.01 dB 2 MHz 1 dB 10 MHz 0 dB 500 fs 123.26 fs 28.36 fs 1.17 ps PASS

34 GEN4 16 Gb/s Common Clock 4.0 4 MHz 2 dB 2 MHz 1 dB 10 MHz 0 dB 500 fs 103.18 fs 39.49 fs 934.09 fs PASS


36 GEN4 16 Gb/s Common Clock 4.0 2 MHz 2 dB 5 MHz 0.01 dB 10 MHz 0 dB 500 fs 156.08 fs 41.50 fs 1.52 ps PASS


38 GEN4 16 Gb/s Common Clock 4.0 4 MHz 2 dB 5 MHz 0.01 dB 10 MHz 0 dB 500 fs 152.09 fs 17.79 fs 1.38 ps PASS


40 GEN4 16 Gb/s Common Clock 4.0 2 MHz 2 dB 5 MHz 1 dB 10 MHz 0 dB 500 fs 144.40 fs 44.61 fs 1.39 ps PASS


42 GEN4 16 Gb/s Common Clock 4.0 4 MHz 2 dB 5 MHz 1 dB 10 MHz 0 dB 500 fs 130.23 fs 11.12 fs 1.14 ps PASS

(1) Spread Spectrum Clocking (SSC) separation is intended to remove the energy associated with the spread spectrum (30KHz-33KHz) in the low frequency range (0.01-1.5MHz)specified by the PCI-Express Base Specification in order to define separate low frequency Rj and Dj components.

Unfiltered Waveform Jitter Information vs. Time

Time Interval Error Period

Cycle-to-Cycle





Spread Spectrum Phase Jitter Plot

Reference Clock AC Specifications

TestSpecification Analysis Result Compliance

ResultMin Max Min Max Avg

Rising Edge Rate .6 V/ns 4 V/ns 1.49 V/ns 1.57 V/ns 1.53 V/ns PASS

Falling Edge Rate .6 V/ns 4 V/ns 1.49 V/ns 1.57 V/ns 1.53 V/ns PASS

Diff Input High 150 mV 225.70 mV 225.70 mV 225.70 mV PASS

Diff Input Low -150 mV -225.70 mV -225.70 mV -225.70 mV PASS

Average Clock Period Accuracy -300 ppm 2,800 ppm N/A N/A -10 ppm PASS

Absolute Period 9.847 ns 10.203 ns 9.996 ns 10.004 ns 10.000 ns PASS

Cycle to Cycle Jitter 150 ps 0.00 s 7.50 ps 1.23 ps PASS

Duty Cycle 40 % 60 % 49.5 % 50.0 % 49.9 % PASS

Detailed Jitter Reports

In the pages that follow, jitter response is analyzed for each selected standard, architecture and filter parameter combination.





# Class Data Rate Architecture Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation

1 GEN1 2.5 Gb/s Common Clock 1.1 · 2.1 · 3.1 22 MHz 3 dB 1.5 MHz 3 dB 1.5 MHz 0 dB 10 ns Off (1)

Test SpecificationAnalysisResult

ComplianceResult

Refclk HF RMS Jitter 698.957 fs N/A

Refclk LF RMS Jitter 350.343 fs N/A

Pk-pk Phase Jitter 86 ps 6.669 ps PASS

Low Frequency Phase Jitter High Frequency Phase Jitter

Filter Magnitude Responses


2 GEN2 5 Gb/s Common Clock 3.1 5 MHz 0.5 dB 16 MHz 0.5 dB N/A N/A 12 ns On (1)


ComplianceResult

Refclk HF RMS Jitter 3.1 ps 461.941 fs PASS

Refclk LF RMS Jitter 3 ps 178.897 fs PASS

Pk-pk Phase Jitter 4.503 ps N/A








3 GEN2 5 Gb/s Common Clock 3.1 5 MHz 1 dB 16 MHz 0.5 dB N/A N/A 12 ns On (1)


ComplianceResult







4 GEN2 5 Gb/s Common Clock 3.1 8 MHz 3 dB 16 MHz 0.5 dB N/A N/A 12 ns On (1)


ComplianceResult











5 GEN2 5 Gb/s Common Clock 3.1 5 MHz 0.5 dB 16 MHz 1 dB N/A N/A 12 ns On (1)


ComplianceResult







6 GEN2 5 Gb/s Common Clock 3.1 5 MHz 1 dB 16 MHz 1 dB N/A N/A 12 ns On (1)


ComplianceResult











7 GEN2 5 Gb/s Common Clock 3.1 8 MHz 3 dB 16 MHz 1 dB N/A N/A 12 ns On (1)


ComplianceResult







8 GEN2 5 Gb/s Common Clock 2.1 · 3.1 5 MHz 0.5 dB 16 MHz 3 dB N/A N/A 12 ns On (1)


ComplianceResult











9 GEN2 5 Gb/s Common Clock 1.1 · 2.1 · 3.1 5 MHz 1 dB 16 MHz 3 dB N/A N/A 12 ns On (1)


ComplianceResult







10 GEN2 5 Gb/s Common Clock 2.1 · 3.1 8 MHz 3 dB 16 MHz 3 dB N/A N/A 12 ns On (1)


ComplianceResult











11 GEN3 8 Gb/s Common Clock 3.1 · 4.0 2 MHz 0.01 dB 2 MHz 0.01 dB 10 MHz 0 dB 12 ns On (1)


ComplianceResult

Refclk HF RMS Jitter 1 ps 63.946 fs PASS


Pk-pk Phase Jitter 572.408 fs N/A




12 GEN3 8 Gb/s Common Clock 3.1 · 4.0 2 MHz 2 dB 2 MHz 0.01 dB 10 MHz 0 dB 12 ns On (1)


ComplianceResult













ComplianceResult









ComplianceResult











15 GEN3 8 Gb/s Common Clock 3.1 · 4.0 2 MHz 0.01 dB 2 MHz 1 dB 10 MHz 0 dB 12 ns On (1)


ComplianceResult







16 GEN3 8 Gb/s Common Clock 3.1 · 4.0 2 MHz 2 dB 2 MHz 1 dB 10 MHz 0 dB 12 ns On (1)


ComplianceResult













ComplianceResult









ComplianceResult













ComplianceResult









ComplianceResult













ComplianceResult









ComplianceResult













ComplianceResult









ComplianceResult













ComplianceResult









ComplianceResult











27 GEN4 16 Gb/s Common Clock 4.0 2 MHz 0.01 dB 2 MHz 0.01 dB 10 MHz 0 dB 12 ns On (1)


ComplianceResult

Refclk HF RMS Jitter 500 fs 63.946 fs PASS






28 GEN4 16 Gb/s Common Clock 4.0 2 MHz 2 dB 2 MHz 0.01 dB 10 MHz 0 dB 12 ns On (1)


ComplianceResult













ComplianceResult









ComplianceResult











31 GEN4 16 Gb/s Common Clock 4.0 2 MHz 0.01 dB 2 MHz 1 dB 10 MHz 0 dB 12 ns On (1)


ComplianceResult







32 GEN4 16 Gb/s Common Clock 4.0 2 MHz 2 dB 2 MHz 1 dB 10 MHz 0 dB 12 ns On (1)


ComplianceResult













ComplianceResult









ComplianceResult













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Transfer Function Constants

# Class Architecture SpecsH1BW

H1Peaking

H1Omega

H1Zeta

H2BW

H2Peaking

H2Omega

H2Zeta

H3BW

H3Peaking

H3Omega

H3Zeta

Delay

1 GEN1 Common Clock 1.12.13.1

22 MHz 3 dB 7.46800E+7 5.40000E-1 1.5 MHz 3 dB 5.09000E+6 5.40000E-1 1.5 MHz 0 dB 9.42478E+6 0.00000E+0 10 ns


5 MHz 0.5 dB 8.30009E+6 1.75000E+0 16 MHz 0.5 dB 2.65716E+7 1.75000E+0 12 ns


5 MHz 1 dB 1.14605E+7 1.16000E+0 16 MHz 0.5 dB 2.65716E+7 1.75000E+0 12 ns


8 MHz 3 dB 2.70428E+7 5.40000E-1 16 MHz 0.5 dB 2.65716E+7 1.75000E+0 12 ns


5 MHz 0.5 dB 8.30009E+6 1.75000E+0 16 MHz 1 dB 3.66624E+7 1.16000E+0 12 ns


5 MHz 1 dB 1.14605E+7 1.16000E+0 16 MHz 1 dB 3.66624E+7 1.16000E+0 12 ns


8 MHz 3 dB 2.70428E+7 5.40000E-1 16 MHz 1 dB 3.66624E+7 1.16000E+0 12 ns


5 MHz 0.5 dB 8.30009E+6 1.75000E+0 16 MHz 3 dB 5.40919E+7 5.40000E-1 12 ns


5 MHz 1 dB 1.14605E+7 1.16000E+0 16 MHz 3 dB 5.40919E+7 5.40000E-1 12 ns


8 MHz 3 dB 2.70428E+7 5.40000E-1 16 MHz 3 dB 5.40919E+7 5.40000E-1 12 ns

11 GEN3 Common Clock 3.14.0

2 MHz 0.01 dB 4.48000E+5 1.40000E+1 2 MHz 0.01 dB 4.48000E+5 1.40000E+1 10 MHz 0 dB 6.28319E+7 0.00000E+0 12 ns


2 MHz 2 dB 6.02000E+6 7.30000E-1 2 MHz 0.01 dB 4.48000E+5 1.40000E+1 10 MHz 0 dB 6.28319E+7 0.00000E+0 12 ns






2 MHz 0.01 dB 4.48000E+5 1.40000E+1 2 MHz 1 dB 4.62000E+6 1.15000E+0 10 MHz 0 dB 6.28319E+7 0.00000E+0 12 ns


2 MHz 2 dB 6.02000E+6 7.30000E-1 2 MHz 1 dB 4.62000E+6 1.15000E+0 10 MHz 0 dB 6.28319E+7 0.00000E+0 12 ns

























27 GEN4 Common Clock 4.0 2 MHz 0.01 dB 4.48000E+5 1.40000E+1 2 MHz 0.01 dB 4.48000E+5 1.40000E+1 10 MHz 0 dB 6.28319E+7 0.00000E+0 12 ns

28 GEN4 Common Clock 4.0 2 MHz 2 dB 6.02000E+6 7.30000E-1 2 MHz 0.01 dB 4.48000E+5 1.40000E+1 10 MHz 0 dB 6.28319E+7 0.00000E+0 12 ns



31 GEN4 Common Clock 4.0 2 MHz 0.01 dB 4.48000E+5 1.40000E+1 2 MHz 1 dB 4.62000E+6 1.15000E+0 10 MHz 0 dB 6.28319E+7 0.00000E+0 12 ns

32 GEN4 Common Clock 4.0 2 MHz 2 dB 6.02000E+6 7.30000E-1 2 MHz 1 dB 4.62000E+6 1.15000E+0 10 MHz 0 dB 6.28319E+7 0.00000E+0 12 ns















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Documents

Requirements AN946: PCI-Express 4.0 Jitter - Silicon Labs · 1. Clocking Architectures In the application note, "AN562: PCI Express 3.0 Jitter Requirements", there are three different