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Register Transfer Language:
A digital system is an interconnection of digital hardware modules that perform a specific task.
The modules are constructed from digital components such as registers, decoders, arithmetic elements, and control logic.
These modules are interconnected with common data and control paths to form a digital computer.
The operations executed on data stored in registers are called microoperations.
A microoperation is an elementary operation performed on the information stored in one or more registers.
For any function of the computer, a sequence of microoperations is used to describe it
The result of the operation may be replace the previous binary information of a register or transferred to another register
Examples of microoperations are shift, count, clear and load.
1
Register Transfer Language:
The internal hardware organization of a digital computer is defined by specifying:
The set of registers it contains and their function. The sequence of microoperations performed on the binary information stored in the registers. The control that initiates the sequence of microoperations.
The symbolic notation used to describe the microoperation transfers among registers is called a register transfer language.
The term register transfer implies the availability of hardware logic circuit that can transfer the result of the operation to the same or another register.
A register transfer language (RTL) is a system for expressing in symbolic form the microoperation sequences among the register of a digital module.
Computer registers are designated by capital letters (sometimes followed by numerals) to denote the function of the register
R1: processor register (general purpose register) MAR: Memory Address Register (holds an address for a memory unit) PC: Program Counter IR: Instruction Register SR: Status Register
2
Register Transfer:
The individual flip-flops in an n-bit register are numbered in sequence from 0 to n-1 (from the right position toward the left position).
R1
Register R1
7 6 5 4 3 2 1 0
Showing individual bits
PC
Numbering of bits
15 0
Partitioned into two parts
PC(H) PC(L)08 715
Lower byteUpper byte
Information transfer from one register to another is described by a replacement operator:
R2 ← R1
This statement denotes a transfer of the content of register R1 into register R2.
The transfer happens in one clock cycle.
The content of the R1 (source) does not change.
The content of the R2 (destination) will be lost and replaced by the new data transferred from R1. 3
Register Transfer:
Register transfer statement implies that the circuits are available from the outputs of the source register to the inputs of the destination register, and that the destination register has a parallel load capability.
Conditional transfer occurs only under a control condition
This can be shown by means of an if-then statement:
If (P = 1) then (R2 ← R1)
where P is control signal generated in the control section.
The control variables are separated from the register transfer operation by specifying a control function.
A control function is a Boolean variable that is equal to 1 or 0.
The control function is included in the statement as follows:
P: R2 ← R1
The control condition is terminated with a colon.
It symbolizes that the transfer operation takes place by the hardware only if P = 1.
4
Register Transfer:
n
Clock
R1
R2Control Circuit
LoadP
Block Diagram:
t t+1
Clock
Load
Transfer occurs here
Synchronized with the clock
Timing Diagram:
5
Register Transfer:
The statement
T: R2 ← R1, R1 ← R2
denotes an operation that exchanges the contents of two registers during one common clock pulse provided that T = 1.
This simultaneous operation is possible with registers that have edge-triggered flip-flops.
Symbol Description ExamplesLetters Denotes a register MAR, R2Parentheses ( ) Denotes a part of a register R2(0- 7), R2(L)Arrow ← Denotes transfer of information R2 <- - R1Comma , Separates two microoperations R2 <- - R1, R1 <- - R2
Basic Symbols for Register Transfer:
6
Bus and Memory Transfers:
A typical digital computer has many registers, and paths must be provided to transfer information from one register to another.
The number of wires will be excessive if separate lines are used between each register and all other registers in the system.
The more efficient scheme for transferring information between registers in a multiple-register system is a common bus system.
A bus structure consists of a set of common lines, one for each bit of a register, through which binary information is transferred one at a time.
Control signals determine which register is selected by the bus during each particular register transfer.
Common bus system can be constructed either by using multiplexers or by using three-state buffers.
7
Bus System for Four Registers using Multiplexers:
S1 S0 Register selected 0 0 A 0 1 B 1 0 C 1 1 D
1 03 2
4*1MUX 3
1 03 2
1 03 2
4*1MUX 0
1 03 2
1 03 2
4*1MUX 1
1 03 2
1 03 2
4*1MUX 2
1 03 2
4-linecommonbus
Register C Register B Register ARegister D
S1
S0
A bus system will multiplex k registers of n bits each to produce an n-line common bus.
The number of multiplexers needed to construct the bus is equal to n, the number of bits in each register.
The size of each multiplexer must be k X 1, since it multiplexes k data lines.
•BUS ← C
•R1 ← BUS
• R1 ← C
8
Bus System for Four Registers using Three-State Buffers:
A three state gate is a digital circuit that exhibits three states.
Logic 1 State
Logic 0 State
High Impedance State Z (Open Circuit)
Buffer --- A device designed to be inserted between other devices to match impedance, to prevent mixed interactions, and to supply additional drive or relay capability
Buffer types are classified as inverting or non-inverting.
Normal input A
Control input C
If C=1, Output Y = A
If C=0, Output = High-impedance
9
Bus System for Four Registers using Three-State Buffers:
The outputs of four buffer are connected together to form a single bus line.
No more than one buffer may be in the active state at any given time.
10
0
3
1
2
S 0
S 1
E
2*4decoder
Select inputs
Enable input
Bus line for bit 0
D0
A0
B0
C0
Memory Read : A transfer information into DR from the memory word M selected by the address in AR
Memory Write : A transfer information from R1 into the memory word M selected by the address in AR
1][:
][:
RARMWRITE
ARMDRREAD
Memory Transfer: AR: Address Register.
DR: Data Register.M : Memory Word (Data)
Microoperations:
A microoperation is an elementary operation performed with the data stored in registers.
The microoperations performed in digital systems are classified into four categories:
Register transfer microoperations --- transfer binary information one register to another.
Arithmetic microoperations --- perform arithmetic operation on numeric data stored in registers.
Logic microoperations --- perform bit manipulation operations on numeric data stored in registers.
Shift microoperations --- perform shift operations on data stored in registers.
11
Arithmetic Microoperations:
Symbolic Designation Description
Contents of R1 plus R2 transferred to R3
Contents of R1 minus R2 transferred to R3
Compliment the contents of R2 (1’s compliment)
2’s compliment the contents of R2 (negative)
R1 plus the 2’s compliment of R2 (subtraction)
Increment the content of R1 by one
Decrement the content of R1 by one
1R2R2 1R2R1R3
R2R1R3 R2R1R3
1R1R1 1R1R1
R2R2
12
4-bit Binary Adder:
FA FA FAFA
A0 A1 A2 A3 B0 B1 B2 B3
C0 C1 C2 C3
C4 S0 S1 S2 S3
C4 C3 C2 C1 C0
A3 A2 A1 A0
B3 B2 B1 B0
S3 S2 S1 S0
13
4-bit Binary Adder-Subtractor:
FAFAFAFA
A0 A1 A2 A3 B0 B1 B2 B3
C0 C1 C2 C3
C4 S0 S1 S2 S3
M
14
4-bit Binary Adder-Subtractor:
C4 C3 C2 C1 C0
A3 A2 A1 A0
B3’ B2
’ B1’ B0
’
S3 S2 S1 S0
C4 C3 C2 C1 C0
A3 A2 A1 A0
B3 B2 B1 B0
S3 S2 S1 S0
M = 0 M = 1
A + B A - B
15
4-bit Binary Incrementer:
A0 A1 A2 A3
S0 S1 S2 S3
x
S
y
C
HA
x
S
y
C
HA
x
S
y
C
HA
x
S
y
C
HA
C4
1
C4 C3 C2 C1
A3 A2 A1 A0
1
S3 S2 S1 S0
16
2
1
0
3
4*1MUX
S 0
S 1
X0
C1
Y 0
C0
2
1
0
3
4*1MUX
S 0
S 1
X1
C2
Y 1
C1
2
1
0
3
4*1MUX
S 0
S 1
X3
C4
Y 3
C3
2
1
0
3
4*1MUX
S 0
S 1
X2
C3
Y 2
C2
FA
FA
FA
FA
Input Output MicrooperationS1 S0 Cin Y D=A+Y+Cin
0 0 0 B D=A+B Add0 0 1 B D=A+B+1 Add with carry0 1 0 B' D=A+B' Subtract with borrow0 1 1 B' D=A+B'+1 Subtract 1 0 0 0 D=A Transfer A1 0 1 0 D=A+1 Increment A1 1 0 1 D=A- 1 Decrement A1 1 1 1 D=A Transfer A
Select
A+B’=A+B’+1-1 = A-B-1A+1111=A-1
A-1+1=A
S0S1
Cin
D0
D1
D2
D3
Cout
A0
B0
A1
B1
A2
B2
A3
B3
0
Arithmetic Circuit:
17
Logic Microoperations:
Logic microoperations specify binary operations for strings of bits stored in registers.
These operations consider each bit of the register separately and treat them as binary variables.
Example: R2R1R1:P
1010 Content of R1+ 1100 Content of R2 0110 Content of R1 after P=1
Special Symbols
Special symbols will be adopted for the logic microoperations OR(V), AND(Ʌ), and complement (a bar on top), to distinguish them from the corresponding symbols used to express Boolean functions.
18
Logic Microoperations:
R5VR6R4R3,R2R1:QP
Logic OR Arithmetic ADD
S 1
S 0
0
1
3
2
4*1MUX
E i
Ai
Bi
S1 S0 Output Operation
0 0 E = A Ʌ B AND
0 1 E = A V B OR
1 0 E = A B XOR
1 1 E = A’ ComplimentNOT
19
List of Logic Microoperations:
There are 16 different logic microoperations that can be performed with two binary variables, determined from all possible truth tables obtained with two binary variables, as shown below:
x y F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
The 16 Boolean functions of two variables x and y are expressed in algebraic form in the first column of table #.
20
Boolean Function Microoperation Name
F0 = 0 F ← 0 Clear
F1 = xy F ← A Ʌ B AND
F2 = xy’ F ← A Ʌ B
F3 = x F ← A Transfer A
F4 = x’y F ← A Ʌ B
F5 = y F ← B Transfer B
F6 = x y F ← A B Exclusive-OR
F7 = x + y F ← A V B OR
F8 = (x + y)’ F ← A V B NOR
F9 = (x y)’ F ← A B Exclusive-NOR
F10 = y’ F ← B Compliment B
F11 = x + y’ F ← A V B
F12 = x’ F ← A Compliment A
F13 = x’ + y F ← A V B
F14 = (xy)’ F ← A Ʌ B NAND
F15 = 1 F ← all 1’s Set to all 1’s
Table #
21
Logic Microoperations --- Applications:
Logic microoperations are very useful for manipulating individual bits or a portion of a word stored in a register
Used to change bit values, delete a group of bits, or insert new bit values
Selective-set
The selective-set operation sets to 1 the bits in register A where there are corresponding 1’s in register B. It does not effect bit positions that have 0’s in B.
1010 A before 1100 B(Logic Operand) 1110 A After
AVBA
22
Selective-complement
The selective-complement operation complements bits in A where there are corresponding 1’s in B. It does not effect bit positions that have 0’s in B.
BAA 1010 A before 1100 B(Logic Operand) 0110 A After
Logic Microoperations --- Applications: Selective-clear
The selective-clear operation clears to 0 the bits in A only where there are corresponding 1’s in B.
BAA 1010 A before 1100 B(Logic Operand) 0010 A After
23
Selective-mask
The mask operation is similar to the selective-clear operation except that the bits of A are cleared only where there are corresponding 0’s in B.
BAA 1010 A before 1100 B(Logic Operand) 1000 A After masking Clear
The clear operation compares the words in A and B and produces an all 0’s result if the two numbers are equal
0110 A 0110 B 0000 A after clear
BAA
Shift Microoperations:
Used for serial transfer of data.
Three types of shift: Logical, Circular, and Arithmetic.
SymbolicDesignation
Description
R ← shl R Shift left register R
R ← shr R Shift right register R
R ← cil R Circular shift left register R
R ← cir R Circular shift right register R
R ← ashl R Arithmetic shift left register R
R ← ashr R Arithmetic shift right register R
24
Logical Shift:
Transfers 0 through the serial input.
? 0R0R1R2R3Rn-1
0 ?R0R1R2R3Rn-1
Logical Shift Left:
Logical Shift Right:
25
Register Contents Before Shift Operation
1 0 1 1 0 1 0 1
Register Contents After Shift left Operation
0 1 1 0 1 0 1 0
Register Contents After Shift Right Operation
0 1 0 1 1 0 1 0
Circular Shift: Also known as rotate operation, circulates the bits of the register around the two ends without loss of information.
This is accomplished by connecting the serial output of the shift register to its serial input.
Circular Shift Right
R0R1R2R3Rn-1
Circular Shift Left
R0R1R2R3Rn-1
26
Circular Shift Examples:
Register Contents Before Shift Operation
1 0 1 1 0 1 0 1
Register Contents After Shift left Operation
0 1 1 0 1 0 1 1
Register Contents After Shift Right Operation
1 1 0 1 1 0 1 0
27
Arithmetic Shift: Shifts a signed binary number to the left or right.
An arithmetic shift-left multiplies a signed binary number by 2:
ashl (00100): 01000
An arithmetic shift-right divides the number by 2:
ashr (00100) : 00010
Arithmetic Shift Right:
Arithmetic Shift RightSign Bit
?R0R1R2R3Rn-1
28
Register Contents Before Arithmetic Shift Right Operation
0 0 1 1 0 1 0 1
Register Contents After Arithmetic Shift Right Operation
0 0 0 1 1 0 1 0
Register Contents Before Arithmetic Shift Right Operation
1 0 1 1 0 1 0 1
Register Contents After Arithmetic Shift Right Operation
1 1 0 1 1 0 1 0
Arithmetic Shift Left: The arithmetic shift-left inserts a 0 into R0, and shifts all other bits to the left.
The initial bit of R n – 1 is lost and replaced by the bit from R n – 2.
Arithmetic Shift LeftSign Bit
0? R0R1R2R3Rn-1
29
Register Contents Before Arithmetic Shift Left Operation
0 0 1 1 0 1 0 1
Register Contents After Arithmetic Shift Left Operation
0 1 1 0 1 0 1 0
Register Contents Before Arithmetic Shift Left Operation
1 0 1 1 0 1 0 1
Register Contents After Arithmetic Shift Left Operation
0 1 1 0 1 0 1 0
Arithmetic Shift Left: A sign reversal occurs if the bit in Rn-1 changes in value after the shift.
This happens if the multiplication by 2 causes an overflow.
An overflow flip-flop VS can be used to detect an arithmetic shift-left overflow.
VS = Rn-1 Rn-2
Rn-2
VS=
Rn-1 1 overflow
0 no overflow
30
Arithmetic Shift Unit:
S 1 0 S 1 0 S 1 0 S 1 0
A3
A2A1
A0Serial Input
IR
Serial Input IL
Select
0 for shift right
1 for shift left
H3 H2 H1 H0
MUX MUX MUX MUX
SelectS
Output
H3 H2 H1 H0
0 IR A3 A2 A1
1 A2 A1 A0 IL31
Arithmetic Logic Shift Unit:
2
1
0
3
4*1MUX
Selec t
One state of arithmetic
c ircuit(F ig. 4.9)
One state of logic c ircuit(F ig. 4.10)
S3S2S1S0
C i + 1
Ci
Di
Ei
Fi
Bi
Ai
A i - 1
A i + 1 32
33
Instruction Codes:
• The internal organization of a digital system is defined by the sequence of microoperations it performs on data stored in the registers.
• The user of a program can control the process by means of a program.
• A program is a set of instructions that specify the operations, operands, and the sequence by which processing has to occur.
• An instruction code is a group of bits that instruct that the computer to perform a specific operation.
• An instruction code is usually divided into two parts, operation code (opcode) and operand.
• The operation code is a group of bits that define such operations as add, subtract, multiply, shift, and compliment.
• A computer operation is a part of an instruction stored in computer memory that tells the computer to perform a specific operation, which requires a sequence of microoperations in internal computer registers.
• An operation code is sometimes called a macrooperation because it specifies a set of micro-operations.
34
Stored Program Organization:
• A stored program organization consists of one processor register and an instruction code format with two parts.
• The first part specifies the operation to be performed and the second specifies an address.
• The memory address tells the control where to find an operand in memory.
• Instructions are stored in one section of memory and data in another.
Instruction(program)
Operands(data)
Memory4096 X 16
Processor register(accumulator or
AC)
Binary operand (Data)
15 0
Opcode Address15 12 11 0
Instruction Format
35
Stored Program Organization:
• When the second part of an instruction code specifies an operand (not an address), the instruction is said to have an immediate operand.
• When the second part specifies the address of an operand, the instruction is said to have direct address.
• When the second part of an instruction code specifies an address of a memory word in which the address of the operand is found, the instruction is said to have indirect address. I Opcode Address
15 14 12 11 0
Instruction Format
• Instruction code format that consists of a 3-bit operation code, a 12-bit address, and a address mode bit designated by I.
• The mode bit is 0 for a direct address and 1 for an indirect address.
• The effective address is the address of the operand in a computation-type instruction or the target address in a branch-type instruction.
36
Stored Program Organization:
22 0 ADD 457
457 Operand
Memory
AC
+
Direct address
35 1 ADD 300
1350 Operand
Memory
AC
+
Indirect address
300 1350
I Opcode Address
15 14 12 11 0
Instruction Format
37
Basic Computer Registers and Memory:
Memory4096 words
16 bits per word
AC
DR
15 0
15 0
TR
15 0
IR
15 0
OUTR
7 0 INPR
7 0
AR
11 0
PC
11 0
38
Computer Registers:
RegisterSymbol
Numberof bits
Register name Function
DR 16 Data register Holds memory operand
AR 12 Address register Holds address for memory
AC 16 Accumulator Processor register
IR 16 Instruction register Holds instruction code
PC 12 Program counter Holds address of instruction
TR 16 Temporary register Holds temporary data
INPR 8 Input register Hold input character
OUTR 8 Output register Holds output character
Common Bus System: The basic computer has eight registers, a memory unit, and a
control unit.
Paths must be provided to transfer information from one register to another and between memory and registers.
A more efficient scheme for transferring information in a system with many registers is to use a common bus.
39
Common Bus System:
The outputs of seven registers and memory are connected to the common bus.
The specific output is selected by MUX (S0, S1, S2) :
Memory(7), AR(1), PC(2), DR(3), AC(4), IR(5), TR(6)
When LD(Load Input) is enable, the particular register receives the data from the bus
Control Input : LD, INC, CLR, Write, Read
Load input (LD): Enables the input of a register to download bits form the common bus. When LD = 1 for a register, the data on the common bus is read into the register during the next clock pulse transition.
Increment input (INR): Increments the content of a register.
Clear input (CLR): Clear the content of a register to zero.
40
Common Bus System:Bus
s1 s2s0
16-bit common bus
ClockLD
LD
LD
INR
OUTR
IR
INPR
LD INR CLR
LD INR CLR
LD INR CLR
LD INR CLR
WRITEAddress
Adder & Logic
E
DR
PC
AR
CLR
7
1
2
3
4
5
6
AC
READ
Memory Unit 4096x16
TR
41
Computer Instructions:
The basic computer has three instruction formats:
I Opcode Address
15 14 12 11 0
Memory – reference instruction
(Opcode = 000 through 110)
0 1 1 1 Register Operation
15 12 11 0
Register - reference instruction
(Opcode = 111, I = 0)
1 1 1 1 I/O Operation15 12 11 0
Input – output instruction
(Opcode = 111, I = 1)
Register – reference instructions Input – output instructions
Memory – reference instructions
Memory – reference instructions
Symbol
Hexadecimal
Code
Description Symbolic Description
I = 0 I = 1
AND 0xxx 8xxx AND memory word to AC AC AC M[AR]
ADD 1xxx 9xxx Add memory word to AC AC AC + M[AR], E Cout
LDA 2xxx Axxx Load memory word to AC AC M[AR]
STA 3xxx Bxxx Store content of AC in memory
M[AR] AC
BUN 4xxx Cxxx Branch unconditionally PC AR
BSA 5xxx Dxxx Branch and save return address
M[AR] PC, PC AR + 1
ISZ 6xxx Exxx Increment and skip if zero M[AR] M[AR] + 1,If M[AR] + 1 = 0 then PC PC + 1
42
Memory – Reference Instructions:
Symbol
Hex Cod
e
Description Symbolic Description
CLA 7800 Clear AC AC 0
CLE 7400 Clear E E 0
CMA 7200 Compliment AC AC AC
CME 7100 Compliment E E E
CIR 7080 Circular right AC and E AC shr AC, AC(15) E, E AC(0)
CIL 7040 Circular left AC and E AC shl AC, AC(0) E, E AC(15)
INC 7020 Increment AC AC AC + 1
SPA 7010 Skip next instruction if AC positive
If (AC(15) = 0) then (PC PC + 1)
SNA 7008 Skip next instruction if AC negative
If (AC(15) = 1) then (PC PC + 1)
SZA 7004 Skip next instruction if AC zero If (AC = 0) then (PC PC + 1)
SZE 7002 Skip next instruction if E is 0 If (E = 0) then (PC PC + 1)
HLT 7001 Halt computer (Program termination)
S 0 (S is a start-stop flip-flop)
43
Register – Reference Instructions:
Input – output instructions
Symbol
HexCod
e
Description Symbolic Description
INP F800 Input character to AC AC(0-7) INPR, FGI 0
OUT F400 Output character from AC
OUTR AC(0-7), FGO 0
SKI F200 Skip on input flag If (FGI = 1) then (PC PC+ 1)
SKO F100 Skip on output flag If (FGO = 1) then (PC PC+ 1)
ION F080 Interrupt on IEN 1
IOF F040 Interrupt off IEN 0
44
Input – Output Instructions:
ORG 0 /Origin of program is at location 0
LDA A /Load operand from location A
ADD B /Add operand from location B
STA C /Store sum in location C
HLT /Halt computer
A DEC 83 /Decimal operand
B DEC -23 /Decimal operand
C DEC 0 /Sum stored in location C
END /End of symbolic program
45
Assembly Language Program to Add Two Numbers:
The numbers may be positive or negative, but if negative, they must be converted to binary in the signed 2’s compliment representation.
The symbols ORG, DEC, and END are called as pseudo instructions.
ORG 100 /Origin of program is at location 100
LDA SUB /Load subtrahend to AC
CMA /Compliment AC (1’s compliment of subtrahend)
INC /Increment AC (2’s compliment of subtrahend)
ADD MIN /Add minuend to AC
STA DIF /Store difference
HLT /Halt computer
MIN, DEC 83 /Minuend (M)
SUB, DEC -23 /Subtrahend (N)
DIF, HEC 0 /Difference stored here
END /End of symbolic program
46
Assembly Language Program to Subtract Two Numbers:
47
Program Control: Program Control Instruction: Branch and Jump
instructions are used interchangeably to mean the same thing. Status register bits:
V Z S C
Check for zero output8
8 8
8-bit ALU
F7 – F0
C7
C8
F7
Output F
48
Program Control: Status Bit Conditions:
A status register stores status bit conditions called condition-code bits or flag bits
The bits are set or cleared as a result of an operation performed in the ALU.
4-bit status register
Bit C (carry) is set to 1 if the end carry C8 is 1.
Bit S (sign) is set to 1 if the highest-order bit F7 is 1.
Bit Z (zero) is set to 1 if the output of the ALU contains all 0’s.
Bit V (overflow) is set to 1 if the exclusive-OR of the last two carries (C8 and C7) is equal to 1.
11110000
+ 11101100 (2’s comp. of B)
1 11011100
C = 1, S = 1, V = 0, Z = 0
Example : A - B = A + ( 2’s Comp. of B ) : A =11110000, B = 00010100
49
Program Interrupt:
Program Interrupt
Transfer program control from a currently running program to another service program as a result of an external or internal generated request.
Control returns to the original program after the service program is executed.
Interrupt Service Program:
An interrupt is initiated by an internal or external signal (except for software interrupt).
The address of the interrupt service program is determined by the hardware.
An interrupt procedure stores all the information necessary to define the state of the CPU.
50
Program Interrupt:
Interrupt Detect
Determine the address of ISR
Store Information
Main body of ISR
Restore Information
Interrupt Return
External Int.Internal Int.Software Int.
PC, CPU Register, Status Register,(PSW)
51
Program Interrupt:
Types of Interrupts:
•External Interrupts - come from I/O device, from a timing device, from a circuit monitoring the power supply, or from any other external source.
•Internal Interrupts or TRAP - caused by register overflow, attempt to divide by zero, an invalid operation code, stack overflow, and protection violation.
•Software Interrupts - initiated by executing an instruction (INT or RST) used by the programmer to initiate an interrupt procedure at any desired point in the program.Types of CPU Organizations:
•Single accumulator organization
•General register organization
•Stack organization
52
General Register Organization:Clock Input
MUX MUX
Arithmetic Logic Unit(ALU)
Output
A bus B bus
SELBSELALoad
(7 lines)
SELDOPR
3 X 8Decoder
R1R2R3
R4R5R6R7
53
General Register Organization:
• 2 MUX: select one of 7 register or external data input by SELA and SELB.
• BUS A and BUS B form the inputs to a common ALU.
• ALU : An operation is selected by the ALU operation selector (OPR).
• The result of the microoperation is available for external data output and also goes into the inputs of all registers.
• The result of a microoperation is directed to a destination register selected by a decoder (SELD).
• Control word: The 14 binary selection inputs (3 bits for SELA, 3 for SELB, 3 for SELD, and 5 for OPR)Control Word Format:
54
General Register Organization:
Encoding of register selection fields:
Binary Code SELA SELB SELD
000 Input Input None
001 R1 R1 R1
010 R2 R2 R2
011 R3 R3 R3
100 R4 R4 R4
101 R5 R5 R5
110 R6 R6 R6
111 R7 R7 R7
55
General Register Organization:
Encoding of ALU operations:
OPR Select Operation Symbol
00000 Transfer A TSFA
00001 Increment A INCA
00010 Add A + B ADD
00101 Subtract A – B SUB
00110 Decrement A DECA
01000 AND A and B AND
01010 OR A and B OR
01100 XOR A and B XOR
01110 Compliment A COMA
10000 Shift right A SHRA
11000 Shift left A SHLA
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General Register Organization:
• Example: R1 R2 + R3
• MUX A selector (SELA - 010) : to place the content of R2 into BUS A.
• MUX B selector (SELB - 011) : to place the content of R3 into BUS B.
• ALU operation selector (OPR - 00010) : to provide the arithmetic addition R2 + R3.
• Decoder selector (SELD - 001) : to transfer the content of the output bus into R1.Control Word Format:
Field SELA SELB SELD OPR
Symbol R2 R3 R1 ADD
Control Word: 010 011 001 00010
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General Register Organization:
Microoperation Symbolic Designation Control Word
SELA SELB SELD OPR
R1 R2 – R3 R2 R3 R1 SUB 010 011 001 00101
R4 R4 V R5 R4 R5 R4 OR 100 101 100 01010
R6 R6 + 1 R6 --- R6 INCA 110 000 110 00001
R7 R1 R1 --- R7 TSFA 001 000 111 00000
Output R2 R2 --- None TSFA 010 000 000 00000
Output Input Input --- None TSFA 000 000 000 00000
R4 shl R4 R4 --- R4 SHLA 100 000 100 11000
R5 0 R5 R5 R5 XOR 101 101 101 01100
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Stack Organization:
• Stack is a set of memory locations in R/W memory (or set of registers) used to store data temporarily during program execution.
• A stack stores the information in such a manner that the item stored last is the first item retrieved. i.e., LIFO; last-in, first-out.
• The address register that holds the address for the stack is called a stack pointer (SP) because its value always points at the top item in the stack.
• The two operations of the stack are the insertion and deletion of items.
• The operation of insertion is called push (or push-down).
• The operation deletion is called pop (or pop-up).
• A stack can be placed in a portion of s large memory (memory stack) or it can be organized as a collection of a finite number of memory words or registers (register stack).
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Register Stack: • A register stack is organized as a collection of a finite number of registers.
• In a 64-word stack, the stack pointer contains 6 bits.
• The one-bit register FULL is set to 1 when the stack is full; EMTY register is 1 when the stack is empty.
• The data register DR holds the data to be written into or read from the stack.
• Initially, SP is cleared to 0, EMTY is set to 1, and FULL is cleared to 0, so that SP points to the word at address 0.
• If the stack is not full (if FULL = 0), a new item is inserted with a push operation.
• A new item is deleted from the stack if the stack is not empty (if EMTY = 0) with a pop operation.
A
B
CSP
EMTYFULL
DR
64
0
1
2
3
4
Address
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Register Stack:
• push operation:
• SP SP + 1 Increment stack pointer
• M[SP] DR Write item on top of the stack
• If (SP = 0) then (FULL 1) Check if stack is full
• EMTY 0 Mark the stack not empty
• pop operation:
• DR M[SP] Read item from top of stack
• SP SP - 1 Decrement stack pointer
• If (SP = 0) then (EMTY 1) Check if stack is empty
•FULL 0 Mark the stack not full
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Memory Stack:• A memory stack is implemented by assigning a portion of memory to a stack operation and using a processor register as a stack pointer.
• The program counter PC points at the address of the next instruction in the program.
• The address register AR points at an array of data.
• The stack pointer SP points at the top of the stack.
• The three registers are connected to a common address bus, and either one can provide address for memory.
• Once the stack is initialized by loading address of stack top in SP, the stack grows with decreasing address.
Program(instruc tions)
Data(operands)
Stack
SP
PC
AR
DR
1000
2000
4001
3000
4000
3999
3998
3997
AddressMemory unit
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Memory Stack:• push operation:
• SP SP - 1 Decrement stack pointer
• M[SP] DR Write item on top of the stack
•pop operation:
• DR M[SP] Read item from top of stack
• SP SP +1 Increment stack pointer
Arithmetic Expressions - Notation:• A + B Infix notation
• +AB Prefix or Polish notation
• AB+ Postfix or reverse Polish notation (RPN)
• A * B + C * D AB*CD*+
• This expression is evaluated from left to right as follows:
• (A* B)CD*+
• (A* B)(C*D)+
• (A* B) + (C*D)
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Conversion to RPN:
• The conversion from infix to reverse Polish notation must follow the operational hierarchy adopted for infix notation.
• First perform all arithmetic inside inner parenthesis, then inside outer parenthesis, and do multiplication and division operations before addition and subtraction operations.
• Consider the expression (A + B) * [C * (D + E) + F]
• First we evaluate the arithmetic inside the inner parenthesis (A + B) and (D +E).
• Next calculate the expression inside the square brackets.
• The multiplication of C * (D + E) must be done prior to the addition of F since multiplication has precedence over addition.
• The last operation is the multiplication of the two terms between the parenthesis and brackets.
• The converted expression is AB + DE + C * F + *
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Evaluation of Arithmetic Expression:
• Reverse Polish notation, combined with a stack arrangement of registers, is the efficient way for evaluating arithmetic expressions.
• First convert the arithmetic expression into its equivalent reverse Polish notation.
• The operands are pushed into the stack in which order they appear.
• The following microoperations are executed with the stack when an operation is entered:
the two top most operands in the stack are used for the operation, and
the stack is popped and the result of the operation replaces the lower operand.
• By pushing the operands into the stack continuously and performing the operations, the expression is evaluated in the proper order and the final result remains on top of the stack.
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Evaluation of Arithmetic Expression:• Consider the example
( 3 * 4 ) + ( 5 * 6 ) 34 * 56 * +
3 12
6
5
42
30
12
5
1212
4
3
43 +*65*
Instruction Formats:
• The bits of an instruction are divided into three fields.
Operation Code Field : specify the operation to be performed.
Address Field : designate a memory address or a processor register.
Mode Field : specify the operand or the effective address (Addressing Mode).
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Instruction Formats:• Three types of CPU organizations.
• The influence of the number of addresses on computer instructions
Consider the example X = (A + B)*(C + D)
• Three Address Instruction:
ADD R1, A, B R1 M[A] + M[B]
ADD R2, C, D R2 M[C] + M[D]
MUL X, R1, R2 M[X] R1 * R2
• Two Address Instruction:
MOV R1, A R1 M[A]
ADD R1, B R1 R1 + M[B]
MOV R2, C R2 M[C]
ADD R2, D R2 R2 + M[D]
MUL R1, R2 R1 R1 * R2
MOV X R1 M[X] R1
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• One Address Instructions:
LOAD A AC M[A]
ADD B AC AC + M[B]
STORE T M[T] AC
LOAD C AC M[C]
ADD D AC AC + M[D]
MUL T AC AC * M[T]
STORE X M[X] AC• Zero Address Instructions:
PUSH A TOS A
PUSH B TOS B
ADD TOS (A + B)
PUSH C TOS C
PUSH D TOS D
ADD TOS (C + D)
MUL TOS (C + D) * (A + B)
POP X M[T] TOS
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Addressing Modes:
• The way the operands are chose during program execution is dependent on the addressing mode of the instruction.
• The addressing mode specifies a rule for interpreting or modifying the address field of the instruction before the operand is actually referenced.
•Immediate Mode: In this mode the operand is specified in the instruction itself i.e., an immediate-mode instruction has an operand field rather than an address field.
• Immediate mode instructions are useful for initializing registers to a constant value.
• Example: MOVE #100, R1 R1 100
•Register Mode: In this mode the operands are in CPU registers.
• The particular register is selected from a register filed in the instruction.
• A k-bit field can specify any one of 2k registers.
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•Register Indirect Mode: In this mode the instruction specifies a CPU register whose contents give the address of the operand in memory.
• The advantage of a register indirect mode instruction is that the address field of the instruction uses fewer bits to select a register than a memory address directly.
•Autoincrement or Autodecrement Mode: This is similar to the register indirect mode except that the register is incremented or decremented after (or before) its value is used to access memory.
• This mode is used to refer to a table of data in memory.
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• Direct Address Mode: In this mode the effective address is equal to the address part of the instruction.
• The operand resides in memory and its address is given directly by the address field of the instruction.
•Indirect Address Mode: In this mode the address field of the instruction gives the address where the effective address is stored in memory.
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Direct Address Mode:
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Indirect Address Mode:
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Addressing Modes:•Indexed Addressing Mode: In this mode the content of an index register is added to the address part of the instruction to obtain the effective address.
• The index register is a special CPU register that contains an index value.
• The address field of the instruction defines the beginning address of a data array in memory.
effective address = address part of instruction + content of CPU register
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Addressing Modes:
•Relative address Mode: In this mode the content of the program counter is added to the address part of the instruction in order to obtain the effective address.
•Base Register Addressing Mode: In this mode the content of a base register is added to the address part of the instruction to obtain the effective address.
• The base register holds a base address and the address field of the instruction gives a displacement relative to the base address.
•Implied Mode: In this mode the operands are specified implicitly in the definition of the instruction.
• Examples: Compliment Accumulator
• All register-reference instructions that use an accumulator are implied-mode instructions.
• Zero address instructions in a stack-organized computer are implied-mode instructions since the operands are implied to be on top of the stack.
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Addressing Modes:
•Examples:
• MOVE # 100, R1; R1 100
• LOAD 2583, R1; R1 M(2583)
• STORE R1, 1024; M(1024) R1
• ADD 1000(R2), R0; R0 R0 + M(1000 + R2)
• ADD 1000(R2)+, R0; R0 R0 + M(1000 + R2) & R2 R2 + 1
• INCREMENT R1; R1 R1 + 1
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Typical Data TransferInstructions
Name Mnemonic
Load LD
Store ST
Move MOV
Exchange XCH
Input IN
Output OUT
Push PUSH
Pop POP
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Eight Addressing Modes for the Load Instruction
Mode AssemblyConvention
Register Transfer
Direct address LD ADR AC M[ADR]
Indirect address LD @ADR AC M[M[ADR]]
Relative address LD $ADR AC M[PC + ADR]
Immediate operand LD #NBR AC NBR
Index addressing LD ADR(X) AC M[ADR + XR]
Register LD R1 AC R1
Register indirect LD (R1) AC M[R1]
Autoincrement LD (RI) + AC M[R1],R1 R1 + 1
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Typical Logical and Bit Manipulation Instructions
Name Mnemonic
Clear CLR
Compliment COM
AND AND
OR OR
Exclusive-OR XOR
Clear carry CLRC
Set carry SETC
Compliment carry COMC
Enable interrupt EI
Disable interrupt DI
Typical Shift Instructions
Name Mnemonic
Logical shift right SHR
Logical shift left SHL
Arithmetic shift right SHRA
Arithmetic shift left SHLA
Rotate right ROR
Rotate left ROL
Rotate right through carry RORC
Rotate left through carry ROLC
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Typical Program ControlInstructions
Name Mnemonic
Branch BR
Jump JMP
Skip SKP
Call CALL
Return RET
Compare (by subtraction) CMP
Test (by ANDing) TST
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Conditional Branch Instructions
Mnemonic Branch condition Tested condition
BZ Branch if zero Z = 1
BNZ Branch if not zero Z = 0
BC Branch if carry C = 1
BNC Branch if no carry C = 0
BP Branch if plus S = 0
BM Branch if minus S = 1
BV Branch if overflow V = 1
BNV Branch if no overflow V = 0
Unsigned compare conditions (A – B)
BHI Branch if higher A > B
BHE Branch if higher or equal A B
BLO Branch if lower A < B
BLOE Branch if lower or equal A B
BE Branch if equal A = B
BNE Branch if not equal A B
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Conditional Branch Instructions
Mnemonic Branch condition Tested condition
Signed compare conditions (A – B)
BGT Branch if greater than A > B
BGE Branch if greater or equal A B
BLT Branch if lesser than A < B
BLE Branch if less or equal A B
BE Branch if equal A = B
BNE Branch if not equal A B
