REGISTER MANAGMENT TOOL

REGISTER MANAGMENT TOOL

Preformed by: Liat Honig Nitzan Carmel

Supervisor: Moshe Porian

Date: 29/1/2012 winter semester 2011

Duration: One semester

Middle presentation

Dress Specifications: Color: White Fabric: Lace Length: Long

Different designer - Different dress!

Motivation:

Background

Different teams use the register HSID

But each team creates their own registers code… WHY?!?

Automatically generates registers according to the required specification.

The Solution – a Register Management Tool

Creates unity in the registers VHD files

Enables REUSE

Saves money and resources

Manages the registers through the entire project

Creates documentation for the components created Leads to an organized – HSID

The Solution – a Register Management Tool

Alarms in case of incorrect input

Project Specifications

1. Writing a GUI interface through which the user will determine a variety of attributes.

GUI demo



GUI demo

2. Interactivity - The tool will provide feedback for user errors end will provide a summary output.



3. VHDL: VHD files1 Local Bus

Master

2 Simulation Environment

3


GUI demo



4. No special license will be needed to operate the tool, an EXE file will be given to the user.

3. VHDL: VHD files1 Local Bus

Master

2 Simulation Environment

3


GUI demo

General Description

Block

Local Bus

Chip data I/O

Register access

Register RegisterRegister

Block Block

Wishbone - open source protocol

Block C

Block A

Wish

bone

Mas

ter

clk_i

cyc_i

stb_iadr_idat_i

dat_oack_o

Stall_o

we_i Block B

Top Architecture

Block_A_reg_top Function_2

Function_3

Function_1

Block A

Reg_status_1

Wish

bone

Mas

ter

Reg_enable_2

func_err_3

reset clk

Reg Block Architecture

WB Slave

Reg1

Reg2

Reg3

Reg4

Priority Encoder

reg_chosen

4

WBMaster

Functional Block

Data from chosen register

Inputs from block

Outputs to block

Block_A_reg_top

Wishbone Slave Component

WB Slave

clk_i

wbs_cyc_i

wbs_stb_iwbs_we_iwbs_adr_i

wbs_dat_iwbs_dat_o

wbs_stall_o

wbs_ack_o

dout

din_ack

dout_valid

rd_en

din

addr

wr_en

Wishbone Slave Component

Idlewr_en=‘0’rd_en=‘0’

Read Cyclerd_en=‘1’

(wbs_cyc_i) ●(_ _wbs stb i)

(wbs_cyc_i) ●(_ _wbs stb i )

Active Cycle

wbs_stall_o=‘1’

Write Cyclewr_en=‘1’

wbs_we_iwbs_we_i

Cycle Finishedwbs_ack_o=‘1’

dout_validdin_ack

wbs_cyc_i

gen_reg Component

addr

din

wr_enrd_en

doutdin_ack

reg_chosendout_valid

gen_reg

clk reset

reg_in_b

Idlereg_chosen=‘0’

din_ack=‘0’dout_valid=‘0’

Read action

addr==reg addr

The Register is chosenreg_chosen=‘1’

Write action

addr==reg addr

rd_en wr_en

addr==reg addr addr==reg addr

gen_reg Component

Invalid Read Action

dout_valid=‘0’

Valid ReadAction

dout_valid=‘1’

Valid Write Action

din_ack=‘1’

Invalid write Actiondin_ack=‘0’

Register type is WRegister type is R/RW/COR/CONST

Register type is W/RW Register type is R/COR/CONST

Register Types • Read• Write• W/R• Clear on Read (COR)• Constant register

Wishbone Master

Functional BlockReg Block

Register Types• Read• Write• W/R• Clear on Read (COR)• Constant register

Wishbone Master



Wishbone Master



Wishbone Master


“0000”

“0000”


Wishbone Master


“0100”

“0100”


Wishbone Master


“0001”“0101”


Wishbone Master


rd_en = ‘1’“0000”

“0101”


Wishbone Master


“0000”

“1010”

“0000”


Wishbone Master


Generic Implementation



Simulation

COR register simulation

WB slave

addr = 0010COR

addr = 1110W/R

Encoder

Reg_chosen

4

WBMaster

Functional Block

.

.

.

.

“00000000”

“00000000”


WB slave

addr = 0010COR

addr = 1110W/R

Encoder

Reg_chosen

4

WBMaster

Functional Block

.

.

.

.

“00010000”

“00010000”


WB slave

addr = 0010COR

addr = 1110W/R

Encoder

Reg_chosen

4

WBMaster

Functional Block

.

.

.

.

“00000000”

“00010000”


WB slave

addr = 0010COR

addr = 1110W/R

Encoder

Reg_chosen

4

WBMaster

Functional Block

.

.

.

.

adr_i = 0010we_i =‘0’

“00000000”

“00000000”

dout =“00010000 ”dout_valid = ‘1’

din_ack = ‘0’

COR register waveform

0

Scenario: the block updates the data while the master reads

rd_en =‘1’

Data from block = 1


Results:

0

dout = “1”

Dout_valid = ‘1’

• updated data is transferred to the WB master• reg_data is cleared


0

Reg_data = “00000000 ”

Results:• updated data is transferred to the WB master• reg_data is cleared

W/R register simulation

WB slave

addr = 0010COR

addr = 1110W/R

Encoder

Reg_chosen

4

WBMaster

Functional Block

.

.

.

.“00000000”“00001101”


WB slave

addr = 0010COR

addr = 1110W/R

Encoder

Reg_chosen

4

WBMaster

Functional Block

.

.

.

.“00001101”


WB slave

addr = 0010COR

addr = 1110W/R

Encoder

Reg_chosen

4

WBMaster

Functional Block

.

.

.

.dout =“00001101 ”dout_valid = ‘1’

din_ack = ‘0’adr_i = 1110

we_i =‘0’

W/R register waveform

Scenario: WB master writes to register

din = 7 and then 8

wr_en = ‘1’ for 2 cycles


dout = 7 and then 8

din_ack = ‘1’ for 2 cycles

Results:• updated data from WB master is transferred to register• din_ack rises, indicating dout is updated• Register not influenced by data from block (reg_in_b)


Scenario: WB master tries to read from this register’s address (register address is 10)

Result: dout_valid rises to ‘1’

Dout_valid = ‘1’rd_en = ‘1 ’

addr = 10


Scenario: WB master tries to read from another register’s address (register address is 10)

Result: dout_valid is ‘0’

Dout_valid = ‘0’

rd_en = ‘1 ’

addr = 15

Project Steps1. Determine the implementation platform of the user interface and data

processing: Excel/MATLAB/C++/C#/JAVA .

2. Full characterization of the tool capabilities.

3. Learning the working environment (Wishbone protocol, advanced VHDL coding , MODELSIM simulation environment).

4. VHDL generic design and simulation.

5. Implementing the GUI and automatic VHDL generation.

6. Final MODELSIM and MATLAB Simulations.

In process

Schedule

The End

GUI Demonstration

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REGISTER MANAGMENT TOOL