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Index

FO4,99

active feedback, 21 active inductors, 34

Bode plots of active inductors, 36 cascode gyrator-C active inductors,

39 dynamic range, 47 floating gyrator-C active inductors,

41 gyrator-C active inductors, 35 multi-regulated cascode gyrator-C

active inductors, 40 noise of active inductors, 43 noise of gyrator-C active inductors,

44 noise of Q-enhanced gyrator-C ac­

tive inductors, 45 noise of transconductors, 43 Q-enhanced gyrator-C active induc­

tors, 40 regulated cascode gyrator-C active

inductors, 40 self-biased active inductors, 41

adjoint network, 4 analog and digital grounding, 238 attenuation constant, 63 avalanche multiplication, 248

back-end ballast resistors, 264 back-to-back integrating receiver, 199 balancing networks, 22 ballast resistors, 252 basic current amplifiers, 13 bipolar junction transistor, 248 bonding wires

maximum frequency, 216 bootstrapping, 21 Butterworth response, 27

capacitance of bonding pads, 55 cascode current amplifiers, 15

basic cascodes, 15 low-volt age cascodes, 19 multi-regulated cascodes, 17 pseudo-cascodes, 18 regulated cascodes, 17

characteristic impedance, 63 charge pumps, 172

Ahn-Allstot charge pump, 180 basic charge pumps, 176 Charge pump with perfect current

matching, 179 current-steering charge pumps, 176 Diff"erential charge pump with common-

mode feedback, 179 Hung-Kenneth charge pump, 180 nonidealities, 173 self-biased differential current-steering

charge pump, 178 class A integrating receivers, 198 class AB current amplifiers, 32 clock and data recovery using phase-

picking, 140 complex propagation constant, 63 conductivity of n-well resistors, 247 contact resistance, 51 critically terminated, 67 current branching, 25 current-controlled ring oscillators, 189

current-starve delay cell, 189 Mansuri-Yang delay cell, 190

current-current feedback, 31 current-mode circuits, 1 current-mode integrating receiver, 200

reset phase, 202 current-mode loop filter, 191 current-mode multiplexers, 104 current-mode phase-locked loops, 191 current-mode signaling

288 INDEX

advantages, 82 current-steering multiplexers, 102 cut-off frequency of transconductors, 35

Data recovery using integration, 195 decoupling capacitors, 234 diffusion equation, 60 Diodes, 250 drain contact-gate spacing, 252

electrical signaling current-mode incremental signaling,

91 current-mode signaling, 89 fully differential signaling, 85 low-voltage differential signaling, 90 pseudo-differential signaling, 86 single-ended signaling, 84 unipolar current-mode signaling, 89 voltage-mode incremental signaling,

87 voltage-mode signaling, 84

electro-static discharge, 243 ESD protection circuit

Domino nMOS MFT, 265 ESD protection circuits

basic ESD protection circuits, 257 challenges in ESD Protection, 257 decreasing-size distributed ESD pro­

tection scheme, 262 distributed ESD protection circuits,

260 ESD protection with negative capac­

itors, 262 poly back-end ballast with segmen­

tation, 263 polysilicon diodes, 259 primary ESD protection stage, 257 scaling of gate oxide thickness, 258 scaling of junction depth, 258 secondary ESD protection stage, 257 soft-grounded-gate nMOS MFT, 264 stacked diodes, 260 uniform condition, 264

ESD protection principles, 246 current-limiting of n-well resistors,

247 ESD sources, 244

charged device model, 245 finger model, 244 human body model, 244 machine model, 245

first-generation current conveyers, 3 fringe capacitance of wire channels, 54 full-clock low-power DAC, 118

voltage-coupling capacitor, 254 volt age-holding resistor, 254

gate-grounded nMOS transistors, 251 grounding in mixed-Mode circuits, 236

half-clock low-power DAC, 117

ideal current-mode circuits, 3 ideal voltage-mode circuits, 2 impact ionization, 247 impedance matching, 75

active impedance matching, 75 digital trimming, 77 dynamic clamping, 78 low-power active impedance match­

ing, 77 passive impedance matching, 75 self-regulated active impedance match­

ing, 78 symmetric load, 76

improved Wilson current amplifier, 17 inductance of wire channels, 55 inductor series peaking, 28 input impedance of transmission lines, 65 integrating receiver

partial steering of tail current, 198 threshold state of logic state, 195 voltage-mode integrating receiver,

196 integration receiver

voltage comparator, 196 integration time, 195 inter-reciprocal, 4

Lee's multiplexer, 102 Lorezen force, 51 low input-capacitance current amplifiers,

20 low-voltage silicon-controlled rectifier, 256

maximum flat response, 31 Miller capacitances, 7 Miller effect, 7 Miller poles, 7 modeling of wire channels, 59

distributed RC model of wire chan­nels, 60

Elmore model of wire channels, 61 lumped RC model of wire channels,

59 transmission-line model of wire

channels, 62 modified silicon-controlled rectifier, 256 mutual capacitance of wire channels, 54 mutual inductance, 56

gate-coupled nMOS transistors, 253 n+/p-well diodes, 250

INDEX 289

n-well ballast resistors, 253 n-well resistors, 250 non-uniform scaling, 50

open lines, 64 over terminated, 67

p+/n-well diodes, 250 parallel data links, 95 partial inductance, 58 partial mutual-inductance, 58 partial self-inductance, 58 phase constant, 63 phase noise of oscillators, 204

Dai-Harjani model, 209 Hajimiri-Lee model, 207 impulse sensitivity function, 207 Lesson model, 204 Razavi model, 206 single-side-band phase noise, 204 Weigandt model, 205

phase-frequency detectors, 155 XOR phase detectors, 156

phase-locked loops damping factor, 210 pole resonant frequency, 210

Phase-picking 2x-oversampling clock and data re­

covery, 148 3x-oversampling clock and data re­

covery, 150 4x-oversampling clock and data re­

covery, 152 oversampling ratio, 141

Phase-tracking clock and data recovery using phase-

tracking, 154 phase-tracking, 154

conventional D-Flipflop bang-bang phase detector, 164

D-flipflop phase-frequency detector, 159

dynamic D-flipflop phase detector, 170

Half-rate phase detector, 162 improved D-flipflop bang-bang phase

detector, 165 improved XOR bang-bang phase de­

tector, 169 RS phase detectors, 157 Sample-and-hold phase detector,

161 Two-XOR phase detector, 160

pre-emphasis, 113 current-mode direct pre-emphasis,

121 current-mode pre-emphasis, 114

power-area efficient current-mode pre-emphasis, 115

voltage-mode pre-emphasis, 114 pseudo-nMOS multiplexers, 101

resistance of wire channels, 50 resistor series peaking, 27 Reuhli loop, 58

Samplers, 143 advantages of oversampling clock

and data recovery, 142 evaluation phase, 144 hold time, 144 maximum time window, 142 minimum input, 144 Moon-Kang sampler, 148 Poulton-Dally-Tell sampler, 145 pre-charge phase, 144 regenerative sense amplifier, 143 setup time, 144 setup-hold time, 141, 144 Yang-Horowitz sampler, 146

scaling of metal interconnects, 50 second-generation current conveyors, 3 self-inductance, 56 serial data links, 95

advantages, 97 serial links

advantages, 97 class A current-mode drivers, 109 class AB current-mode drivers. 111 drivers, 106 inverter drivers, 107 low-volt age differential-signaling drivers,

109 open-drain drivers, 107 serialization, 98

serialization multi-phase single-stage scheme, 99 single-phase multi-stage scheme, 98

sheet resistance, 51 shorted lines, 64 silicon-controlled rectifiers, 254 skin depth, 51 Slew rate, 7 snap back, 249 snapback holding voltage, 249 source contact-gate spacing, 252 stub, 55 substrate grounding, 239 substrate modeling, 237 supply voltage sensitivity, 9 switching noise, 217

analysis of switching noise, 220 efi'ects of switching noise, 218 noise margins, 218

switching noise analysis

290

a-power law approach, 222 application specific device modeling

approach, 231 improved a-power law approach,

225 partial buffer switching approach­

ing, 227 peak switching noise approach, 229 triangle waveform approach, 221

switching noise reduction techniques, 232 balanced drivers, 236 pre-skewing, 233

Tellegen's theorem, 4 termination schemes

AC parallel termination, 74 parallel termination, 74 series termination, 72 Thevenin termination, 75

termination schemes of transmission lines, 72

thermal breakdown, 249 thermal conductivity of silicon, 250 thermal conductivity of silicon dioxide,

250 transmission line effects, 67 transmission-gate multiplexers, 100 Transmitters

ADC-based serial link transmitter, 123

INDEX

current-mode area-power efficient 4PAM serial link transmitter, 132

current-mode class A 2PAM serial link transmitter, 124

current-mode Class AB 2PAM serial link transmitter, 124

current-mode power-insensitive Class AB 2PAM serial link transmit­ter, 126

under terminated, 67

voltage-controlled ring oscillators, 181 cross-coupled delay cells, 184 cross-coupled delay cells with active

inductor load, 184 Huang delay cells, 189 Park-Kim delay cells, 185 Park-Kim delay cells with active in­

ductor load, 187 source-coupled delay cells, 182 source-coupled delay cells with ac­

tive inductor load, 184 voltage-mode circuits, 1 voltage-mode integration receiver, 196

Yang's multiplexer, 103

About the Author

Fei Yuan received the PhD. degree in electrical engineering from University of Waterloo, Canada in October 1999. He is currently an Associate Professor in the Department of Electrical and Computer En­gineering, Ryerson University, Toronto, Ontario, Canada. He is the co-author of the book Computer Methods for Analysis of Mixed-Mode Switching Circuits (with Ajoy Opal, Kluwer Academic Publishers, April 2004), and the author / co-author of over 80 refereed journal and confer­ence papers in the field of mixed-mode circuits. Dr. Yuan is the recipient of the Ryerson Research Chair award from Ryerson University in 2005, the Research Excellence award from the Faculty of Engineering, Archi­tecture, and Science of Ryerson University in 2004, the doctoral scholar­ship from Natural Science and Engineering Research Council of Canada in 1997, and the Teaching Excellence award from Changzhou Institute of Technology, Jiangsu, China in 1988. He is a registered professional engineer in the province of Ontario, Canada and a senior member of IEEE.

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