Reduction of Power by Using Multi-bit Flip-flops for Vlsi Applications

8/9/2019 Reduction of Power by Using Multi-bit Flip-flops for Vlsi Applications

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REDUCTION OF POWER BY USING MULTI-BIT FLIP-FLOPS FOR VLSI APPLICATIONS

INTRODUCTION

Because of the !o"#$e$ce of co" act e%ect!o$#c #te"s& %o' o'e! f!a"e'o!(

has u%%e) #$ "o!e co$s#)e!at#o$ %ate%*+ As tech$o%o,* a) a$ces& a s*ste"-o$-a-ch#

.SOC/ co$f#,u!at#o$ ca$ co$ta#$ "o!e a!ts that !o" t a h#,he! o'e! )e$s#t*+ Th#s

"a(es o'e! )#ss# at#o$ ach#e e the cutoff o#$ts of 'hat ac(a,#$,& coo%#$, o! othe!

f!a"e'o!( ca$ he% + Dec!eas#$, the o'e! co$su" t#o$ ca$ u ,!a)e 0atte!* %#fe as

'e%% as ca$ e a)e the o e!heat#$, #ssue& 'h#ch 'ou%) 0u#%) the %e e% of t!ou0%e of

ac(a,#$, o! coo%#$, co$se1ue$t%*& the thou,ht of o'e! co$su" t#o$ #$ co" %e2

SOCs has tu!$e) #$to a hu,e test to )es#,$e!s+

I$ a))#t#o$& #$ a) a$ce) VLSI %a$s& o'e! co$su"e) 0* c%oc(#$, has ta(e$ a

s#,$#f#ca$t #ece of the e$t#!e %a$ a!t#cu%a!%* fo! those )es#,$s us#$, )ee %* sca%e)

CMOS tech$o%o,#es+ I$ th#s 'a*& a fe' st!ate,#es ha e 0ee$ !o ose) to )ec!ease the

o'e! co$su" t#o$ of c%oc(#$,+ Fo! a ,# e$ %a$ that the a!eas of the ce%%s ha e 0ee$

f#!"& the o'e! co$su"e) 0* c%oc(#$, ca$ 0e )ec!ease) fu!the! 0* su0st#tut#$, a fe'

f%# -f%o s '#th "u%t#-0#t f%# -f%o s+ At c%oc( t!ee s*$thes#s& %ess $u"0e! of f%# -f%o s

#" %#es !e)uce) $u"0e! of c%oc( s#$(s+ The!efo!e& the !esu%t#$, c%oc( s*ste" uses

!e)uce) o'e! co$su" t#o$ a$) ut#%#3es %ess !out#$, !esou!ce+

Fu!the!"o!e& s"a%%e! f%# -f%o s a!e su0st#tute) 0* 0#,,e! "u%t#-0#t f%# -f%o s4

,a),et a!#et#es #$ the !e%at#$, c#!cu#t ca$ 0e o!)e!%* !e)uce)+ As the CMOS

tech$o%o,* !o,!esses& the )!# #$, ca ac#t* of a$ #$ e!te!-0ase) c%oc( 0uffe!

#$c!e"e$ts fu$)a"e$ta%%*+ The a0#%#t* to )!# e a c%oc( 0uffe! ca$ 0e assesse) 0* the

1ua$t#t* of %east "easu!e) #$ e!te!s that #t ca$ )!# e o$ a ,# e$ !#s#$, o! fa%%#$, t#"e+

Due to th#s se$sat#o$& a fe' f%# -f%o s ca$ #" a!t a co""o$ c%oc( 0uffe! to e a)e

u$$ecessa!* 'aste of o'e!+

F#,+5+5 sho's the 0%oc( )#a,!a"s of 5- a$) 6-0#t f%# -f%o s+ If 'e !e %ace the

t'o 5-0#t f%# -f%o s as sho'$ #$ F#,+5+5 0* the 6-0#t f%# -f%o as sho'$ #$ F#,+5+6& the

tota% o'e! co$su" t#o$ ca$ 0e !e)uce) 0ecause the t'o 5-0#t f%# -f%o s ca$ sha!e the

sa"e c%oc( 0uffe!+

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Fig 1.1 Two single bit flip-flops before merging and after merging

I$ a$* case& the a!eas of so"e f%# -f%o s 'ou%) 0e cha$,e) afte! th#s

su0st#tut#o$& a$) afte!'a!) the '#!e %e$,ths of $ets co$$ect#$, #$s to a f%# -f%o a!e

a))#t#o$a%%* cha$,e)+ To a0sta#$ f!o" )a"a,#$, the t#"#$, #" e!at# es& 'e co$f#$e

that the '#!e %e$,ths of $ets u$#t#$, #$s to a f%# -f%o ca$8t 0e %o$,e! tha$ )eta#%e)

a%ues afte! th#s !oce)u!e+ O$ the othe! ha$)& to e$su!e that a$othe! f%# -f%o ca$ 0e ut #$s#)e the )es#!e) !e,#o$& 'e %#(e'#se $ee) to co$s#)e! the a!ea ca ac#t* of the

!e,#o$+

The o'e! %a*s a s#,$#f#ca$t a!t #$ a$* )es#,$ o$e "a* $ee) to focus o$

o'e! !e)uct#o$ st!ate,#es+ To )#"#$#sh the o'e! co$su" t#o$& a %ot of %o'- o'e!

%a$ !oce)u!es ha e 0ee$ !ese$te)& fo! e2a" %e& c%oc( ,at#$,& o'e! ,at#$, "a(#$,

"u%t#-su %*- o%ta,e %a$s& )*$a"#c o%ta,e e! f!e1ue$c* sca%#$,& a$) "#$#"#3#$,

c%oc( s*ste"+ A"o$, these !oce)u!es& "#$#"#3#$, a$) fus#$, the c%oc( s*ste" #sesse$t#a% #$ !e)uc#$, o'e! co$su" t#o$ of a Soc .S*ste" o$ Ch# /+ B* )#"#$#sh#$,

the o'e! #$ c#!cu#t )es#,$ #t $atu!a%%* !e)uces the "a$*-s#)e) 1ua%#t* a$) '#!e

%e$,th+ I$ th#s "a$$e!& )#st#$ct# e s*ste"s ha e 0ee$ !o ose) 96:& 9;: to )es#,$ a

!e)uce) o'e! co$su" t#o$ )es#,$+

The o'e! ha) 0ee$ e2 a$)e) fo! )# e!se sta,es a!e stat#c a$) )*$a"#c

o'e!+ I$ )*$a"#c o'e!& cha$,e #$ #$ ut s#,$a% at )#st#$ct# e !at#o$a%e %e e% '#%%

!esu%t #$ e2cha$,#$, a$) sho!t out fo!ce #$ the co$f#,u!at#o$+ I$ stat#c fo!ce& #t )oes$8tha e a$* #" act of %e e% cha$,e #$ #$fo!"at#o$ a$) *#e%)+ The Mu%t#-0#t F%# -f%o



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.MBFF/ #s a successfu% o'e! !e)uct#o$ !oce)u!e+ It #s ut#%#3e) to )ec!ease the

1ua$t#t* of F%# F%o a'a* sta,e+ Se$)#$, $u"e!ous 0#ts of #$fo!"at#o$ '#th s#$,%e

FF ut#%#3#$, s#$,%e c%oc( u%se #s ca%%e) MBFF+ The #)ea of MBFF #s !ese$te) #$

a))e! a %#cat#o$ 'h#ch #s ut#%#3e) to )#"#$#sh the 1ua$t#t* of FFs 'h#ch a!e $ot

e" o'e!e) #$ the c#!cu#t out%#$e+ M0ffs ha e a) a$ta,e o e! SBFF as "o!e "o)est

out%#$e 3o$e& co$t!o%%a0%e c%oc(& %ess )e%a* o$ c%oc( s*ste" a$) effect# e use of

!out#$, !esou!ces+

The 'o!(#$, of "u%t#-0#t f%# f%o #s sa"e as s#$,%e-0#t f%# -f%o & at 'hate e!

o#$t the c%oc( ,ets )*$a"#c state f%# f%o %atches a%% )ata to *#e%)+ Fo! #)%e state the

f%# f%o ho%)s the #$fo!"at#o$+ The fu$)a"e$ta% st!uctu!e of "u%t#-0#t f%# fa#%u!e #s

,# e$ #$ F#,+ 5& #t )e"o$st!ates that as o ose) to ut#%#3#$, s#$,%e 0#t FF 'e ca$su %a$t #$to "u%t# 0#t FF as 6-0#t FF&


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Fig 1.2 8 bit flip flop

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EXISTING METHOD

2.1 NEED FOR LOW POWER DESIGN

I$ the $ea! the 0e,#$$#$, 5>?@ s sche"#$, )#,#ta% c#!cu#ts fo! soa!#$, s ee)

a$) 0a!e "#$#"u" a!ea 'e!e the "a#$ )es#,$ co$st!a#$ts+ Most of the EDA too%s 'e!e

)e%#0e!ate )#st#$ct# e%* to "eet th#s c!#te!#o$+ Po'e! co$su" t#o$ 'as a%so a

e%e"e$t of the )e #se !o,!ess#o$ 0ut $ot e!* )#sce!$#0%e+ The %esse$#$, of

a!ea of )#,#ta% c#!cu#ts #s $ot as 0#, #ssue to)a* fo! the !easo$ that '#th $e' IC

"a(#$, tech$#1ues& "a$* "#%%#o$s of t!a$s#sto!s ca$ 0e f#t #$ a s#$,%e IC+ O$ the

othe! ha$)& )'#$)%#$, s#3es of c#!cu#ts ha e a e) the 'a* fo! co$)e$se) o'e!

co$su" t#o$ #$ o!)e! to ha e a$ 'ho%esa%e 0atte!* %#fe+ A%so #$ su0"#c!o$

tech$o%o,#es& the!e #s a co$st!a#$t o$ the !o e! !u$$#$, of c#!cu#ts )ue to heat

,e$e!ate) 0* o'e! )#ss# at#o$+ Ma!(et "#%#ta!* a!e se e!e %o' o'e! fo! $ot o$%*

'e%% a,a#$ %#fe 0ut a%so t!ust'o!th#$ess& o!ta0#%#t*& !out#$e& cost a$) t#"e to "a!(et+

Th#s #s e!* t!ue #$ the f#e%) of e!so$a% co" ut#$, )e #ces& '#!e%ess co$$ect#o$s

s*ste"s& ho"e a"use"e$t s*ste"s& 'h#ch a!e 0eco"#$, o u%a! $o'-a-)a*s+

De #ces that a!e a%so use) fo! h#,h- e!fo!"a$ce co" ut#$, a!t#cu%a!%* $ee) to

s1ua$)e! %ess o'e! to fu$ct#o$ f#tt#$,%* a$) fo! a %o$, e!#o) of t#"e +

ee #$, a%% these #$ "#$)& %o' o'e! )es#,$ has ,!o' to 0e o$e of the "ost #" o!ta$t

)es#,$ a!a"ete!s fo! VLSI .Ve!* La!,e Sca%e I$te,!at#o$/ s*ste"s+

2.1.1 DESIGN FLOW WITH AND WITHOUT POWER

A to -)o'$ co""o$ %ace VLSI )es#,$ co"e u to #s #%%ust!ate) #$ F#,+ 6+5+

The F#,+ su""a!#3es the f%o' of ste %a))e! that #s !e1u#s#te to fo%%o' f!o" a s*ste"

%e e% %a$ to the h*s#ca% )es#,$+ The a !oach 'as "ea$t at !ec#ta% o t#"#3at#o$ a$)

a!ea "#$#"#3at#o$+ O$ the othe! ha$)& #$t!o)uc#$, the th#!) st!#ctu!e of o'e!

)#ss# at#o$ f#$#she) the )es#,$e!s to a%te! the ou! as sho'$ #$ the !#,ht-ha$) s#)e of

the F#,+ 6+5+I$ each of the )e #se %e e%s a!e t'o #" e!at# e o'e! facto!s& $a"e%*

o'e! o t#"#3at#o$ a$) o'e! assess"e$t+ Po'e! o t#"#3at#o$ #s )ef#$e) as the

!o,!ess#o$ of o0ta#$#$, the 0est )e #se e%o1ue$t the )e #se co$st!a#$ts a$) )e o#)

of #o%at#$, )es#,$ st# u%at#o$+ I$ o!)e! to "eet the )e #se a$) !e1u#s#te as #!at#o$&

a o'e! o t#"#3at#o$ "o)us o e!a$)# o$%* o$e of #ts (#$) to that a%t#tu)e shou%)

0e #$ e" %o*"e$t+ Po'e! est#"at#o$ #s )ef#$#te as the cou!se of act#o$ of

"a$# u%at# e o'e! a$) e$e!,* )e0auche) '#th a ce!ta#$ e$t#t%e"e$t of accu!ac* a$)



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at o%es a a!t hase of the )e #se !o,!ess#o$+ Po'e! est#"at#o$ tech$#1ues a !a#se

the effect of a!#ous o t#"#3at#o$s a$) )e #se "o)#f#cat#o$s o$ o'e! at o%es a a!t

a0st!act#o$ %e e%s+

Ge$e!a%%* a )e #se e!fo!"s a o'e! o t#"#3at#o$ !u$, f#!st a$) the$ a o'e! est#"at#o$ !u$,& 0ut su!!ou$)e) 0* a f#!" )e #se %e e% the!e #s $o u$a"0#,uous )e #se

!oce)u!e+ Each )e #se %e e% #$c%u)es a %a!,e ,athe!#$, of %o' o'e! tech$#1ues+

Each oss#0%* '#%% !esu%t #$ a "o"e$tous )ec%#$e of o'e! )#ss# at#o$+ o'e e!& a

f#!" !ec# e of %o' o'e! tech$#1ues "a* ,o #$ f!o$t to hea%th#e! )o"#$o effect tha$

a$othe! se!#es of tech$#1ues+

Ge$e!a%%*& o'e! #s o0sess# e 'he$ ca ac#to!s #$ the c#!cu#ts a!e e#the!

cha!,e) o! )#scha!,e) )ue to s'#tch#$, t!#c(s+ So at h#,he! %e e%s of a st!uctu!e th#s o'e! )#ss# at#o$ #s !ese! e) 0* !e)uc#$, the s'#tch#$, t!#c(s 'h#ch #s f#$#she) 0*

shutt#$, )o'$ )o'$ o!t#o$s of the s*ste" 'he$ the* a!e $ot %oo(e)-fo!+ La!,e VLSI

c#!cu#ts co$ta#$ )#ffe!e$t 'o!(#$,s %#(e a !ocesso!& a fu$ct#o$a% u$#t a$) co$t!o%%e!s+

The #$#t#at# e of o'e! !e)uct#o$ #s to sto a$* of the 'o!(#$,s of the !ocesso! 'he$

the* a!e $ot $ee)e) so that %ess o'e! '#%% 0e )e0auche) 'he$ the !ocesso! #s #$

co""#ss#o$+

The f#!st se"#co$)ucto! ch# s a !ehe$)e) t'o t!a$s#sto!s each+ Su0se1ue$t

a) a$ces su %e"e$ta!* "o!e t!a$s#sto!s& a$) as a u shot& "o!e c!eatu!e fu$ct#o$s o!

s*ste"s 'e!e #$co! o!ate) o e! t#"e+ The f#!st #$te,!ate) c#!cu#ts he%) o$%* a fe'

)e #ces& e!ha s as "a$* as te$ )#o)es& t!a$s#sto!s& !es#sto!s a$) ca ac#to!s& "a(#$, #t

oss#0%e to fa0!#cate o$e o! "o!e %o,#c ,ates o$ a s#$,%e )e #ce+ No' ($o'$

!es ect# e%* as s"a%%-sca%e #$te,!at#o$ .SSI/& #" !o e"e$ts #$ tech$#1ue %e) to

)e #ces '#th hu$)!e)s of %o,#c ,ates& ($o'$ as "e)#u"-sca%e #$te,!at#o$ .MSI/+

Fu!the! #" !o e"e$ts %ea) to %a!,e-sca%e #$te,!at#o$ .LSI/& #+e+ s*ste"s '#th ats%#,htest a thousa$) %o,#c ,ates+ Cu!!e$t tech$o%o,#es ha e e$cou!a,e) fa!-f%u$, ast

th#s "a!( a$) to)a*8s "#c!o !ocesso!s ha e %oa)s of "#%%#o$s of ,ates a$) 0#%%#o$s of

e!so$a,e t!a$s#sto!s+

At o$e occas#o$ the!e 'as a$ sta0 to $a"e a$) !e,u%ate a$ asso!t"e$t of %e e%s

of %a!,e-sca%e #$te,!at#o$ 0e*o$) VLSI+ Te!"s %#(e u%t!a %a!,e sca%e #$te,!at#o$

.ULSI/ 'e!e 'o!$+ But the ,#,a$t#c $u"0e! of ,ates a$) t!a$s#sto!s e2#st#$, o$



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co""o$ )e #ces has !e$)e!e) such f#$e )#st#$ct#o$s "oot+ Te!"s o!te$tous ,!eate!

tha$ VLSI %e e%s of #$te,!at#o$ a!e $o %o$,e! #$ '#)es !ea) use+

Fig 2.1: VLSI design flow

2.2 RELATIONSHIP BETWEEN DIFFERENT ABSTRACTION

LEVELS

The !e%at#o$sh# 0et'ee$ )e #se a0st!act#o$ %e e% a$) o'e! est#"at#o$

tech$#1ues #s sho'$ as F#, 6+6+ The o'e! est#"at#o$ at to %e e% #s a ,oo) )ea% "o!e

!a #)%*& 0ut the accu!ate$ess '#%% 0eco"e 'o!se )ue to the so"e )e,!ee of )e #se

#$fo!"at#o$ a $u"0e! of CAD tech$#1ues fo! o'e! est#"at#o$ at %o'e! %e e%s of

a0st!act#o$& such as t!a$s#sto!-%e e% 96-


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2.3.2 DYNAMIC POWER

D*$a"#c o'e! #s the o'e! )e0auche) 'h#%st the c#!cu#t #s act# e+ A

c#!cu#t #s act# e a$*t#"e the o%ta,e o$ $et cha$,es )ue to a 1ua$t#t* of s u! a %#e)

to the c#!cu#t+ I$ su %e"e$ta!* 'o!)s& )*$a"#c o'e! )#ss# at#o$ #s cause) 0* thecha!,#$,+ Fo! the !easo$ that o%ta,e o$ a$ #$ ut $et ca$ cha$,e '#thout u$a o#)a0%*

co$se1ue$t#a% #$ %o,#c a%te!at#o$ #$ the out ut& )*$a"#c o'e! ca$ 0e )#ss# ate)

e e$ at 'hat t#"e a$ out ut $et )oes$ t cha$,e #ts %o,#c state+ Th#s #ece of )*$a"#c

o'e! )#ss# at#o$ #s the co$se1ue$ce of cha!,#$, a$) )#scha!,#$, a!as#t#c

ca ac#ta$ces #$ the c#!cu#t+

D*$a"#c o'e! of a c#!cu#t #s se%f- ossesse) of

a/ S'#tch#$, o'e!

0/ I$te!$a% o'e!

2.3.2.1 SWITCHING POWER

The s'#tch#$, o'e! of a !ous#$, ce%% #s the o'e! )e0auche) 0* the cha!,#$,

a$) )#scha!,#$, of the %oa) ca ac#ta$ce at the a"ou$t !o)uce) of the ce%%+ The fu%%

a"ou$t %oa) ca ac#ta$ce at the out ut of a )!# #$, ce%% #s the tott#$, u of the $et a$)

,ate ca ac#ta$ces o$ the ou!#$, a"ou$t !o)uce)+ The cha!,#$, a$) )#scha!,#$, a!eu shot of %o,#c t!a$s#t#o$s+ S'#tch#$, o'e! #$c!eases as %o,#c t!a$s#t#o$s #$c!ease+

The!efo!e& the s'#tch#$, o'e! of a ce%% #s a ut#%#t* of #$ coo e!at#o$ the tota% %oa)

ca ac#ta$ce at the ce%% a"ou$t !o)uce) a$) the e%oc#t* of %o,#c t!a$s#t#o$s+

S'#tch#$, o'e! co" !#ses ?@->@ e!ce$t of the o'e! )#ss# at#o$ of a$ #,o!ous

CMOS c#!cu#t+

2.3.2.2 INTERNAL POWER

I$-house o'e! #s a$* o'e! )#ss# ate) su!!ou$)e) 0* the 0o!)e! %#$e of

a ce%%+ Du!#$, s'#tch#$,& a c#!cu#t )#ss# ate #$te!$a% o'e! 0* the cha!,#$, o!

)#scha!,#$, of a$* to 0e ha) ca ac#ta$ces #$-house to the ce%%+ I$-house o'e!

#$c%u)es o'e! )e0auche) 0* a "o"e$ta!* sho!t c#!cu#t stuc( 0et'ee$ the P a$) N

t!a$s#sto!s of a ,ate& ca%%e) sho!t-c#!cu#t o'e!+

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Ne e!the%ess& #t has the "ost a'fu% 0ecause #t !e1u#!es too to a %a!,e

e2te$t co" utat#o$ !esou!ces co" ete$ce a$) #t ta(es too to a ,!eat e2te$t t#"e

o$ 0eha%f of s#"u%at#o$+ Gate-%e e% o'e! s#"u%at#o$ tech$#1ues 0e ca a0%e of "a(e

a a#%a0%e a 'e%% a,a#$ t!a)e-off stuc( 0et'ee$ accu!ac* a$) eff#c#e$c*& 0ut #t oss#0%*

'#%% st#%% cost a %ot of !e)es#,$ t#"e to ,et to the 0otto" of o'e! !o0%e"s at 'hat

t#"e the )es#,$ #s 0efo!e $o' at ,ate-%e e%+ Co" a!e) to othe! a !oaches& h#,h-%e e%

o'e! est#"at#o$ #s "uch ha!)e! to o0ta#$ h#,h accu!ate !esu%ts& 0ecause the

)eta#% #$ o!)e! of the )es#,$ #s 0efo!e $o' %oss too a %a!,e a"ou$t+ o'e e!& #f the

accu!ac* ($o' ho' to 0e su e!#o! to a$ u to sta$)a!) !e,#o$& h#,h %e e% o'e!

est#"at#o$ tech$#1ues )ete!"#$at#o$ )e e%o #$to e!* fu$ct#o$a% 0ecause 'e ca$

0eco"e a'a!e of the o'e! !o0%e"s to a ,!eat e2te$t ea!%#e! a$) "o!e hast#%*+ I$

fo%%o'#$, sect#o$& the h#,h-%e e% o'e! est#"at#o$ '#%% o'e! 0e #$t!o)uce)+

2. HIGH-LEVEL POWER ESTIMATION

I$ a!!a$,e to (ee a'a* f!o" !ec#ous !e)es#,$ ste s fo! such co" %e2 )e #se&

)es#,$e!s e$co" ass to est#"ate the o'e! co$su" t#o$ at su e!#o! )es#,$ sta,e

to a !ec#ate 'hethe! su %e"e$ta!* #" !o e"e$ts a!e !e1u#s#te+ It #s u$ !act#ca%

fo! SOC )es#,$s to use the %o$,-esta0%#she) SPICE-%#(e) s#"u%at#o$ at

t!a$s#sto!-%e e% as "e$t#o$e) #$ Cha te! 5+ Co$se1ue$t%*& a $u"e!a% of CADtech$#1ues e$co" ass 0ee$ %a$$e) fo! ,ate-%e e% o'e! est#"at#o$+ o'e e!& 'he$

the )e #se has 0ee$ #" %e"e$te) to the ,ate %e e%& #t "a* at a sta$)st#%% too %ate

o! too e2 e$s# e to a) a$ce the )e #se fo! o'e! co$su" t#o$ !o0%e"s+ It

#" %#es that h#,h-%e e% o'e! assess"e$t tech$#1ues a!e #ta% fo! )es#,$#$, such a

co" %e2 )es#,$ to cu!ta#% !e)es#,$ c*c%es+

Fig 2.&: ' %sage of high-le!el power model



12/55


A $u"0e! of h#,h-%e e% o'e! assess"e$t tech$#1ues ha e 0ee$ !o ecte) as

su! e*e) #$+ The* a!e ha0#tua%%* c%ass#f#e) as to -)o'$ a$) 0otto"-u st*%es+ I$ the

to -)o'$ tech$#1ues& a cou!se #s s ec#f#e) as a Boo%ea$ fu$ct#o$ '#thout facto!

#$fo!"at#o$ of the c#!cu#t co$f#,u!at#o$+ To )o'$ "etho)s ha0#tua%%* use a

1ua$t#t* of a0st!act "easu!e"e$ts such as e$t!o * to "easu!e of the tota% of

#$fo!"at#o$ a%te! as the o'e! co$su" t#o$ sta$)a!)s + The* 'ou%) 0e co$st!uct# e

'he$ )es#,$#$, a %o,#c 0%oc( that 'as $ot u$t#% that t#"e )es#,$e)+

#,h-%e e% o'e! est#"at#o$ tech$#1ues ca$ 0e #$ the !e,#o$ of )# #)e)

#$to t'o cate,o!#es to )o'$ a$) 0otto"-u + At ho"e the to -)o'$ tech$#1ues& a

co"0#$at#o$a% c#!cu#t #s !ec#se $o "o!e tha$ as a Boo%ea$ fu$ct#o$ '#thout #$ tu!$ o$

the c#!cu#t #" %e"e$tat#o$+ No!"a%%*& the* )ete!"#$at#o$ a !o2#"at#o$ the s'#tch#$, act# #t* of

c#!cu#ts 0* "ea$s of e$t!o *+ E$t!o * #s a cha!acte!#3at#o$ of a !a$)o"

ca !#c#ous o! a !a$)o" !o,!ess#o$ 'h#ch #s co""o$%* use) #$ the #$ se1ue$ce

theo!* as a "easu!e of #$fo!"at#o$-ca!!*#$, ca ac#t*+

Fig 2.(: )igh le!el power modeling on ept

These (#$) of to -)o'$ tech$#1ues a!e usefu% 'he$ o$e #s )es#,$#$, a

%o,#c 0%oc( that 'as $ot !e #ous%* !e"e)#tate) 0ecause the* 0e ca a0%e of



13/55


!o #)e a #!!e,u%a! "easu!e"e$t o$ the su0 ect of the t!e$) of o'e!

co$su" t#o$ soo$e! tha$ #" %e"e$tat#o$+ o'e e!& the* oss#0%* '#%% $ot ha e

e!* ,oo) accu!ac* o'#$, to the %ac( of #" %e"e$tat#o$ a!t#cu%a!s+

I$ )#s a!#t*& 0otto"-u "etho)s a!e usefu% as soo$ as !eus#$, a !e #ous%*)es#,$e) %o,#c 0%oc( so '#th the #$te$t#o$ of a%% e2haust# e #$te!$a% st!uctu!es of

the c#!cu#t a!e ac($o'%e),e)+ A o'e! "ac!o-"o)e% st!e$,th of cha!acte! 0e

0u#%t fo! such %o,#c 0%oc(s #$ th#s so!t of "etho)s+ Whe$ th#s %o,#c 0%oc( #s

use) #$ a$ a))#t#o$a% a %#cat#o$& the a$a%o,ous o'e! "ac!o-"o)e% 0e ca a0%e of

0e !ec*c%e) to est#"ate the o'e! )#ss# at#o$ of th#s 0%oc( %ac(#$, e!fo!"#$, a$*

s#"u%at#o$ at ,ate-%e e% o! t!a$s#sto!-%e e%+ The t!a)#t#o$ of o'e! "o)e% has 0ee$

sho'#$, F#,+ 6+;+ Th#s (#$) of o'e! "o)e%#$, a !oach '#%% 0e e!* usefu% #$ the IP- 0ase) SOC )es#,$s+

De t of ECE& VLSI 7 ES& GVIC 5;


14/55


TOOLS REQUIRED

The!e has 0ee$ a asso!t"e$t of too%s "#2e) u #$ th#s thes#s+ E e$

thou,h& th#s thes#s #s a%% '#th !efe!e$ce to s#"u%at#o$ a$) o'e! ca%cu%at#o$s of

"ac!os 'h#ch a!e "a)e us#$, too%s4 the!e a!e othe! too%s that ha e 0ee$ use)

!ece)#$, to the t!a)#t#o$ of o'e! too%s to ,# e the !e1u#s#te #$ ut to the

o'e! too%s+ Mo!e !o"#$e$ce #s ,# e$ to these too%s that a!e "a#$%* #$ o% e) #$

o'e! assess"e$t+ The usa,e of too%s has 0ee$ off the !eco!) as Po'e! too%s a$) No$-

Po'e! too%s+

3.1 NON-POWER TOOLS

No$- o'e! too%s ta(e accou$t of S#"u%at#o$ too%s& S*$thes#s too%s& La*outtoo%s& E2t!act#o$ too%s a$) Wa efo!" #e'e!s+ The too%s that a!e )#scusse) #$ th#s

cha te! a!e so"e of the $o$- o'e! too%s )!a'$ #$ #$ the #$tact )es#,$ f%o'+ A sho!t

o!t!a*a% of each of these too%s a%o$, '#th the#! fu$ct#o$#$, f%o' #s ,# e$ #$ th#s

cha te! to a !ec#ate the#! fu$ct#o$a%#t*+ The su0se1ue$t cha te! )#scusses each of the

o'e! too%s #$ )eta#%e) "a$$e! as "ost of the thes#s #$ o% es the use of these o'e!

too%s+ The fo%%o'#$, cha te! a%so )#scusses the )es#,$ f%o' f!o" co)e

#$sc!# t#o$ to s #ce $et-%#st s#"u%at#o$& c%ea!%* #%%u"#$at#o$ the usa,e of these too%s atthe !es ect# e %e e%+

3.1.1 SIMULATION TOOL

I$#t#a%%*& Ve!#%o, o! V DL co)e fo! a fast#)#ous )es#,$ #s '!#tte$ a$) teste)+

S#"u%at#o$ #s )o$e us#$, Me$to! s Mo)e%s#" fo! 0oth V DL Ve!#%o, a$) othe!

Ve!#%o, s#"u%ato!s+ J#%#$2 #s a s#"u%at#o$ a$) a )e0u,,#$, too% fo! V DL& Ve!#%o,&

a$) othe! "#2e)-%a$,ua,e )es#,$s f!o" Me$to! G!a h#cs+ The 0as#c s#"u%at#o$ f%o'

#s as sho'$ #$ F#,+ 6+ + I$#t#a%%*& a 'o!(#$, %#0!a!* #s fash#o$e) a$) the co)e #s

co" #%e) us#$, the co""a$)s )e e$)#$, u o$ 'hethe! the co)e #s V DL o!

Ve!#%o,+

Ve!#%o, Co" #%e) S#"u%ato! .VCS/ f!o" S*$o s*s #s a h#,h-

e!fo!"a$ce& h#,h-ca ac#t* Ve!#%o, s#"u%ato! that #$co! o!ates a) a$ce) h#,h-

%e e% a0st!act#o$& e!#f#cat#o$ #$to a$ o e$ %atfo!"+ The 0as#c 'o!( f%o' fo! VCS

co$s#sts of t'o 0as#c ste s

a/ Co" #%#$, sou!ce f#%es #$to e2ecuta0%e 0#$a!* f#%es



15/55


0/ Ru$$#$, the e2ecuta0%e 0#$a!* f#%e

Th#s t'o ste a !oach s#"u%ates the )es#,$ faste! a$) uses %ess

"e"o!* tha$ othe! #$te! !et# e s#"u%ato!s+ The 0as#c )es#,$ f%o' #s ,# e$ #$ F#,

;+5+

Fig &.1: shows the design flow

3.1.2 SYNTHESIS TOOL

Des#,$ Co" #%e! #s the co!e of the S*$o s*s s*$thes#s soft'a!e !o)ucts+ It

co" !#ses too%s that s*$thes#3e DL )es#,$s #$to o t#"#3e) tech$o%o,*-)e e$)e$t&

,ate-%e e% )es#,$s+ It su o!ts a '#)e !a$,e of h#e!a!ch#ca% )es#,$ st*%es a$) ca$

o t#"#3e 0oth co"0#$at#o$a% a$) se1ue$t#a% )es#,$s fo! s ee)& a!ea& a$) o'e!+

The 0as#c Des#,$ Co" #%e! .Des#,$ V#s#o$/ s*$thes#s !ocess #s ,# e$ #$ F#,+


16/55


Fig &.2: shows basi design ompiler s*nthesis pro ess

3.2 POWER TOOLS

Th#s thes#s #$ o% es the usa,e of S*$o s*s o'e! too%s+ The o'e! !o)ucts

a!e too%s that co" !#se a co" %ete "etho)o%o,* fo! %o'- o'e! )es#,$+

S*$o s*s o'e! too%s offe! o'e! a$a%*s#s a$) o t#"#3at#o$ th!ou,hout the

)es#,$ c*c%e& f!o" RTL to the ,ate %e e%+ A$a%*3#$, o'e! ea!%* #$ the )es#,$ c*c%e

ca$ s#,$#f#ca$t%* affect the 1ua%#t* of the )es#,$+ I" !o e"e$ts "a)e to the )es#,$

'h#%e #t #s at RTL %e e% ca$ ,et e e$ 0ette! !esu%ts e e$tua%%*+ Not o$%* these o'e!

too%s )o accu!ate "easu!e"e$ts 0ut a%so ca$ he% #$ ca%cu%at#$, o'e! 1u#c(e!+

Po'e! co$su" t#o$ #s ca%cu%ate) at th!ee %e e%s of a0st!act#o$+ The too%s use)

at these %e e%s a!e

a/ RTL Le e% - RTL Po'e! Est#"ato!

0/ Gate Le e% K Po'e! Co" #%e! .0ase) o$ s'#tch#$, act# #t*/&

c/ T!a$s#sto! Le e% K Na$o S#"

3.2.1 POWER COMPILER

Po'e! Co" #%e! #s a$ a))-o$ !o)uct to Des#,$ Co" #%e!+ The Po'e!

Co" #%e! too% o t#"#3es the )es#,$ fo! o'e!+ Wo!(#$, #$ co$ u$ct#o$ '#th the

Des#,$ Co" #%e! too%& Po'e! Co" #%e! !o #)es s#"u%ta$eous o t#"#3at#o$ fo!

t#"#$,& o'e! a$) a!ea+ I$ a))#t#o$ to the sta$)a!) #$ uts to s*$thes#s .RTL o!

,ate-%e e% $et-%#st& tech$o%o,* %#0!a!*& )es#,$ co$st!a#$ts& a$) a!as#t#c/&Po'e!

Co" #%e! uses t'o othe! #$ uts S'#tch#$, act# #t* of )es#,$ e%e"e$ts a$) o'e!

co$st!a#$ts+ It co$ta#$s a%% the a$a%*s#s ca a0#%#t#es of Des#,$ Po'e!+



17/55


Po'e! Co" #%e! uses the sa"e o'e! a$a%*s#s e$,#$e as Des#,$ Po'e!+

Th#s a%%o's Po'e! Co" #%e! to the use the sa"e s'#tch#$, act# #t* fo!

o t#"#3at#o$ that Des#,$ Po'e! uses fo! a$a%*s#s+ It acce ts e#the! use!-)ef#$e)

s'#tch#$, act# #t*& s'#tch#$, act# #t* f!o" s#"u%at#o$& o! a co"0#$at#o$ of 0oth+ It

!o #)es RTL c%oc( ,at#$, a$) o t#"#3es the c#!cu#t 0ase) o$ c#!cu#t act# #t*&

ca ac#ta$ce& a$) t!a$s#t#o$ t#"es+ Po'e! Co" #%e! ca$$ot o$%* 0e use) as a

sta$)a%o$e !o)uct 0ut a%so ca$ 0e use) #$ coo!)#$at#o$ '#th Des#,$ Co" #%e!&

Mo)u%e Co" #%e!& Ph*s#ca% Co" #%e! a$) F%oo! %a$ Ma$a,e!+

3.2.2. POWER COMPILER METHODOLOGY

Po'e! Co" #%e! #s use) at RTL a$) Gate %e e% to ca%cu%ate o'e! a$)

)o o'e! o t#"#3at#o$ )e e$)#$, o$ the $ee)+ At each %e e% of a0st!act#o$&s#"u%at#o$& a$a%*s#s a$) o t#"#3at#o$ ca$ 0e e!fo!"e) to !ef#$e the )es#,$

0efo!e "o #$, to the $e2t %o'e! %e e%+ S#"u%at#o$ a$) the !esu%ta$t s'#tch#$,

act# #t* ,# es the a$a%*s#s a$) o t#"#3at#o$ the $ecessa!* #$fo!"at#o$ to !ef#$e the

)es#,$ 0efo!e ,o#$, to $e2t %o'e! %e e% of a0st!act#o$+ The h#,he! the %e e% of )es#,$

a0st!act#o$& the ,!eate! the o'e! sa #$,s ca$ 0e ach#e e)+ The fo%%o'#$, F#,+


18/55


the )es#,$ 0* co" a!#$, the t#"e of a s#,$a% at a ce!ta#$ %o,#c state to the tota% t#"e of

the s#"u%at#o$+ To,,%e !ate #s the $u"0e! of %o,#c-@-to-%o,#c-5 a$) %o,#c-5-to-%o,#c-@

t!a$s#t#o$s of a )es#,$ o0 ect e! u$#t of t#"e+

The fo%%o'#$, F#,


19/55


Fig &.(: shows power flow from RTL to +ate le!el

The fo%%o'#$, F#, ;+ sho's the "etho)o%o,* of o'e! ca%cu%at#o$

us#$, the co"0#$at#o$ of Po'e! Co" #%e! a$) Des#,$ Co" #%e!+ The f%o' of )ata 0et'ee$ the )#ffe!e$t ste s a$) too%s use) a!e a%so sho'$+ Befo!e sta!t#$, to ca%cu%ate

o'e! us#$, Po'e! Co" #%e! the )es#!e) ,ate-%e e% $et-%#st of the )es#,$ shou%) 0e

f#!st ,e$e!ate)+ The o'e! "etho)o%o,* sta!ts '#th the RTL )es#,$ a$) f#$#shes '#th a

o'e!-o t#"#3e) ,ate-%e e% $et-%#st+ U%t#"ate%*& Po'e! Co" #%e! #s use) to

ca%cu%ate o'e! us#$, the ,ate-%e e% $et-%#st !o)uce) 0* the Des#,$ Co" #%e!

o! o'e!-o t#"#3e) ,ate $et-%#st !o)uce) 0* Po'e! Co" #%e! #tse%f+ As see$ #$

the f#,u!e "ost of the !ocesses that ta(e %ace a!e us#$, Des#,$ Co" #%e!& 0ut

the s#"u%at#o$ !ocess that #s sho'$ #s outs#)e Des#,$ Co" #%e! too% a$) #s )o$e as

a!t of o'e! ca%cu%at#o$+

The "a#$ u! ose of s#"u%at#o$ #s to ,e$e!ate #$fo!"at#o$ a0out the

s'#tch#$, act# #t* of the )es#,$ a$) c!eate a f#%e ca%%e) Bac(-a$$otat#o$+ Th#s

f#%e ca$ co$ta#$ s'#tch#$, act# #t* f!o" RTL s#"u%at#o$ o! ,ate-%e e% s#"u%at#o$+

I$#t#a%%*& the RTL )es#,$ #s ,# e$ to the DL co" #%e! to c!eate a tech$o%o,*-

#$)e e$)e$t fo!"at ca%%e) as GTEC )es#,$+ Th#s #s as a !esu%t of a$a%*3#$, a$)

e%a0o!at#$, the )es#,$ 0* DL co" #%e!+ Th#s fo!"atte) )es#,$ #s ,# e$ as a$

De t of ECE& VLSI 7 ES& GVIC 5>


20/55


#$ ut to Des#,$ Co" #%e!+ Befo!e #t #s co" #%e) 0* the Des#,$ Co" #%e!& !t%6sa#f

co""a$) #s use) to c!eate fo!'a!)-a$$otat#o$ f#%e 'h#ch #s %ate! use) fo! s#"u%at#o$+

The fo!"atte) )es#,$ GTEC #s %ate! ,# e$ as #$ ut to Des#,$ Co" #%e! 'h#ch

!o)uces a$ out ut 'h#ch #s ,# e$ to Po'e! Co" #%e!+

The Fo!'a!)-a$$otat#o$ SAIF f#%e #s ,# e$ as a$ #$ ut to )o RTL s#"u%at#o$

'h#ch ,# es a 0ac(-a$$otat#o$ SAIF f#%e 'h#ch #s use) 0* Po'e! Co" #%e!+ Th#s

fo!'a!) a$$otate) f#%e co$ta#$s )#!ect# es that )ete!"#$e 'h#ch )es#,$ e%e"e$ts to 0e

t!ace) )u!#$, s#"u%at#o$+ Gate %e e% s#"u%at#o$ ca$ a%so use a %#0!a!* fo!'a!)-

a$$otat#o$ f#%e+ Th#s fo!'a!)-a$$otat#o$ f#%e use) fo! ,ate %e e% s#"u%at#o$ has

)#ffe!e$t #$fo!"at#o$ co" a!e) to RTL fo!'a!)-a$$otat#o$ f#%e+ Th#s f#%e

co$ta#$s #$fo!"at#o$ f!o" the tech$o%o,* %#0!a!* a0out ce%%s '#th state a$) ath )e e$)e$t o'e! "o)e%s+ L#06sa#f co""a$) #s use) to ,et th#s fo!'a!)-

a$$otat#o$ f#%e+

Fig &.,: shows power methodolog* in power ompiler

Du!#$, o'e! a$a%*s#s& Po'e! Co" #%e! uses the a$$otate) s'#tch#$, act# #t*

to e a%uate the o'e! co$su" t#o$ of the )es#,$+ Du!#$, o'e! o t#"#3at#o$& Po'e!

Co" #%e! uses the a$$otate) s'#tch#$, act# #t* to "a(e )ec#s#o$s a0out the )es#,$+

De t of ECE& VLSI 7 ES& GVIC 6@


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3.3 STARTING ISE SOFTWARE

3.3.1 WINDOWS

To sta!t ISE& )ou0%e-c%#c( the )es(to #co$

O! ,o to& Sta!t A%% P!o,!a"s J#%#$2 ISE Des#,$ Su#te 5


22/55


3.3.4 PRO!ECT SETTINGS PAGE

5+ I$ the f#e%) E a%uat#o$ De e%o "e$t Boa!)& se%ect V#!te2 ML @ E a%uat#o$

P%atfo!"+

6+ I$ the f#e%) S#"u%ato!& Se%ect IS#".V DL Ve!#%o,/+

;+ I$ the f#e%) P!efe!!e) La$,ua,e& Se%ect V DL+


23/55


Fig &./: shows the spe ifi de!i e and pro e t properties

3.3. CREATE A NEW DESIGN

To stu)* ho' to c!eate a $e' )es#,$& 'e '#%% )es#,$ #$ th#s sect#o$ a 6-I$ ut

J-OR Gate+ The J-OR Fu$ct#o$ #s )ef#$e) as Y A5 2o! B5 A5 B5 H A5B5 +

3.3. .1 CREATE A SCHEMATIC SOURCE

5+ I$ ISE Des#,$ Su#te that a ea!s o$ the %eft s#)e of ISE& c%#c( o$ the Des#,$ Ta0 to

,o to the Des#,$ Pa$e%

6+ I$ the Des#,$ Pa$e%& !#,ht-c%#c( o$ the #co$ tuto!#a%Q 5 a$) se%ect Ne' Sou!ce to

"o e to the a,e Se%ect Sou!ce T* e+

De t of ECE& VLSI 7 ES& GVIC 6;


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Fig &.8: shows how to reate new so%r e

;+ The a,e Se%ect Sou!ce T*e

#/ I$ the f#e%) F#%e Na"e& t* e "*Q2o!

You ca$ choose a$othe! $a"e that )oes $ot co$ta#$ a$* 'h#te s aces

##/ F!o" the Co%u"$ at the %eft-s#)e& se%ect Sche"at#c as a Sou!ce T* e

###/ T#c( the o t#o$ A)) To P!o ect+

# / C%#c( Ne2t to "o e to the a,e P!o ect Su""a!*


25/55


;+ F!o" the a% ha0et#ca%%* o!)e!e) s*"0o%s a ea! #$ the S*"0o%s a$e% se%ect the

!e1u#!e) s*"0o%s fo! ou! )es#,$& a$) a)) the" to the sche"at#c f#%e

The !e1u#!e) S*"0o%s a!e .T'o 6-I$ ut A$) ,ates& T'o 5-I$ ut I$ e!te!s& a$)

O$e 6-I$ ut O! ,ates/+


26/55


=+ Sa e the f#$a% sche"at#c f#%e "*Q2o!+sch 'h#ch co$ta#$s the f#$a% )es#,$+

3.4 SIMULATE DESIGN

I$ th#s sect#o$& 'e '#%% s#"u%ate ou! )es#,$ to e!#f* that #t 0eha es as 'e

e2 ect+ We '#%% use the I$te,!ate) S#"u%ato! .IS#"/+

3.4.1 ISIM

5+ O e$ Des#,$ Pa$e%+ I$ Des#,$ Pa$e% V#e'& se%ect S#"u%at#o$

6+ I$ Des#,$ Pa$e% #e!a!ch*& se%ect "*Q2o!Qtst+ h)

;+ I$ Des#,$ Pa$e% P!ocesses IS#" S#"u%ato!& Dou0%e C%#c( S#"u%ate

Beha #o!a% Mo)e% to o e$ the I$te,!ate) S#"u%ato! .IS#"/+

3.4.1.2 ISIM WINDOW

#/ oo"-Out to #e' the 'ho%e s#"u%at#o$ t#"e& the Defau%t s#"u%at#o$ t#"e #s 5@@@

$s&

##/ The S#"u%ato! sho's the th!ee o!ts A5& B5 a$) Y5

###/ Co" a!e the a%ue of Y5 '#th A5 a$) B5+ Y5 shou%) a%'a*s e1ua% to A5 J-OR

B5

Fig &.1 : shows how to sim%late



27/55


Fig &.11: The wa!eforms res%lt

De t of ECE& VLSI 7 ES& GVIC 6?


28/55


IMPLEMENTATION

I$ the ast tech$#1ue 95: the "easu!e of t#"e #s 'aste) 0* )#sco e!#$, the

#" oss#0%e co"0#$at#o$ of FF fu!the!"o!e $u"e!ous s#$,%e 0#t FF #s ut#%#3e)+ Th#s

"a* e2 a$) the co" %#cate) $atu!e+ So as to )ec!ease the o'e! MBFF #)ea #s

ut#%#3e)+ It o!t!a*s that $ee) to !eco,$#3e a %e,a% %ace"e$t !e,#o$ fo! e e!* FF+ I$

f#!st sta,e& the !easo$a0%e %ace"e$t !e,#o$s of a FF co$$ecte) '#th )# e!se #$s a!e

)#sco e!e) focuse) a!ou$) the t#"#$, st# u%at#o$s cha!acte!#3e) o$ the #$s+ At that

o#$t& the %e,a% %ace"e$t !e,#o$ of the FF ca$ 0e o0ta#$e) 0* o e!%a e) a!ea of

these !e,#o$s+

No$ethe%ess& these !e,#o$s a!e f#t as a )#a"o$) sha e4 #t #s $ot s#" %e to

!eco,$#3e the o e!%a e) !e,#o$+ Acco!)#$,%*& the o e!%a e) 3o$e ca$ 0e !eco,$#3e)

a%% the "o!e effect# e%* #$ the e e$t that #t ca$ cha$,e the coo!)#$ate a!!a$,e"e$t of

ce%%s to ,et !ecta$,u%a! !e,#o$s+ I$ the seco$) sta,e& #t "#,ht 'a$t to "a$ufactu!e a

co"0#$at#o$ ta0%e& 'h#ch cha!acte!#3es a%% co"0#$at#o$s of FF (ee #$, #$ "#$) the

e$) ,oa% to ,et a$othe! "u%t#-0#t Ffs ,# e$ 0* the %#0!a!*+

The f%# -f%o s ca$ 0e u$#te) '#th the ass#sta$ce of the ta0%e+ Afte! the %e,a%

%ace"e$t !e,#o$s of f%# -f%o s a!e )#sco e!e) a$) the co"0#$at#o$ ta0%e #s fa0!#cate)&

'e ca$ ut#%#3e the" to "e!,e f%# -f%o s+ To acce%e!ate ou! !o ect& 'e '#%% #so%ate a

ch# #$to a fe' ca$#ste!s a$) co$so%#)at#o$ f%# -f%o s #$ a $e#,h0o!hoo) 0#$+

o'e e!& the f%# -f%o s #$ )# e!se 0#$s "#,ht 0e "e!,e a0%e+ I$ th#s 'a*& 'e

$ee) to co$so%#)ate a fe' 0#$s #$to a 0#,,e! 0#$ a$) !e eat th#s e$tu!e u$t#% $o f%# -

f%o ca$ 0e fuse) a$* %o$,e!+ I$ th#s a!ea& 'e 'ou%) )eta#% each o$e hase of ou!

tech$#1ue+ I$ the f#!st su0sect#o$& 'e )e"o$st!ate a 0as#c e1uat#o$ to cha$,e the

o!#,#$a% coo!)#$at#o$ f!a"e'o!( #$to a$othe! o$e so that a %e,a% %ace"e$t !e,#o$ fo! each o$e f%# -f%o ca$ 0e )#st#$,u#she) a%% the "o!e effect# e%*+ The seco$) su0sect#o$

sho's the f%o' of 0u#%)#$, the co"0#$at#o$ ta0%e+ At %o$, %ast& the su0st#tut#o$s of

f%# -f%o s '#%% 0e )e #cte) #$ the %ast su0sect#o$+

4.1 TRANSFORMATION OF PLACEMENT SPACE

We ha e sho'$ that the sha e of a feas#0%e %ace"e$t !e,#o$ assoc#ate) '#th

o$e #$ pi co$$ect#$, to a # - o fi 'ou%) 0e )#a"o$) #$ Sect#o$ II+ S#$ce the!e "a*

e2#st se e!a% #$s co$$ect#$, to f i " the %e,a% %ace"e$t !e,#o$ of f i a!e the

De t of ECE& VLSI 7 ES& GVIC 6=


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o e!%a #$, a!ea of se e!a% !e,#o$s+ As sho'$ #$ F#,+


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F#,+


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F#,+


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4.2.1 COMBINATION TABLE

A fe' f%# -f%o s ca$ 0e !e %ace) 0* "u%t#-0#t f%# -f%o + I$ th#s !o ose)

"etho)o%o,*& the co"0#$at#o$ ta0%e #s asse"0%e& 'h#ch #s ut#%#3e) to ,et ach#e a0%e

f%# -f%o s 0efo!e su0st#tut#o$+ Th#s "a(es to use fo! !eco,$#3#$, the s ec#f#c f%# -f%o

'h#ch '#%% 0e e" o'e!e) #$ act# e !e,#o$ a$) ca$$ot 0e co e!e)+ Ut#%#3#$, th#s

co"0#$at#o$ ta0%e& the f%# -f%o ca$ 0e 0#t 0* 0#t !e %ace) a$) th#s "a(es %esse$s the

"u%t#facete) $atu!e of the co$f#,u!at#o$+ S#$ce o$e a$) o$%* co"0#$at#o$ of f%# -f%o

$ee) to 0e co$s#)e!e) #$ each o$e t#"e& the c%oc( s#,$a% ca$ 0e successfu%%*

)ec!ease)+

If 'e 'a$t to !e %ace se e!a% # - o s 0* a $e' # - o f $ote that the 0#t '#)th of

f shou%) e1ua% to the su""at#o$ of 0#t '#)ths of these # - o s/& 'e ha e to "a(e

su!e that the $e' # - o f #s !o #)e) 0* the %#0!a!* L 'he$ the feas#0%e !e,#o$s of

these # - o s o e!%a . I$ th#s a e!& 'e '#%% 0u#%) a co"0#$at#o$ ta0%e& 'h#ch

!eco!)s a%% oss#0%e co"0#$at#o$s of # - o s to ,et feas#0%e # - o s 0efo!e

!e %ace"e$ts+ Thus& 'e ca$ ,!a)ua%%* !e %ace # - o s acco!)#$, to the o!)e! of the

co"0#$at#o$s of # - o s #$ th#s ta0%e+ S#$ce o$%* o$e co"0#$at#o$ of # - o s $ee)s

to 0e co$s#)e!e) #$ each t#"e& the sea!ch t#"e ca$ 0e !e)uce) ,!eat%*+ I$ th#s

su0sect#o$& 'e #%%ust!ate ho' to 0u#%) a co"0#$at#o$ ta0%e+

The seu)o co)e fo! 0u#%)#$, a co"0#$at#o$ ta0%e T #s sho'$ #$ A%,o!#th" 5+

We use a 0#$a!* t!ee to !e !ese$t o$e co"0#$at#o$ fo! s#" %#c#t*+ Each $o)e #$ the t!ee

)e$otes o$e t* e of a # - o #$ L+ The t* es of # - o s )e$ote) 0* %ea es '#%%

co$st#tute the t* e of the # - o #$ the !oot+ Fo! each $o)e& the 0#t '#)th of the

co!!es o$)#$, # - o e1ua%s to the 0#t '#)th su""at#o$ of # - o s )e$ote) 0* #ts

%eft a$) !#,ht ch#%) 9 %ease see F#,+ >.e/ fo! e2a" %e:+ Let ni )e$ote o$e co"0#$at#o$

#$ T &a$)b ni 3 )e$ote #ts 0#t '#)th . I$ the 0e,#$$#$,& 'e #$#t#a%#3e a co"0#$at#o$ ni fo!

each (#$) of # - o s #$ L .see L#$e 5/ . The$& #$ o!)e! to !e !ese$t a%% co"0#$at#o$s

0* us#$, a 0#$a!* t!ee& 'e "a* a)) ' $ +5'$ & 'h#ch )e$ote those # - o s that

a!e $ot !o #)e) 0* the %#0!a!*& .see L#$e 6/+ Fo! e2a" %e& assu"e that a %#0!a!* o$%*

su o!ts t'o (#$)s of # - o s 'hose 0#t '#)ths a!e 5 a$)


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A#% , +6) 1 B # C )/ *&+ * T&/#$ +

5 T I$#t#a%#3at#o$Co"0#$at#o$Ta0%e.L/46 I$se!tPseu)oT* e.L/4; So!tB*B#tNu"0e! .L/4< fo! each $# #$ T )o

I$se!tCh#%)!e$s .$#& NULL& NULL/4#$)e2 @4

? 76 #$ inde4 s#3e. T /= range5first inde4 4> range5se ond s#3e. T /45@ inde4 s#3e. T /455 8 , $&(6 ni #$ T

56 8 , j 9 5 to range5first T* eVe!#f*. ni& $ &T /45; 8 , j 9 i to range5se ond T* eVe!#f*. ni& $ &T /45< T 9 Du %#cateCo"0#$at#o$De%ete.T /45 T 9 U$use)Co"0#$at#o$De%ete. T /4

I* $,+P $ T5'$ . L/

5+ 18 , i . b"#$H5/ to . b"a2-5/6+ 8 L )oes $ot co$ta#$ a t* e 'hose 0#t '#)th #s e1ua% to i /;+ #$se!t a seu)o t* e typej '#th 0#t '#)th i to L4

I* $,+C6 # ,$* .n6 n16 n2/

1 n.left5 hild X n142 n.right5 hild X n24

T5'$V$, 85 .n1&n26 T /

5+ 1 bs%m b.n1/H b.n2/46+ 8 . L co$ta#$s a t* e 'hose 0#t '#)th #s bs%m/;+ #$se!t a $e' co"0#$at#o$ n 'hose 0#t '#)th bs%mto T 4


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pseudo types. Let bmax and bmin denote the maximum and minimum bit width of

ip-ops in L.In InsertPseudoType , it inserts all ip-ops whose bit widths are

larger than bmin and smaller than bmax into L if they are not provided by L

originally. After this procedure, all combinations in L are sorted according to their bit

widths in the ascending order (Line 3). At present, all combinations are represented

by binary trees with 0-level. Thus, we would assign NULL to its right and left child

(see Lines 4 and 5). Finally, for every two kinds of combinations in T ,we try to

combine them to create a new combination (Lines 613). If the new combination is

the ip-op of a feasible type (this can be checked by the function TypeVerify), we

would add it to the table T . In the function TypeVerify ,we rst add the bit widths of

the two combinations together and store the result in bsum (see Line 1 in

TypeVerify ). Then, we will add a new combination n to T with bit width bsum if L

has such kind of a ip-op. After these procedures, there may exist some duplicated

or unused combinations in T . Thus, we have

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Fig. 4.4. Example of building the combination table.



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(a) Initialize the library L and the combination table T . (b) Pseudo types are added

into L,and the corresponding binary tree is also build for each combination in T .(c)

New combination n3 is obtained from combining two n1s. (d) New combination n4 is

obtained from combining n1 and n3, and the combination n5 is obtained fromcombining two n3s. (e) New combination n6 is obtained from combining n1 and n4.4

(f) Last combination table is obtained after deleting the unused combination in4.4 (e).

To )e%ete the" f!o" the ta0%e a$) the t'o fu$ct#o$s D '# (&+$C )/ *&+ *D$#$+$

a$) U* $ C )/ *&+ *D$#$+$ a!e ca%%e) fo! the u! ose .L#$es 5< a$) 5 /+ I$

D '# (&+$C )/ *&+ *D$#$+$ & #t chec(s 'hethe! the )u %#cate) co"0#$at#o$s e2#st

o! $ot+ If the )u %#cate) co"0#$at#o$s e2#st& o$%* the o$e '#th the s"a%%est he#,ht of

#ts co!!es o$)#$, 0#$a!* t!ee #s %eft a$) the othe!s a!e )e%ete)+ I$U* $ C )/ *&+ *D$#$+$ t chec(s the co"0#$at#o$s 'hose co!!es o$)#$, t* e #s

seu)o

Algorithm 2 Insert Pseudo Types (optional)

InsertPseudoType ( L):

1. 1 for each typej in L do

2. PseudoTypeVerifyInsertion( typej , L) ;

PseudoTypeVerifyInsertion( typej , L):

1 if (mod ( b(typej ) /2) == 0)

2 b1 = [b(typej )/2], b2= [ b(typej )/2];

3 else

4 b1 = b(typej )/2 , b2= b(typej ) - b(typej )/2

5 for i = 1 to 2

6 if ( (bi > bmin ) &&

( L does not contain a type whose bit width is equal to bi)) 7 insert a pseudo type typej

with bit width bi to L; 8 PseudoTypeVerifyInsertion (typej, L);

type in L. If the combination is not included into any other combinations, it will be

deleted.

For example, suppose a library L only provides two types of ip-ops, whose

bit widths are 1 and 4 (i.e., bmin = 1and bmax = 4), in Fig. 4.4(a). We rst initialize



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two combinations n1 and n2 to represent these two types of ip-ops in the table T

[see Fig. 4.4(a)]. Next, the function InsertPseudoType is performed to check whether

the ip-op types with bit widths between 1 and 4 exist or not. Thus, two kinds of

ip-op types whose bit widths are 2 and 3 are added into L, and all types of ip-ops

in L are sorted according to their bit widths [see Fig. 4.4(b)]. Now, for each

combination in T , we would build a binary tree with 0-level, and the root of the binary

tree denotes the combination. Next, we try to build new legal combinations according

to the present combinations. By combing two 1-bit ip-ops in the rst combination,

a new combination n3 can be obtained [see Fig. 4.4(c)]. Similarly, we can get a new

combination n4(n5) by combining n1 and n3(two n3s) [see Fig. 4.4(d)]. Finally, n6 is

obtained by combing n1 and n4. All possible combinations of ip-ops are shown in

Fig. 4.4(e). Among these combinations, n5 and n6 are duplicated since they both

represent the same condition, which replaces four 1-bit ip-ops by a 4-bit ip-op.

To speed up our program, n6 is deleted from T rather than n5 because its height is

larger. After this procedure, n4 becomes an unused combination [see Fig. 4.4(e)] since

the root of binary tree of n4 corresponds to the pseudo type, type3,in L and it is only

included in n6.After deleting n6, n4 is also need to be deleted. The last combination

table T is shown in Fig. 4.4(f).

In order to enumerate all possible combinations in the combination table, all

the ip-ops whose bit widths range between bmax and bmin and do not exist in L

should be inserted into L in the above procedure. However, this is time consuming.

To improve the running time, only some types of ip-ops need to be inserted. There

exist several choices if we want to build a binary tree corresponding to a type typej .

However, the complete binary tree has the smallest height. Thus, for building a binarytree of a certain combination ni whose type is typej , only the ip-ops whose bit

widths

De t of ECE& VLSI 7 ES& GVIC ;?


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Input

F.g.4.5 detailed flow to merge flip flops are

(b(typej ) /2)and ( b(typej ) b(typej ) /2) should exist in L. Algorithm 2 shows the

enhanced procedure to insert ip-ops of pseudo types. For each typej in L, the

function.

PseudoTypeVerifyInsertion recursively checks the existence of ip-ops whose bit

widths around[ b(typej ) /2] and add them into L if they do not exist (see Lines 1 and

2). In the function PseudoTypeVerifyInsertion , it divides the bit width b(typej ) into

two parts [ b(typej ) /2] and [ b(typej ) /2] [b(typej ) /2] and b(typej ) b(typej ) /2)ifb(typej ) is an even (odd) number (see Lines 14 in PseudoTypeVerifyInsertion ),

De t of ECE& VLSI 7 ES& GVIC ;=


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and it would insert a pseudo type typej into L if the type is not provided by L and its

bit width is larger than the minimum bit width (denoted by bmin ) of ip-ops in L

(see Lines 58 in PseudoTypeVerifyInsertion ). The same procedure repeats in the

new created type. Note that this method works only when the 1-bit type exists in L.

We still have to insert pseudo ip-ops by the function InsertPseudoType in

Algorithm 1 if the 1-bit ip-op is not provided by L.

For example, assume a library L only provides two kinds of ip-ops whose

bit widths are 1 and 7. In the new procedure, it rst adds two pseudo types of ip-

ops whose bit widths are 3 and 4, respectively, for the ip-op with 7-bit (i.e., L

becomes [1 3 4 7]). Next, the ip-op whose bit width is 2 is added to L for the ip-

op with 4-bit (i.e., L becomes [12 34 7]). For the ip-op with 3-bit, the procedure

stops because op-ops with 1 and 2 bits already exist in L. In the new procedure, we

do not need to insert 5-and 6-bit pseudo types to L.

4.2.2 Merge Flip-Flops

We have shown how to build a combination table in Section III-B. Now, we

would like to show how to use the combination table to combine ip-ops in this

subsection. To reduce the complexity, we rst divide the whole placement region into

several subregions, and use the combination table to replace ip-ops in each

subregion. Then, several subregions are combined into a larger subregion and the ip-

ops are replaced again so that those ip-ops in the neighboring subregions can be

replaced further. Finally, those ip-ops with pseudo types are deleted in the last

stage because they are not provided by the supported library. Fig. 4.5shows this ow.

1) Region Partition (Optional): To speed up our problem, we divide the whole chip

into several subregions. By suitable partition, the computation complexity of merging

ip-ops can be reduced signicantly (the related quantitative analysis will be shown

in Section V). As shown in Fig. 11, we divide the region into several subregions, and

each subregion contains six bins, where a bin is the smallest unit of a subregion

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F.g 4.6 example of region portion with six bins in one sub region

2) Replacement of Flip-ops in Each Subregion: Before illustrating our procedure to

merge ip-ops, we rst give an equation to measure the quality if two ip-ops are

going to be replaced by a new ip-op as follows:

cost = routing_length available_area (5)where routing_length denotes the total routing length between the new ip-op and

the pins connected to it, and avail-able_area represents the available area in the

feasible region for placing the new ip-op. is a weighting factor (the related

analysis of the value will be shown in Section V). The cost function includes the

term routing_length to favor a replacement that induces shorter wirelength. Besides, if

the region has larger available space to place a new ip-op, it implies that it has

higher opportunities to combine with other ip-ops in the future and more power

reduction. Thus, we will give it a smaller cost. Once the ip-ops cannot be merged to

a higher-bit type (as the 4-bit combination n4 in Fig. 4.4), we ignore the

available_area in the cost function, and hence is set to 0.

After a combination has been built, we will do the replacements of ip-ops

according to the combination table. First, we link ip-ops below the combinations

corresponding to



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Fig. 4.7. Example of replacements of ip-ops. (a) Sets of ip-ops before merging.

(b) Two 1-bit ip-ops, f 1 and f 2, are replaced by the 2-bit ip-op f 3. (c) Two 1-bit

ip-ops, f 4 and f 5, are replaced by the 2-bit ip-op f 6.

1(d) Two 2-bit ip-ops, f 7 and f 8, are replaced by the 4-bit ip-op f 9.

2(e) Two 2-bit ip-ops, f 3 and f 6, are replaced by the 4-bit ip-op f 10.

3(f) Sets of ip-ops after merging.



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their types in the library. Then, for each combination n in T , we serially merge the

ip-ops linked below the left child and the right child of n from leaves to root.

Algorithm 3 shows the procedure to get a new ip-op corresponding to the

combination n. Based on its binary tree, we can nd the combinations associated withthe left child and right child of the root. Hence, the ip-ops in the lists, named lleft

and lright, linked below the combinations of its left child and its right child are

checked (see Lines 2 and 3). Then, for each ip-op fi in lleft, the best ip-op f best

in lright, which is the ip-op that can be merged with fi with the smallest cost

recorded in cbest, is picked. For each pair of ip-ops in the respective list, the

combination cost [based on (5)] is computed if they can be merged and the pair with

the smallest cost is chosen (see Lines 411). Finally, we add a new ip-op f in the

list of the combination n and remove the picked ip-ops which constitutes the f (see

Lines 1214).

For example, given a library containing three types of ip-ops (1-, 2-, and 4-bit), we

rst build a combination table T as shown in Fig. 4.7(a). In the beginning, the ip-

ops with various types are, respectively, linked below n1, n2,and n3 in

Fig. 4.8. Combination of flip-flops near subregion boundaries. (a) Result of replace

flip-flops in each subregion. (b) Result of replace flip-flops in each new subregion

which is obtained from combining twelve subregion in (a).



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Fig. 4.9. Combination of subregions to a larger one. (a) Placement is originally

partitioned into 16 subregions for replacement. (b) Subregion bounded by bold line is

obtained from combining four neighboring subregions in (a). (c) Subregion bounded

by bold line is obtained from combining four subregions in (b).

T according to their types. Suppose we want to form a ip-op in n4, which

needs two 1-bit ip-ops according to the combination table. Each pair of ip-ops in

n1 are selected and checked to see if they can be combined (note that they also have

to satisfy the timing and capacity constraints described in Section II). If there are

several possible choices, the pair with the smallest cost value is chosen to break the

tie. In Fig. 4.7(a), f 1 and f 2 are chosen because their combination gains the smallest

cost. Thus, we add a new node f 3 in the list below n4 , and then delete f 1 and f 2 from

their original list [see Fig. 4.7(b)]. Similarly, f 4 and f 5 are combined to obtain a new

ip-op f 6 , and the result is shown in Fig. 4.7(c). After all ip-ops in the

combinations of 1-level trees ( n4 and n5) are obtained as shown in Fig. 4.7(d), we

start to form the ip-ops in the combinations of 2-level trees ( n6,and n7). In Fig.

4.7(e), there exist some ip-ops in the lists below n2 and n4,and we will merge them

to get ip-ops in n6 and n7, respectively. Suppose there is no overlap region between

the couple of ip-ops in n2 and n4. It fails to form a 4-bit ip-op in n6.Since the 2-bit ip-ops f 3 and f 6 are mergeable, we can combine them to obtain a 4-bit ip-op

f 10 in n7. Finally, because there exists no couple of ip-ops that can be combined

further, the procedure nishes as shown in Fig.4.7(f).

If the available overlap region of two ip-ops exists, we can assign a new one to

replace those ip-ops. Once there is sufcient space to place the new ip-op in the

available region, the algorithm will perform the replacement, and the new generated

ip-op will be placed in the grid that makes the wirelength between the ip-op and



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its connected pins smallest. If the capacity constraint of the bin, Bk ,which the grid

belongs to will be violated after the new ip-op is placed on that grid, we will search

the bins near Bk to nd a new available grid for the new ip-op. If none of bins

which are overlapped with the available region of new ip-op can satisfy thecapacity constraint after the placement of new ip-op, the program will stop the

replacement of the two ip-ops.

3) Bottom-Up Flow of Subregion Combinations (Optional): As shown in Fig.4.8 (a),

there may exist some ip-ops in the boundary of each subregion that cannot be

replaced by any ip-op in its subregion. However, these ip-ops may be merged

with other ip-ops in neighboring subregions as shown in Fig. 4.8(b). Hence, to

reduce power consumption further more, we can combine several subregions to obtaina larger subregion and perform the replacement again in the new subregion again. The

procedure repeats until we cannot achieve any replacement in the new subregion. Fig.

14 gives an example for this hierarchical ow. As shown in Fig. 4.9(a), suppose we

divide a chip into 16 subregions in the beginning. After the replacement of ip-ops

is nished in each subregion, four subregions are combined to get a larger one as

shown in Fig. 4.9(b). Suppose some ip-ops in new subregions still can be replaced

by new ip-ops in other new subregions, we would combine four subregions in Fig.

4.9(b) to get a larger one as shown in Fig. 4.9(c) and perform the replacement in the

new subregion again. As the procedure repeats in a higher level, the number of

mergeable ip-ops gets fewer. However, it would spend much time to get little

improvement for power saving. To consider this issue, there exists a trade-off between

power saving and time consuming in our program.

4) De-Replace and Replace (Optional): Since the pseudo type is an intermediate type,

which is used to enumerate all possible combinations in the combination table T ,we

haveto remove the ip-ops belonging to pseudo types. Thus, after the above

procedures have been applied, we would perform de-replacement and replacement

functions if there exists any op-ops belonging to a pseudo type. For example, if

there still exists a ip-op, fi , belonging to n3 after replacements in Fig. 9(f), we have

to de-replace fi into two ip-ops originally belongs to n1. After de-replacing, we will

do the replacements of ip-ops according to T without consideration of the

combinations whose corresponding type is pseudo in L.



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4.3 BLOCK DIAGRAM AND ITS MODULES

Th#s )ea%s '#th the 0%oc( )#a,!a" of the !o ose) "etho) a$) #ts "o)u%es+

4.3.1 BLOCK DIAGRAM

The 0%oc( )#a,!a" of the A %#cat#o$ of Mu%t#-0#t f%# -f%o us#$, CL A))e!

as sho'$ #$ f#,u!e


46/55


47/55


at the c%oc( e),e& a$) #f the )ata cha$,es at )#ffe!e$t t#"es& the *#e%) '#%% 0e

u$affecte)+ D f%# -fa#%u!es a!e 0* a '#)e "a!,#$ the "ost 'e%%-($o'$ so!t of f%# -f%o s

a$) a fe' ,a),ets a!e "a)e a%to,ethe! f!o" D f%# -f%o s+ The* a!e !e,u%a!%* ut#%#3e)

fo! sh#ft- !e,#ste!s a$) #$ ut s*$ch!o$#3at#o$+

4.4 OB!ECTIVES

5+ Re)uce the o'e! co$su" t#o$+

6+ To !e)uce to the a!ea+

;+ To !e)uce the )e%a* a$) o'e! of a c%oc( $et'o!(+


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RESULTS

.1 SIMULATION AND SYNTHESIS OUTPUT

These !esu%ts co$ta#$ the s#"u%at#o$ a$) s*$thes#s !esu%ts fo! )#ffe!e$t f%#f%o s a$) the a))e! 'h#ch 'as )es#,$e) as a %#cat#o$ "o)u%e+

Fo! a s#$,%e 0#t f%# -f%o 'he$ #$ ut of c%oc( %ea)#$, e),e #s at @ a$) the

t!a#%#$, e),e #s at 5& ) f%# -f%o #$ ut #s ,# e$ as 5& c%ea! #$ ut #s ,# e$ as 5a$) the

!eset out ut #s ,# e$ as 5+ The out ut '#%% 0e the 54 the s#"u%ate) 'a efo!" 'as as

sho'$ #$ the F#,+ +5+

Fig ,.1: Sim%lation diagram of single bit flip-flop

Fo! th#s s#$,%e 0#t f%# -f%o e!fo!"e) s*$thes#s #$ o!)e! to ,e$e!ate the

s*$thes#s !e o!ts+ The RTL sche"at#c fo! the s#$,%e 0#t f%# f%o has sho'$ #$ the

0e%o' f#,u!e+



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Fig ,.2: RTL s hemati for single bit flip-flop.

Fo! a "u%t#0#t.6 0#t f%# -f%o / f%# -f%o 'he$ #$ ut of c%oc( %ea)#$, e),e #s @

a$) t!a#%#$, e),e #s 5&)5 #$ ut #s 5 a$) )6 #$ ut #s @&c%ea! #$ ut #s 5 a$) !eset #$ ut #s

@+The out ut of 15 '#%% 0e 5 a$) the out ut of 16 '#%% 0e @ as sho'$ #$ the F#,+ +;+

The out ut of D f%# -f%o '#%% 0e sa"e as the #$ ut o$%* 'he$ the c%ea! #$ ut #s

#$ the h#,he! os#t#o$ )e e$)#$, o$ e!#o) ,# e$ to the c%oc( 0efo!e the s#"u%at#o$

#$ ut the c%oc( s#,$a% a!#es as sho'$ #$ the F#,+ +5+

The out ut a!#es '#th the cha$,e #$ the #$ ut the F#,+ sho'$ a!e so"e

e2a" %es+ Not o$%* t'o 0#t "u%t#-0#t f%# -f%o 'e ca$ a%so use < a$) = 0#t "u%t#-0#tf%# -f%o + The F#,+ 0e%o' sho's the s#"u%at#o$ out ut of 6 "u%t#-0#t f%# -f%o +



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Fig ,.&: Sim%lation diagram of m%lti bit flip-flop

Fo! th#s "u%t# 0#t f%# -f%o e!fo!"e) s*$thes#s #$ o!)e! to ,e$e!ate the

s*$thes#s !e o!ts+ The RTL sche"at#c fo! the "u%t# 0#t f%# f%o has sho'$ #$ the

0e%o' f#,u!e+

The fo%%o'#$, f#,u!e sho's the s*$thes#s !esu%ts of )ou0%e 0#t f%# -f%o +

De t of ECE& VLSI 7 ES& GVIC @


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Fig ,.(: shows s*nthesis o%tp%t of m%lti bit flip-flop.

Fo! a))e! 'he$ c%oc( %ea)#$, e),e #$ ut #s @ a$) the t!a#%#$, e),e #$ ut #s 5&

!eset #$ ut #s 5& #$ ut fo! a #s @@@@@@@ a$) the #$ ut fo! 0 #s @5555555+The out ut #s

@5555555 as sho'$ #$ the F#,+ +


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Fig. ,.,: Sim%lation o%tp%t of adder

Fo! e2a" %e #f the #$ ut #s @@@@@55 fo! a& #f the #$ ut #s @@@@@55 fo! 0 the

out ut '#%% 0e @@@@@55@ a$) the c%oc( s#,$a% #s ,# e$ to the f%# f%o that #s !e1u#!e)

to sho' the out ut+

That the $u"0e! of o$es #$ that out ut 'as 6& th#s $u"0e! of o$es ca$ 0e

sho'$ 0* the e$ #$ ut #$ the co)e+ B* see#$, that e$ a%ue the co"0#$at#o$ ta0%e '#%%

act# ates a$) co!!es o$)#$, !e,#ste!s '#%% 0e e$a0%e)+ That #s the !e"a#$#$, f%# f%o s

a!e #$ )eact# at#o$ "o)e+ B* th#s 'e ca$ !e)uce the o'e! that #s !e1u#!e) fo! the

o e!at#o$ #$ the s*ste" o$ ch# +

A,a#$ the a%ues #$ the !e,#ste!s 'e!e !esett%e) a$) a,a#$ ,# e$ as a #$ ut to

@@@@@@@@ a$) 0 #$ ut as @@@55555+ The$ the out ut 'as @@@55555& s#"#%a!%* the e$

out ut 'as 0ecause the $o of o$es #$ the out ut #s + The$ #t chec(s the co"0#$at#o$

fo! a$) the$ e$a0%es the 5 0#t a$) < 0#t !e,#ste!s #$ o!)e! to sto!e f# e 0#t )ata+ B*

th#s 'e ca$ !e)uce the o'e! that #s !e1u#!e) fo! the o e!at#o$ #$ the s*ste" o$ ch# +

Whe$ the s*$thes#s has )o$e fo! 5&6&;&< 0#t f%# -f%o s the s*$thes#s !e o!t has

a$a%*3e) a$) ,# e$ the co" a!#so$ ta0%e 0e%o'+



53/55


F%# -F%o T* e De%a*.$s/ C%oc( Po'e!.W/

5-0#t + ;5 @+@56?

6-0#t + ;5 @+@56?


54/55


Th#s !o ect has !o ose) a "etho)o%o,* fo! f%# -f%o su0st#tut#o$ fo! o'e!

!e)uct#o$ #$ )#,#ta% #$te,!ate) c#!cu#t )es#,$+ The s*ste" of f%# -f%o su0st#tut#o$s #s

!e%*#$, u o$ the co"0#$at#o$ ta0%e& 'h#ch !eco!)s the co$$ect#o$s a"o$, the f%# -

f%o t* es+ B* the !u%es of su0st#tut#o$s f!o" the co"0#$at#o$ ta0%e& the

#$co" !ehe$s#0%e co"0#$at#o$s of f%# -fa#%u!es 'o$8t 0e #e'e) as that !e)uct#o$s

e2ecut#o$ t#"e+ Othe! tha$ o'e! !e)uct#o$& the )est#$at#o$ of "#$#"#3#$, the

a,,!e,ate '#!e %e$,th %#(e'#se co$s#)e!e) to the e2 e$se ca ac#t*+ The Ve!#%o, sou!ce

co)e ha) !o)uce) fo! the a %#cat#o$ "o)u%e as #$)#cate) #$ a0o e a!eas a$)

s#"u%ate) ut#%#3#$, the Is#" test s*ste"+ The s#$,%e 0#t a$) "u%t#0#t f%# -f%o s sou!ce

co)e a))#t#o$a%%* %a$$e) a$) !e !o)uce) a$) co"0#$e) ut#%#3#$, J#%#$2 ISE Des#,$

su#te+ Th#s "etho)o%o,* ca$ 0e a !o !#ate fo! a$* c#!cu#t co" !#s#$, of a!#ous f%# -

f%o s %#(e cou$te!s !e,#ste!s+

REFERENCES



55/55


95: Ya-T#$, Sh*u& [a#-M#$, L#$& Chu$-Po ua$,& Che$,-Wu L#$& Y#$,- u L#$&

a$) Soo$- [*h Cha$,& 6@5;& \Effect# e a$) eff#c#e$t a !oach fo! o'e! !e)uct#o$

0* us#$, Mu%t#-0#t F%# -f%o s #$ IEEE t!a$sact#o$s o$ VLSI& o%+ 65& $o+ >=+

9 : L+ Che$& A+ u$,& +-M+ Che$& E+ Y+-W+ Tsa#& S+- + Che$& M+- + u& a$) C+-

C+Che$& Us#$, "u%t#-0#t f%# -f%o fo! c%oc( o'e! sa #$, 0* Des#,$

Co" #%e!& #$ P!oc+ S*$o s*s Use! G!ou .SNUG/& 6@5@+9?: [+-T+ Ya$ a$) +-W+ Che$& Co$st!uct#o$ of co$st!a#$e) "u%t#-0#t f%# -f%o s fo!

c%oc( o'e! !e)uct#o$& #$ P!oc+ ICGCS& + ? K ?=& 6@5@+

9=: S+- + Wa$,& Y+-Y+ L#a$,& T+-Y+ uo& a$) W+- + Ma(& Po'e!-)!# e$ f%# -

f%o "e!,#$, a$) !e%ocat#o$& #$ P!oc+ ISPD& + 5@?K55: [+ M+ Ra0ae*& A+ Cha$)!a(asa$& a$) B+ N#(o%#c& 6@@;& D#,#ta% I$te,!ate)

C#!cu#ts A Des#,$ Pe!s ect# e& 6$) e)+ U e! Sa))%e R# e!& N[ P!e$t#ce- a%%

95@: Y+ !etch"e!& 6@@5& Us#$, "u%t#-0#t !e,#ste! #$fe!e$ce to sa e a!ea a$) o'e!&

EE T#"es As#a+

Documents

Reduction of Power by Using Multi-bit Flip-flops for Vlsi Applications